Re: [PATCH v3 9/9] arm64: tegra: Enable GPCDMA and add iommu-map in Tegra264

[Jon Hunter <jonathanh@nvidia.com>]

On 16/03/2026 17:18, Akhil R wrote:
> Remove the fallback compatible string "nvidia,tegra186-gpcdma" and
> enable GPCDMA in Tegra264. Tegra186 compatible cannot work on
> Tegra264 because of the register offset changes and absence of
> the reset property.
> 
> Also add the iommu-map property so that each channel uses a separate
> stream ID and gets its own IOMMU domain for memory.
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> ---
>   arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 ++++
>   arch/arm64/boot/dts/nvidia/tegra264.dtsi       | 3 ++-
>   2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> index 7e2c3e66c2ab..c8beb616964a 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> @@ -16,6 +16,10 @@ serial@c4e0000 {
>   		serial@c5a0000 {
>   			status = "okay";
>   		};
> +
> +		dma-controller@8400000 {
> +			status = "okay";
> +		};
>   	};

We need to fix the ordering here, because we order these according to 
the address. Thierry may be able to fix this when applying.

>   
>   	bus@8100000000 {
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 24cc2c51a272..b2f20d4b567a 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3208,7 +3208,7 @@ agic_page5: interrupt-controller@99b0000 {
>   		};
>   
>   		gpcdma: dma-controller@8400000 {
> -			compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";
> +			compatible = "nvidia,tegra264-gpcdma";

Ideally this would be a separate patch with the appropriate fixes tag, 
however, there is a dependency on patch 2/9. Really patch 2/9 should be 
the first patch in the series as this is a fix and preparing for 
enabling Tegra264 support. And this part should probably be patch 2/9. 
Then this patch that enables this, the final one in the series.

>   			reg = <0x0 0x08400000 0x0 0x210000>;
>   			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
> @@ -3244,6 +3244,7 @@ gpcdma: dma-controller@8400000 {
>   				     <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
>   			#dma-cells = <1>;
>   			iommus = <&smmu1 0x00000800>;
> +			iommu-map = <1 &smmu1 0x801 31>;
>   			dma-coherent;
>   			dma-channel-mask = <0xfffffffe>;
>   			status = "disabled";

-- 
nvpublic