* [RFC PATCH] Docs: move more driver,device related docs into drivers dir follows kernel source
From: Alex Shi @ 2019-07-12 6:10 UTC (permalink / raw)
Cc: Alex Shi, linux-pci-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ,
drbd-dev-cunTk1MwBs8qoQakbn7OcQ,
linux-block-u79uwXL29TY76Z2rM5mHXA, nbd-2H2hN8V1XRtuHlm7Suoebg,
linux-ide-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-crypto-u79uwXL29TY76Z2rM5mHXA,
keyrings-u79uwXL29TY76Z2rM5mHXA,
linux-wireless-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linaro-mm-sig-cunTk1MwBs8s++Sfvej+rw,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-edac-u79uwXL29TY76Z2rM5mHXA,
linux-fpga-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-s390-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Could I have a proposal to move the following driver/devices dirs which
under Documentation/ into Documentation/drivers/, follows kernel source
acpi backlight bus cpu-freq device-mapper driver-model gpio hid
ide leds md memory mmc nfc nvmem pcmcia scsi sound watchdog
auxdisplay blockdev cdrom crypto driver-api fpga gpu
i2c infiniband lightnvm media misc mtd nvdimm PCI apidio
serial usb
More docs and dirs could move into this dir later, that could make
Documenation dir much more clear, and don't cause trouble to find them.
If it's acceptable, we could do docs pointer redirect further.
Signed-off-by: Alex Shi <alex.shi-KPsoFbNs7GizrGE5bRqYAgC/G2K4zDHf@public.gmane.org>
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
Cc: drbd-dev-cunTk1MwBs8qoQakbn7OcQ@public.gmane.org
Cc: linux-block-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: nbd-2H2hN8V1XRtuHlm7Suoebg@public.gmane.org
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-crypto-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: keyrings-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: linaro-mm-sig-cunTk1MwBs8s++Sfvej+rw@public.gmane.org
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-edac-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-fpga-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-s390-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: intel-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: xen-devel-GuqFBffKawtpuQazS67q72D2FQJk+8+b@public.gmane.org
Cc: linux-input-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-leds-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-scsi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: dc395x-rWtB/k1P5JpAfugRpC6u6w@public.gmane.org
Cc: esc.storagedev-dzo6w/eZyo2tG0bUXCXiUA@public.gmane.org
Cc: megaraidlinux.pdl-dY08KVG/lbpWk0Htik3J/w@public.gmane.org
Cc: osst-users-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
Cc: linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Documentation/{ => drivers}/PCI/MSI-HOWTO.txt | 0
Documentation/{ => drivers}/PCI/PCIEBUS-HOWTO.txt | 0
Documentation/{ => drivers}/PCI/acpi-info.txt | 0
.../{ => drivers}/PCI/endpoint/function/binding/pci-test.txt | 0
Documentation/{ => drivers}/PCI/endpoint/pci-endpoint-cfs.txt | 0
Documentation/{ => drivers}/PCI/endpoint/pci-endpoint.txt | 0
Documentation/{ => drivers}/PCI/endpoint/pci-test-function.txt | 0
Documentation/{ => drivers}/PCI/endpoint/pci-test-howto.txt | 0
Documentation/{ => drivers}/PCI/pci-error-recovery.txt | 0
Documentation/{ => drivers}/PCI/pci-iov-howto.txt | 0
Documentation/{ => drivers}/PCI/pci.txt | 0
Documentation/{ => drivers}/PCI/pcieaer-howto.txt | 0
Documentation/{ => drivers}/acpi/dsd/leds.txt | 0
Documentation/{ => drivers}/auxdisplay/cfag12864b | 0
Documentation/{ => drivers}/auxdisplay/ks0108 | 0
Documentation/{ => drivers}/auxdisplay/lcd-panel-cgram.txt | 0
Documentation/{ => drivers}/backlight/lp855x-driver.txt | 0
.../{ => drivers}/blockdev/drbd/DRBD-8.3-data-packets.svg | 0
Documentation/{ => drivers}/blockdev/drbd/DRBD-data-packets.svg | 0
Documentation/{ => drivers}/blockdev/drbd/README.txt | 0
Documentation/{ => drivers}/blockdev/drbd/conn-states-8.dot | 0
Documentation/{ => drivers}/blockdev/drbd/data-structure-v9.txt | 0
Documentation/{ => drivers}/blockdev/drbd/disk-states-8.dot | 0
.../blockdev/drbd/drbd-connection-state-overview.dot | 0
Documentation/{ => drivers}/blockdev/drbd/node-states-8.dot | 0
Documentation/{ => drivers}/blockdev/floppy.txt | 0
Documentation/{ => drivers}/blockdev/nbd.txt | 0
Documentation/{ => drivers}/blockdev/paride.txt | 0
Documentation/{ => drivers}/blockdev/ramdisk.txt | 0
Documentation/{ => drivers}/blockdev/zram.txt | 0
Documentation/{bus-devices => drivers/bus}/ti-gpmc.txt | 0
Documentation/{ => drivers}/cdrom/cdrom-standard.rst | 0
Documentation/{ => drivers}/cdrom/ide-cd.rst | 0
Documentation/{ => drivers}/cdrom/index.rst | 0
Documentation/{ => drivers}/cdrom/packet-writing.rst | 0
Documentation/{ => drivers}/cpu-freq/amd-powernow.txt | 0
Documentation/{ => drivers}/cpu-freq/core.txt | 0
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Documentation/{ => drivers}/cpu-freq/index.txt | 0
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Documentation/{ => drivers}/crypto/api-intro.txt | 0
Documentation/{ => drivers}/crypto/api-kpp.rst | 0
Documentation/{ => drivers}/crypto/api-rng.rst | 0
Documentation/{ => drivers}/crypto/api-samples.rst | 0
Documentation/{ => drivers}/crypto/api-skcipher.rst | 0
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Documentation/{ => drivers}/crypto/architecture.rst | 0
Documentation/{ => drivers}/crypto/asymmetric-keys.txt | 0
Documentation/{ => drivers}/crypto/async-tx-api.txt | 0
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Documentation/{ => drivers}/crypto/crypto_engine.rst | 0
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Documentation/{ => drivers}/crypto/intro.rst | 0
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.../{ => drivers}/driver-api/80211/mac80211-advanced.rst | 0
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.../{ => drivers}/driver-api/firmware/direct-fs-lookup.rst | 0
.../{ => drivers}/driver-api/firmware/fallback-mechanisms.rst | 0
.../{ => drivers}/driver-api/firmware/firmware_cache.rst | 0
.../{ => drivers}/driver-api/firmware/fw_search_path.rst | 0
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.../{ => drivers}/driver-api/firmware/other_interfaces.rst | 0
.../{ => drivers}/driver-api/firmware/request_firmware.rst | 0
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Documentation/{ => drivers}/driver-api/frame-buffer.rst | 0
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Documentation/{ => drivers}/driver-api/i2c.rst | 0
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Documentation/{ => drivers}/driver-api/i3c/index.rst | 0
Documentation/{ => drivers}/driver-api/i3c/master-driver-api.rst | 0
Documentation/{ => drivers}/driver-api/i3c/protocol.rst | 0
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Documentation/{ => drivers}/driver-api/iio/triggered-buffers.rst | 0
Documentation/{ => drivers}/driver-api/iio/triggers.rst | 0
Documentation/{ => drivers}/driver-api/index.rst | 0
Documentation/{ => drivers}/driver-api/infrastructure.rst | 0
Documentation/{ => drivers}/driver-api/input.rst | 0
Documentation/{ => drivers}/driver-api/libata.rst | 0
Documentation/{ => drivers}/driver-api/message-based.rst | 0
Documentation/{ => drivers}/driver-api/misc_devices.rst | 0
Documentation/{ => drivers}/driver-api/miscellaneous.rst | 0
Documentation/{ => drivers}/driver-api/mtdnand.rst | 0
Documentation/{ => drivers}/driver-api/pci/index.rst | 0
Documentation/{ => drivers}/driver-api/pci/p2pdma.rst | 0
Documentation/{ => drivers}/driver-api/pci/pci.rst | 0
Documentation/{ => drivers}/driver-api/pinctl.rst | 0
Documentation/{ => drivers}/driver-api/pm/conf.py | 0
Documentation/{ => drivers}/driver-api/pm/cpuidle.rst | 0
Documentation/{ => drivers}/driver-api/pm/devices.rst | 0
Documentation/{ => drivers}/driver-api/pm/index.rst | 0
Documentation/{ => drivers}/driver-api/pm/notifiers.rst | 0
Documentation/{ => drivers}/driver-api/pm/types.rst | 0
Documentation/{ => drivers}/driver-api/pps.rst | 0
Documentation/{ => drivers}/driver-api/ptp.rst | 0
Documentation/{ => drivers}/driver-api/rapidio.rst | 0
Documentation/{ => drivers}/driver-api/regulator.rst | 0
Documentation/{ => drivers}/driver-api/s390-drivers.rst | 0
Documentation/{ => drivers}/driver-api/scsi.rst | 0
Documentation/{ => drivers}/driver-api/slimbus.rst | 0
Documentation/{ => drivers}/driver-api/sound.rst | 0
.../{ => drivers}/driver-api/soundwire/error_handling.rst | 0
Documentation/{ => drivers}/driver-api/soundwire/index.rst | 0
Documentation/{ => drivers}/driver-api/soundwire/locking.rst | 0
Documentation/{ => drivers}/driver-api/soundwire/stream.rst | 0
Documentation/{ => drivers}/driver-api/soundwire/summary.rst | 0
Documentation/{ => drivers}/driver-api/spi.rst | 0
Documentation/{ => drivers}/driver-api/target.rst | 0
Documentation/{ => drivers}/driver-api/uio-howto.rst | 0
Documentation/{ => drivers}/driver-api/usb/URB.rst | 0
Documentation/{ => drivers}/driver-api/usb/anchors.rst | 0
Documentation/{ => drivers}/driver-api/usb/bulk-streams.rst | 0
Documentation/{ => drivers}/driver-api/usb/callbacks.rst | 0
Documentation/{ => drivers}/driver-api/usb/dma.rst | 0
Documentation/{ => drivers}/driver-api/usb/dwc3.rst | 0
Documentation/{ => drivers}/driver-api/usb/error-codes.rst | 0
Documentation/{ => drivers}/driver-api/usb/gadget.rst | 0
Documentation/{ => drivers}/driver-api/usb/hotplug.rst | 0
Documentation/{ => drivers}/driver-api/usb/index.rst | 0
Documentation/{ => drivers}/driver-api/usb/persist.rst | 0
Documentation/{ => drivers}/driver-api/usb/power-management.rst | 0
Documentation/{ => drivers}/driver-api/usb/typec.rst | 0
Documentation/{ => drivers}/driver-api/usb/typec_bus.rst | 0
Documentation/{ => drivers}/driver-api/usb/usb.rst | 0
Documentation/{ => drivers}/driver-api/usb/usb3-debug-port.rst | 0
.../{ => drivers}/driver-api/usb/writing_musb_glue_layer.rst | 0
Documentation/{ => drivers}/driver-api/usb/writing_usb_driver.rst | 0
Documentation/{ => drivers}/driver-api/vme.rst | 0
Documentation/{ => drivers}/driver-api/w1.rst | 0
Documentation/{ => drivers}/driver-model/binding.txt | 0
Documentation/{ => drivers}/driver-model/bus.txt | 0
Documentation/{ => drivers}/driver-model/class.txt | 0
Documentation/{ => drivers}/driver-model/design-patterns.txt | 0
Documentation/{ => drivers}/driver-model/device.txt | 0
Documentation/{ => drivers}/driver-model/devres.txt | 0
Documentation/{ => drivers}/driver-model/driver.txt | 0
Documentation/{ => drivers}/driver-model/overview.txt | 0
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Documentation/{ => drivers}/driver-model/porting.txt | 0
Documentation/{ => drivers}/fpga/dfl.rst | 0
Documentation/{ => drivers}/fpga/index.rst | 0
Documentation/{ => drivers}/gpio/index.rst | 0
Documentation/{ => drivers}/gpio/sysfs.rst | 0
Documentation/{ => drivers}/gpu/afbc.rst | 0
Documentation/{ => drivers}/gpu/amdgpu-dc.rst | 0
Documentation/{ => drivers}/gpu/amdgpu.rst | 0
Documentation/{ => drivers}/gpu/bridge/dw-hdmi.rst | 0
Documentation/{ => drivers}/gpu/conf.py | 0
Documentation/{ => drivers}/gpu/dp-mst/topology-figure-1.dot | 0
Documentation/{ => drivers}/gpu/dp-mst/topology-figure-2.dot | 0
Documentation/{ => drivers}/gpu/dp-mst/topology-figure-3.dot | 0
Documentation/{ => drivers}/gpu/drivers.rst | 0
Documentation/{ => drivers}/gpu/drm-client.rst | 0
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Documentation/{ => drivers}/gpu/drm-kms.rst | 0
Documentation/{ => drivers}/gpu/drm-mm.rst | 0
Documentation/{ => drivers}/gpu/drm-uapi.rst | 0
Documentation/{ => drivers}/gpu/i915.rst | 0
Documentation/{ => drivers}/gpu/index.rst | 0
Documentation/{ => drivers}/gpu/introduction.rst | 0
Documentation/{ => drivers}/gpu/kms-properties.csv | 0
Documentation/{ => drivers}/gpu/komeda-kms.rst | 0
Documentation/{ => drivers}/gpu/meson.rst | 0
Documentation/{ => drivers}/gpu/msm-crash-dump.rst | 0
Documentation/{ => drivers}/gpu/pl111.rst | 0
Documentation/{ => drivers}/gpu/tegra.rst | 0
Documentation/{ => drivers}/gpu/tinydrm.rst | 0
Documentation/{ => drivers}/gpu/todo.rst | 0
Documentation/{ => drivers}/gpu/tve200.rst | 0
Documentation/{ => drivers}/gpu/v3d.rst | 0
Documentation/{ => drivers}/gpu/vc4.rst | 0
Documentation/{ => drivers}/gpu/vga-switcheroo.rst | 0
Documentation/{ => drivers}/gpu/vgaarbiter.rst | 0
Documentation/{ => drivers}/gpu/vkms.rst | 0
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Documentation/{ => drivers}/hid/hid-sensor.txt | 0
Documentation/{ => drivers}/hid/hid-transport.txt | 0
Documentation/{ => drivers}/hid/hiddev.txt | 0
Documentation/{ => drivers}/hid/hidraw.txt | 0
Documentation/{ => drivers}/hid/intel-ish-hid.txt | 0
Documentation/{ => drivers}/hid/uhid.txt | 0
Documentation/{ => drivers}/i2c/DMA-considerations | 0
Documentation/{ => drivers}/i2c/busses/i2c-ali1535 | 0
Documentation/{ => drivers}/i2c/busses/i2c-ali1563 | 0
Documentation/{ => drivers}/i2c/busses/i2c-ali15x3 | 0
Documentation/{ => drivers}/i2c/busses/i2c-amd-mp2 | 0
Documentation/{ => drivers}/i2c/busses/i2c-amd756 | 0
Documentation/{ => drivers}/i2c/busses/i2c-amd8111 | 0
Documentation/{ => drivers}/i2c/busses/i2c-diolan-u2c | 0
Documentation/{ => drivers}/i2c/busses/i2c-i801 | 0
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Documentation/{ => drivers}/i2c/busses/i2c-nforce2 | 0
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Documentation/{ => drivers}/i2c/busses/i2c-parport | 0
Documentation/{ => drivers}/i2c/busses/i2c-parport-light | 0
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Documentation/{ => drivers}/i2c/fault-codes | 0
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Documentation/{ => drivers}/sound/cards/serial-u16550.rst | 0
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.../{ => drivers}/sound/kernel-api/writing-an-alsa-driver.rst | 0
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Documentation/{ => drivers}/sound/soc/pops-clicks.rst | 0
Documentation/{ => drivers}/usb/CREDITS | 0
Documentation/{ => drivers}/usb/WUSB-Design-overview.txt | 0
Documentation/{ => drivers}/usb/acm.txt | 0
Documentation/{ => drivers}/usb/authorization.txt | 0
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Documentation/{ => drivers}/usb/dwc3.txt | 0
Documentation/{ => drivers}/usb/ehci.txt | 0
Documentation/{ => drivers}/usb/functionfs.txt | 0
Documentation/{ => drivers}/usb/gadget-testing.txt | 0
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Documentation/{ => drivers}/usb/gadget_hid.txt | 0
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Documentation/{ => drivers}/usb/linux-cdc-acm.inf | 0
Documentation/{ => drivers}/usb/linux.inf | 0
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Documentation/{ => drivers}/usb/mtouchusb.txt | 0
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Documentation/{ => drivers}/usb/rio.txt | 0
Documentation/{ => drivers}/usb/usb-help.txt | 0
Documentation/{ => drivers}/usb/usb-serial.txt | 0
Documentation/{ => drivers}/usb/usbdevfs-drop-permissions.c | 0
Documentation/{ => drivers}/usb/usbip_protocol.txt | 0
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Documentation/{ => drivers}/watchdog/watchdog-parameters.rst | 0
Documentation/{ => drivers}/watchdog/watchdog-pm.rst | 0
Documentation/{ => drivers}/watchdog/wdt.rst | 0
1079 files changed, 0 insertions(+), 0 deletions(-)
rename Documentation/{ => drivers}/PCI/MSI-HOWTO.txt (100%)
rename Documentation/{ => drivers}/PCI/PCIEBUS-HOWTO.txt (100%)
rename Documentation/{ => drivers}/PCI/acpi-info.txt (100%)
rename Documentation/{ => drivers}/PCI/endpoint/function/binding/pci-test.txt (100%)
rename Documentation/{ => drivers}/PCI/endpoint/pci-endpoint-cfs.txt (100%)
rename Documentation/{ => drivers}/PCI/endpoint/pci-endpoint.txt (100%)
rename Documentation/{ => drivers}/PCI/endpoint/pci-test-function.txt (100%)
rename Documentation/{ => drivers}/PCI/endpoint/pci-test-howto.txt (100%)
rename Documentation/{ => drivers}/PCI/pci-error-recovery.txt (100%)
rename Documentation/{ => drivers}/PCI/pci-iov-howto.txt (100%)
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rename Documentation/{ => drivers}/media/v4l-drivers/cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/cpia2.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/cx18.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/cx2341x.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/cx23885-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/cx88-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/cx88.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/davinci-vpbe.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/em28xx-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/fimc.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/fourcc.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/gspca-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/imx.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/imx7.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/index.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/ipu3.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/ivtv-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/ivtv.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/max2175.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/meye.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/omap3isp.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/omap4_camera.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/philips.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/pvrusb2.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/pxa_camera.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/qcom_camss.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/qcom_camss_8x96_graph.dot (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/qcom_camss_graph.dot (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/radiotrack.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/rcar-fdp1.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/saa7134-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/saa7134.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/saa7164-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/sh_mobile_ceu_camera.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/si470x.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/si4713.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/si476x.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/soc-camera.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/tm6000-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/tuner-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/tuners.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/usbvision-cardlist.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/uvcvideo.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/v4l-with-ir.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/vimc.dot (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/vimc.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/vivid.rst (100%)
rename Documentation/{ => drivers}/media/v4l-drivers/zr364xx.rst (100%)
rename Documentation/{ => drivers}/media/video.h.rst.exceptions (100%)
rename Documentation/{ => drivers}/media/videodev2.h.rst.exceptions (100%)
rename Documentation/{memory-devices => drivers/memory}/ti-emif.txt (100%)
rename Documentation/{misc-devices => drivers/misc}/ad525x_dpot.txt (100%)
rename Documentation/{misc-devices => drivers/misc}/apds990x.txt (100%)
rename Documentation/{misc-devices => drivers/misc}/bh1770glc.txt (100%)
rename Documentation/{misc-devices => drivers/misc}/c2port.txt (100%)
rename Documentation/{misc-devices => drivers/misc}/eeprom (100%)
rename Documentation/{misc-devices => drivers/misc}/ibmvmc.rst (100%)
rename Documentation/{misc-devices => drivers/misc}/ics932s401 (100%)
rename Documentation/{misc-devices => drivers/misc}/index.rst (100%)
rename Documentation/{misc-devices => drivers/misc}/isl29003 (100%)
rename Documentation/{misc-devices => drivers/misc}/lis3lv02d (100%)
rename Documentation/{misc-devices => drivers/misc}/max6875 (100%)
rename Documentation/{misc-devices => drivers/misc}/mei/mei-client-bus.txt (100%)
rename Documentation/{misc-devices => drivers/misc}/mei/mei.txt (100%)
rename Documentation/{misc-devices => drivers/misc}/pci-endpoint-test.txt (100%)
rename Documentation/{misc-devices => drivers/misc}/spear-pcie-gadget.txt (100%)
rename Documentation/{ => drivers}/mmc/mmc-async-req.txt (100%)
rename Documentation/{ => drivers}/mmc/mmc-dev-attrs.txt (100%)
rename Documentation/{ => drivers}/mmc/mmc-dev-parts.txt (100%)
rename Documentation/{ => drivers}/mmc/mmc-tools.txt (100%)
rename Documentation/{ => drivers}/mtd/intel-spi.txt (100%)
rename Documentation/{ => drivers}/mtd/nand_ecc.txt (100%)
rename Documentation/{ => drivers}/mtd/spi-nor.txt (100%)
rename Documentation/{ => drivers}/nfc/nfc-hci.txt (100%)
rename Documentation/{ => drivers}/nfc/nfc-pn544.txt (100%)
rename Documentation/{ => drivers}/nvdimm/btt.txt (100%)
rename Documentation/{ => drivers}/nvdimm/nvdimm.txt (100%)
rename Documentation/{ => drivers}/nvdimm/security.txt (100%)
rename Documentation/{ => drivers}/nvmem/nvmem.txt (100%)
rename Documentation/{ => drivers}/pcmcia/devicetable.rst (100%)
rename Documentation/{ => drivers}/pcmcia/driver-changes.rst (100%)
rename Documentation/{ => drivers}/pcmcia/driver.rst (100%)
rename Documentation/{ => drivers}/pcmcia/index.rst (100%)
rename Documentation/{ => drivers}/pcmcia/locking.rst (100%)
rename Documentation/{ => drivers}/rapidio/mport_cdev.txt (100%)
rename Documentation/{ => drivers}/rapidio/rapidio.txt (100%)
rename Documentation/{ => drivers}/rapidio/rio_cm.txt (100%)
rename Documentation/{ => drivers}/rapidio/sysfs.txt (100%)
rename Documentation/{ => drivers}/rapidio/tsi721.txt (100%)
rename Documentation/{ => drivers}/scsi/53c700.txt (100%)
rename Documentation/{ => drivers}/scsi/BusLogic.txt (100%)
rename Documentation/{ => drivers}/scsi/ChangeLog.arcmsr (100%)
rename Documentation/{ => drivers}/scsi/ChangeLog.ips (100%)
rename Documentation/{ => drivers}/scsi/ChangeLog.lpfc (100%)
rename Documentation/{ => drivers}/scsi/ChangeLog.megaraid (100%)
rename Documentation/{ => drivers}/scsi/ChangeLog.megaraid_sas (100%)
rename Documentation/{ => drivers}/scsi/ChangeLog.ncr53c8xx (100%)
rename Documentation/{ => drivers}/scsi/ChangeLog.sym53c8xx (100%)
rename Documentation/{ => drivers}/scsi/ChangeLog.sym53c8xx_2 (100%)
rename Documentation/{ => drivers}/scsi/FlashPoint.txt (100%)
rename Documentation/{ => drivers}/scsi/LICENSE.FlashPoint (100%)
rename Documentation/{ => drivers}/scsi/LICENSE.qla2xxx (100%)
rename Documentation/{ => drivers}/scsi/LICENSE.qla4xxx (100%)
rename Documentation/{ => drivers}/scsi/NinjaSCSI.txt (100%)
rename Documentation/{ => drivers}/scsi/aacraid.txt (100%)
rename Documentation/{ => drivers}/scsi/advansys.txt (100%)
rename Documentation/{ => drivers}/scsi/aha152x.txt (100%)
rename Documentation/{ => drivers}/scsi/aic79xx.txt (100%)
rename Documentation/{ => drivers}/scsi/aic7xxx.txt (100%)
rename Documentation/{ => drivers}/scsi/arcmsr_spec.txt (100%)
rename Documentation/{ => drivers}/scsi/bfa.txt (100%)
rename Documentation/{ => drivers}/scsi/bnx2fc.txt (100%)
rename Documentation/{ => drivers}/scsi/cxgb3i.txt (100%)
rename Documentation/{ => drivers}/scsi/dc395x.txt (100%)
rename Documentation/{ => drivers}/scsi/dpti.txt (100%)
rename Documentation/{ => drivers}/scsi/g_NCR5380.txt (100%)
rename Documentation/{ => drivers}/scsi/hpsa.txt (100%)
rename Documentation/{ => drivers}/scsi/hptiop.txt (100%)
rename Documentation/{ => drivers}/scsi/libsas.txt (100%)
rename Documentation/{ => drivers}/scsi/link_power_management_policy.txt (100%)
rename Documentation/{ => drivers}/scsi/lpfc.txt (100%)
rename Documentation/{ => drivers}/scsi/megaraid.txt (100%)
rename Documentation/{ => drivers}/scsi/ncr53c8xx.txt (100%)
rename Documentation/{ => drivers}/scsi/osst.txt (100%)
rename Documentation/{ => drivers}/scsi/ppa.txt (100%)
rename Documentation/{ => drivers}/scsi/qlogicfas.txt (100%)
rename Documentation/{ => drivers}/scsi/scsi-changer.txt (100%)
rename Documentation/{ => drivers}/scsi/scsi-generic.txt (100%)
rename Documentation/{ => drivers}/scsi/scsi-parameters.txt (100%)
rename Documentation/{ => drivers}/scsi/scsi.txt (100%)
rename Documentation/{ => drivers}/scsi/scsi_eh.txt (100%)
rename Documentation/{ => drivers}/scsi/scsi_fc_transport.txt (100%)
rename Documentation/{ => drivers}/scsi/scsi_mid_low_api.txt (100%)
rename Documentation/{ => drivers}/scsi/scsi_transport_srp/Makefile (100%)
rename Documentation/{ => drivers}/scsi/scsi_transport_srp/rport_state_diagram.dot (100%)
rename Documentation/{ => drivers}/scsi/sd-parameters.txt (100%)
rename Documentation/{ => drivers}/scsi/smartpqi.txt (100%)
rename Documentation/{ => drivers}/scsi/st.txt (100%)
rename Documentation/{ => drivers}/scsi/sym53c500_cs.txt (100%)
rename Documentation/{ => drivers}/scsi/sym53c8xx_2.txt (100%)
rename Documentation/{ => drivers}/scsi/tcm_qla2xxx.txt (100%)
rename Documentation/{ => drivers}/scsi/ufs.txt (100%)
rename Documentation/{ => drivers}/scsi/wd719x.txt (100%)
rename Documentation/{ => drivers}/serial/cyclades_z.rst (100%)
rename Documentation/{ => drivers}/serial/driver.rst (100%)
rename Documentation/{ => drivers}/serial/index.rst (100%)
rename Documentation/{ => drivers}/serial/moxa-smartio.rst (100%)
rename Documentation/{ => drivers}/serial/n_gsm.rst (100%)
rename Documentation/{ => drivers}/serial/rocket.rst (100%)
rename Documentation/{ => drivers}/serial/serial-iso7816.rst (100%)
rename Documentation/{ => drivers}/serial/serial-rs485.rst (100%)
rename Documentation/{ => drivers}/serial/tty.rst (100%)
rename Documentation/{ => drivers}/sound/alsa-configuration.rst (100%)
rename Documentation/{ => drivers}/sound/cards/audigy-mixer.rst (100%)
rename Documentation/{ => drivers}/sound/cards/audiophile-usb.rst (100%)
rename Documentation/{ => drivers}/sound/cards/bt87x.rst (100%)
rename Documentation/{ => drivers}/sound/cards/cmipci.rst (100%)
rename Documentation/{ => drivers}/sound/cards/emu10k1-jack.rst (100%)
rename Documentation/{ => drivers}/sound/cards/hdspm.rst (100%)
rename Documentation/{ => drivers}/sound/cards/img-spdif-in.rst (100%)
rename Documentation/{ => drivers}/sound/cards/index.rst (100%)
rename Documentation/{ => drivers}/sound/cards/joystick.rst (100%)
rename Documentation/{ => drivers}/sound/cards/maya44.rst (100%)
rename Documentation/{ => drivers}/sound/cards/mixart.rst (100%)
rename Documentation/{ => drivers}/sound/cards/multisound.sh (100%)
rename Documentation/{ => drivers}/sound/cards/sb-live-mixer.rst (100%)
rename Documentation/{ => drivers}/sound/cards/serial-u16550.rst (100%)
rename Documentation/{ => drivers}/sound/cards/via82xx-mixer.rst (100%)
rename Documentation/{ => drivers}/sound/conf.py (100%)
rename Documentation/{ => drivers}/sound/designs/channel-mapping-api.rst (100%)
rename Documentation/{ => drivers}/sound/designs/compress-offload.rst (100%)
rename Documentation/{ => drivers}/sound/designs/control-names.rst (100%)
rename Documentation/{ => drivers}/sound/designs/index.rst (100%)
rename Documentation/{ => drivers}/sound/designs/jack-controls.rst (100%)
rename Documentation/{ => drivers}/sound/designs/oss-emulation.rst (100%)
rename Documentation/{ => drivers}/sound/designs/powersave.rst (100%)
rename Documentation/{ => drivers}/sound/designs/procfile.rst (100%)
rename Documentation/{ => drivers}/sound/designs/seq-oss.rst (100%)
rename Documentation/{ => drivers}/sound/designs/timestamping.rst (100%)
rename Documentation/{ => drivers}/sound/designs/tracepoints.rst (100%)
rename Documentation/{ => drivers}/sound/hd-audio/controls.rst (100%)
rename Documentation/{ => drivers}/sound/hd-audio/dp-mst.rst (100%)
rename Documentation/{ => drivers}/sound/hd-audio/index.rst (100%)
rename Documentation/{ => drivers}/sound/hd-audio/models.rst (100%)
rename Documentation/{ => drivers}/sound/hd-audio/notes.rst (100%)
rename Documentation/{ => drivers}/sound/index.rst (100%)
rename Documentation/{ => drivers}/sound/kernel-api/alsa-driver-api.rst (100%)
rename Documentation/{ => drivers}/sound/kernel-api/index.rst (100%)
rename Documentation/{ => drivers}/sound/kernel-api/writing-an-alsa-driver.rst (100%)
rename Documentation/{ => drivers}/sound/soc/clocking.rst (100%)
rename Documentation/{ => drivers}/sound/soc/codec-to-codec.rst (100%)
rename Documentation/{ => drivers}/sound/soc/codec.rst (100%)
rename Documentation/{ => drivers}/sound/soc/dai.rst (100%)
rename Documentation/{ => drivers}/sound/soc/dapm.rst (100%)
rename Documentation/{ => drivers}/sound/soc/dpcm.rst (100%)
rename Documentation/{ => drivers}/sound/soc/index.rst (100%)
rename Documentation/{ => drivers}/sound/soc/jack.rst (100%)
rename Documentation/{ => drivers}/sound/soc/machine.rst (100%)
rename Documentation/{ => drivers}/sound/soc/overview.rst (100%)
rename Documentation/{ => drivers}/sound/soc/platform.rst (100%)
rename Documentation/{ => drivers}/sound/soc/pops-clicks.rst (100%)
rename Documentation/{ => drivers}/usb/CREDITS (100%)
rename Documentation/{ => drivers}/usb/WUSB-Design-overview.txt (100%)
rename Documentation/{ => drivers}/usb/acm.txt (100%)
rename Documentation/{ => drivers}/usb/authorization.txt (100%)
rename Documentation/{ => drivers}/usb/chipidea.txt (100%)
rename Documentation/{ => drivers}/usb/dwc3.txt (100%)
rename Documentation/{ => drivers}/usb/ehci.txt (100%)
rename Documentation/{ => drivers}/usb/functionfs.txt (100%)
rename Documentation/{ => drivers}/usb/gadget-testing.txt (100%)
rename Documentation/{ => drivers}/usb/gadget_configfs.txt (100%)
rename Documentation/{ => drivers}/usb/gadget_hid.txt (100%)
rename Documentation/{ => drivers}/usb/gadget_multi.txt (100%)
rename Documentation/{ => drivers}/usb/gadget_printer.txt (100%)
rename Documentation/{ => drivers}/usb/gadget_serial.txt (100%)
rename Documentation/{ => drivers}/usb/iuu_phoenix.txt (100%)
rename Documentation/{ => drivers}/usb/linux-cdc-acm.inf (100%)
rename Documentation/{ => drivers}/usb/linux.inf (100%)
rename Documentation/{ => drivers}/usb/mass-storage.txt (100%)
rename Documentation/{ => drivers}/usb/misc_usbsevseg.txt (100%)
rename Documentation/{ => drivers}/usb/mtouchusb.txt (100%)
rename Documentation/{ => drivers}/usb/ohci.txt (100%)
rename Documentation/{ => drivers}/usb/rio.txt (100%)
rename Documentation/{ => drivers}/usb/usb-help.txt (100%)
rename Documentation/{ => drivers}/usb/usb-serial.txt (100%)
rename Documentation/{ => drivers}/usb/usbdevfs-drop-permissions.c (100%)
rename Documentation/{ => drivers}/usb/usbip_protocol.txt (100%)
rename Documentation/{ => drivers}/usb/usbmon.txt (100%)
rename Documentation/{ => drivers}/usb/wusb-cbaf (100%)
rename Documentation/{ => drivers}/watchdog/convert_drivers_to_kernel_api.rst (100%)
rename Documentation/{ => drivers}/watchdog/hpwdt.rst (100%)
rename Documentation/{ => drivers}/watchdog/index.rst (100%)
rename Documentation/{ => drivers}/watchdog/mlx-wdt.rst (100%)
rename Documentation/{ => drivers}/watchdog/pcwd-watchdog.rst (100%)
rename Documentation/{ => drivers}/watchdog/watchdog-api.rst (100%)
rename Documentation/{ => drivers}/watchdog/watchdog-kernel-api.rst (100%)
rename Documentation/{ => drivers}/watchdog/watchdog-parameters.rst (100%)
rename Documentation/{ => drivers}/watchdog/watchdog-pm.rst (100%)
rename Documentation/{ => drivers}/watchdog/wdt.rst (100%)
diff --git a/Documentation/PCI/MSI-HOWTO.txt b/Documentation/drivers/PCI/MSI-HOWTO.txt
similarity index 100%
rename from Documentation/PCI/MSI-HOWTO.txt
rename to Documentation/drivers/PCI/MSI-HOWTO.txt
diff --git a/Documentation/PCI/PCIEBUS-HOWTO.txt b/Documentation/drivers/PCI/PCIEBUS-HOWTO.txt
similarity index 100%
rename from Documentation/PCI/PCIEBUS-HOWTO.txt
rename to Documentation/drivers/PCI/PCIEBUS-HOWTO.txt
diff --git a/Documentation/PCI/acpi-info.txt b/Documentation/drivers/PCI/acpi-info.txt
similarity index 100%
rename from Documentation/PCI/acpi-info.txt
rename to Documentation/drivers/PCI/acpi-info.txt
diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.txt b/Documentation/drivers/PCI/endpoint/function/binding/pci-test.txt
similarity index 100%
rename from Documentation/PCI/endpoint/function/binding/pci-test.txt
rename to Documentation/drivers/PCI/endpoint/function/binding/pci-test.txt
diff --git a/Documentation/PCI/endpoint/pci-endpoint-cfs.txt b/Documentation/drivers/PCI/endpoint/pci-endpoint-cfs.txt
similarity index 100%
rename from Documentation/PCI/endpoint/pci-endpoint-cfs.txt
rename to Documentation/drivers/PCI/endpoint/pci-endpoint-cfs.txt
diff --git a/Documentation/PCI/endpoint/pci-endpoint.txt b/Documentation/drivers/PCI/endpoint/pci-endpoint.txt
similarity index 100%
rename from Documentation/PCI/endpoint/pci-endpoint.txt
rename to Documentation/drivers/PCI/endpoint/pci-endpoint.txt
diff --git a/Documentation/PCI/endpoint/pci-test-function.txt b/Documentation/drivers/PCI/endpoint/pci-test-function.txt
similarity index 100%
rename from Documentation/PCI/endpoint/pci-test-function.txt
rename to Documentation/drivers/PCI/endpoint/pci-test-function.txt
diff --git a/Documentation/PCI/endpoint/pci-test-howto.txt b/Documentation/drivers/PCI/endpoint/pci-test-howto.txt
similarity index 100%
rename from Documentation/PCI/endpoint/pci-test-howto.txt
rename to Documentation/drivers/PCI/endpoint/pci-test-howto.txt
diff --git a/Documentation/PCI/pci-error-recovery.txt b/Documentation/drivers/PCI/pci-error-recovery.txt
similarity index 100%
rename from Documentation/PCI/pci-error-recovery.txt
rename to Documentation/drivers/PCI/pci-error-recovery.txt
diff --git a/Documentation/PCI/pci-iov-howto.txt b/Documentation/drivers/PCI/pci-iov-howto.txt
similarity index 100%
rename from Documentation/PCI/pci-iov-howto.txt
rename to Documentation/drivers/PCI/pci-iov-howto.txt
diff --git a/Documentation/PCI/pci.txt b/Documentation/drivers/PCI/pci.txt
similarity index 100%
rename from Documentation/PCI/pci.txt
rename to Documentation/drivers/PCI/pci.txt
diff --git a/Documentation/PCI/pcieaer-howto.txt b/Documentation/drivers/PCI/pcieaer-howto.txt
similarity index 100%
rename from Documentation/PCI/pcieaer-howto.txt
rename to Documentation/drivers/PCI/pcieaer-howto.txt
diff --git a/Documentation/acpi/dsd/leds.txt b/Documentation/drivers/acpi/dsd/leds.txt
similarity index 100%
rename from Documentation/acpi/dsd/leds.txt
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diff --git a/Documentation/auxdisplay/cfag12864b b/Documentation/drivers/auxdisplay/cfag12864b
similarity index 100%
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diff --git a/Documentation/auxdisplay/ks0108 b/Documentation/drivers/auxdisplay/ks0108
similarity index 100%
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diff --git a/Documentation/auxdisplay/lcd-panel-cgram.txt b/Documentation/drivers/auxdisplay/lcd-panel-cgram.txt
similarity index 100%
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diff --git a/Documentation/backlight/lp855x-driver.txt b/Documentation/drivers/backlight/lp855x-driver.txt
similarity index 100%
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diff --git a/Documentation/blockdev/drbd/DRBD-8.3-data-packets.svg b/Documentation/drivers/blockdev/drbd/DRBD-8.3-data-packets.svg
similarity index 100%
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similarity index 100%
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similarity index 100%
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similarity index 100%
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similarity index 100%
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similarity index 100%
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similarity index 100%
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rename from Documentation/usb/gadget_multi.txt
rename to Documentation/drivers/usb/gadget_multi.txt
diff --git a/Documentation/usb/gadget_printer.txt b/Documentation/drivers/usb/gadget_printer.txt
similarity index 100%
rename from Documentation/usb/gadget_printer.txt
rename to Documentation/drivers/usb/gadget_printer.txt
diff --git a/Documentation/usb/gadget_serial.txt b/Documentation/drivers/usb/gadget_serial.txt
similarity index 100%
rename from Documentation/usb/gadget_serial.txt
rename to Documentation/drivers/usb/gadget_serial.txt
diff --git a/Documentation/usb/iuu_phoenix.txt b/Documentation/drivers/usb/iuu_phoenix.txt
similarity index 100%
rename from Documentation/usb/iuu_phoenix.txt
rename to Documentation/drivers/usb/iuu_phoenix.txt
diff --git a/Documentation/usb/linux-cdc-acm.inf b/Documentation/drivers/usb/linux-cdc-acm.inf
similarity index 100%
rename from Documentation/usb/linux-cdc-acm.inf
rename to Documentation/drivers/usb/linux-cdc-acm.inf
diff --git a/Documentation/usb/linux.inf b/Documentation/drivers/usb/linux.inf
similarity index 100%
rename from Documentation/usb/linux.inf
rename to Documentation/drivers/usb/linux.inf
diff --git a/Documentation/usb/mass-storage.txt b/Documentation/drivers/usb/mass-storage.txt
similarity index 100%
rename from Documentation/usb/mass-storage.txt
rename to Documentation/drivers/usb/mass-storage.txt
diff --git a/Documentation/usb/misc_usbsevseg.txt b/Documentation/drivers/usb/misc_usbsevseg.txt
similarity index 100%
rename from Documentation/usb/misc_usbsevseg.txt
rename to Documentation/drivers/usb/misc_usbsevseg.txt
diff --git a/Documentation/usb/mtouchusb.txt b/Documentation/drivers/usb/mtouchusb.txt
similarity index 100%
rename from Documentation/usb/mtouchusb.txt
rename to Documentation/drivers/usb/mtouchusb.txt
diff --git a/Documentation/usb/ohci.txt b/Documentation/drivers/usb/ohci.txt
similarity index 100%
rename from Documentation/usb/ohci.txt
rename to Documentation/drivers/usb/ohci.txt
diff --git a/Documentation/usb/rio.txt b/Documentation/drivers/usb/rio.txt
similarity index 100%
rename from Documentation/usb/rio.txt
rename to Documentation/drivers/usb/rio.txt
diff --git a/Documentation/usb/usb-help.txt b/Documentation/drivers/usb/usb-help.txt
similarity index 100%
rename from Documentation/usb/usb-help.txt
rename to Documentation/drivers/usb/usb-help.txt
diff --git a/Documentation/usb/usb-serial.txt b/Documentation/drivers/usb/usb-serial.txt
similarity index 100%
rename from Documentation/usb/usb-serial.txt
rename to Documentation/drivers/usb/usb-serial.txt
diff --git a/Documentation/usb/usbdevfs-drop-permissions.c b/Documentation/drivers/usb/usbdevfs-drop-permissions.c
similarity index 100%
rename from Documentation/usb/usbdevfs-drop-permissions.c
rename to Documentation/drivers/usb/usbdevfs-drop-permissions.c
diff --git a/Documentation/usb/usbip_protocol.txt b/Documentation/drivers/usb/usbip_protocol.txt
similarity index 100%
rename from Documentation/usb/usbip_protocol.txt
rename to Documentation/drivers/usb/usbip_protocol.txt
diff --git a/Documentation/usb/usbmon.txt b/Documentation/drivers/usb/usbmon.txt
similarity index 100%
rename from Documentation/usb/usbmon.txt
rename to Documentation/drivers/usb/usbmon.txt
diff --git a/Documentation/usb/wusb-cbaf b/Documentation/drivers/usb/wusb-cbaf
similarity index 100%
rename from Documentation/usb/wusb-cbaf
rename to Documentation/drivers/usb/wusb-cbaf
diff --git a/Documentation/watchdog/convert_drivers_to_kernel_api.rst b/Documentation/drivers/watchdog/convert_drivers_to_kernel_api.rst
similarity index 100%
rename from Documentation/watchdog/convert_drivers_to_kernel_api.rst
rename to Documentation/drivers/watchdog/convert_drivers_to_kernel_api.rst
diff --git a/Documentation/watchdog/hpwdt.rst b/Documentation/drivers/watchdog/hpwdt.rst
similarity index 100%
rename from Documentation/watchdog/hpwdt.rst
rename to Documentation/drivers/watchdog/hpwdt.rst
diff --git a/Documentation/watchdog/index.rst b/Documentation/drivers/watchdog/index.rst
similarity index 100%
rename from Documentation/watchdog/index.rst
rename to Documentation/drivers/watchdog/index.rst
diff --git a/Documentation/watchdog/mlx-wdt.rst b/Documentation/drivers/watchdog/mlx-wdt.rst
similarity index 100%
rename from Documentation/watchdog/mlx-wdt.rst
rename to Documentation/drivers/watchdog/mlx-wdt.rst
diff --git a/Documentation/watchdog/pcwd-watchdog.rst b/Documentation/drivers/watchdog/pcwd-watchdog.rst
similarity index 100%
rename from Documentation/watchdog/pcwd-watchdog.rst
rename to Documentation/drivers/watchdog/pcwd-watchdog.rst
diff --git a/Documentation/watchdog/watchdog-api.rst b/Documentation/drivers/watchdog/watchdog-api.rst
similarity index 100%
rename from Documentation/watchdog/watchdog-api.rst
rename to Documentation/drivers/watchdog/watchdog-api.rst
diff --git a/Documentation/watchdog/watchdog-kernel-api.rst b/Documentation/drivers/watchdog/watchdog-kernel-api.rst
similarity index 100%
rename from Documentation/watchdog/watchdog-kernel-api.rst
rename to Documentation/drivers/watchdog/watchdog-kernel-api.rst
diff --git a/Documentation/watchdog/watchdog-parameters.rst b/Documentation/drivers/watchdog/watchdog-parameters.rst
similarity index 100%
rename from Documentation/watchdog/watchdog-parameters.rst
rename to Documentation/drivers/watchdog/watchdog-parameters.rst
diff --git a/Documentation/watchdog/watchdog-pm.rst b/Documentation/drivers/watchdog/watchdog-pm.rst
similarity index 100%
rename from Documentation/watchdog/watchdog-pm.rst
rename to Documentation/drivers/watchdog/watchdog-pm.rst
diff --git a/Documentation/watchdog/wdt.rst b/Documentation/drivers/watchdog/wdt.rst
similarity index 100%
rename from Documentation/watchdog/wdt.rst
rename to Documentation/drivers/watchdog/wdt.rst
--
2.19.1.856.g8858448bb
^ permalink raw reply
* Re: [PATCH v4 15/23] drm: sti: Provide ddc symlink in hdmi connector sysfs directory
From: Benjamin Gaignard @ 2019-07-12 7:42 UTC (permalink / raw)
To: Andrzej Pietrasiewicz
Cc: Y.C. Chen, Heiko Stübner, Sam Ravnborg, Neil Armstrong,
Maxime Ripard, Ramalingam C, Joonas Lahtinen, Liviu Dudau,
ML dri-devel, Douglas Anderson, Andrzej Hajda, Thierry Reding,
Laurent Pinchart, kernel-ZGY8ohtN/8qB+jHODAdFcQ, Fabio Estevam,
Ville Syrjälä, David (ChunMing) Zhou,
moderated list:ARM/S5P EXYNOS AR..., Joonyoung Shim,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <86afdc0bca6939901870176dcf55f279f7b10a08.1562843413.git.andrzej.p-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Le jeu. 11 juil. 2019 à 13:30, Andrzej Pietrasiewicz
<andrzej.p@collabora.com> a écrit :
>
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
> ---
> drivers/gpu/drm/sti/sti_hdmi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c
> index f03d617edc4c..90f8db63c095 100644
> --- a/drivers/gpu/drm/sti/sti_hdmi.c
> +++ b/drivers/gpu/drm/sti/sti_hdmi.c
> @@ -1279,6 +1279,7 @@ static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
> drm_bridge_attach(encoder, bridge, NULL);
>
> connector->encoder = encoder;
> + drm_connector->ddc = hdmi->ddc_adapt;
>
> drm_connector = (struct drm_connector *)connector;
>
> --
> 2.17.1
>
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply
* Re: [PATCH v1] drm/modes: Skip invalid cmdline mode
From: Maxime Ripard @ 2019-07-12 8:10 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Maarten Lankhorst, Sean Paul,
Daniel Vetter, David Airlie, dri-devel, linux-tegra, linux-kernel
In-Reply-To: <de21fe78-87a6-741f-caf7-2771f6468739@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3570 bytes --]
On Thu, Jul 11, 2019 at 06:55:03PM +0300, Dmitry Osipenko wrote:
> 11.07.2019 12:03, Maxime Ripard пишет:
> > On Wed, Jul 10, 2019 at 06:05:18PM +0300, Dmitry Osipenko wrote:
> >> 10.07.2019 17:05, Maxime Ripard пишет:
> >>> On Wed, Jul 10, 2019 at 04:29:19PM +0300, Dmitry Osipenko wrote:
> >>>> This works:
> >>>>
> >>>> diff --git a/drivers/gpu/drm/drm_client_modeset.c b/drivers/gpu/drm/drm_client_modeset.c
> >>>> index 56d36779d213..e5a2f9c8f404 100644
> >>>> --- a/drivers/gpu/drm/drm_client_modeset.c
> >>>> +++ b/drivers/gpu/drm/drm_client_modeset.c
> >>>> @@ -182,6 +182,8 @@ drm_connector_pick_cmdline_mode(struct drm_connector *connector)
> >>>> mode = drm_mode_create_from_cmdline_mode(connector->dev, cmdline_mode);
> >>>> if (mode)
> >>>> list_add(&mode->head, &connector->modes);
> >>>> + else
> >>>> + cmdline_mode->specified = false;
> >>>
> >>> Hmmm, it's not clear to me why that wouldn't be the case.
> >>>
> >>> If we come back to the beginning of that function, we retrieve the
> >>> cmdline_mode buffer from the connector pointer, that will probably
> >>> have been parsed a first time using drm_mode_create_from_cmdline_mode
> >>> in drm_helper_probe_add_cmdline_mode.
> >>>
> >>> Now, I'm guessing that the issue is that in
> >>> drm_mode_parse_command_line_for_connector, if we have a named mode, we
> >>> just copy the mode over and set mode->specified.
> >>>
> >>> And we then move over to do other checks, and that's probably what
> >>> fails and returns, but our drm_cmdline_mode will have been modified.
> >>>
> >>> I'm not entirely sure how to deal with that though.
> >>>
> >>> I guess we could allocate a drm_cmdline_mode structure on the stack,
> >>> fill that, and if successful copy over its content to the one in
> >>> drm_connector. That would allow us to only change the content on
> >>> success, which is what I would expect from such a function?
> >>>
> >>> How does that sound?
> >>
> >> I now see that there is DRM_MODE_TYPE_USERDEF flag that is assigned only
> >> for the "cmdline" mode and drm_client_rotation() is the only place in
> >> DRM code that cares about whether mode is from cmdline, hence looks like
> >> it will be more correct to do the following:
> >
> > I'm still under the impression that we're dealing with workarounds of
> > a more central issue, which is that we shouldn't return a partially
> > modified drm_cmdline_mode.
> >
> > You said it yourself, the breakage is in the commit changing the
> > command line parsing logic, while you're fixing here some code that
> > was introduced later on.
>
> The problem stems from assumption that *any* named mode is valid. It
> looks to me that the ultimate solution would be to move the mode's name
> comparison into the [1], if that's possible.
>
> [1] drm_mode_parse_command_line_for_connector()
Well, one could argue that video=tegrafb is invalid and should be
rejected as well, but we haven't cleared that up.
> > Can you try the followintg patch?
> > http://code.bulix.org/8cwk4c-794565?raw
>
> This doesn't help because the problem with the rotation_reflection is
> that it's 0 if "rotation" not present in the cmdline and then ilog2(0)
> returns -1. So the patch "drm/modes: Don't apply cmdline's rotation if
> it wasn't specified" should be correct in any case.
So we would have the same issue with rotate=0 then?
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* Re: [PATCH v1] drm/modes: Skip invalid cmdline mode
From: Dmitry Osipenko @ 2019-07-12 8:30 UTC (permalink / raw)
To: Maxime Ripard
Cc: Thierry Reding, Jonathan Hunter, Maarten Lankhorst, Sean Paul,
Daniel Vetter, David Airlie, dri-devel, linux-tegra, linux-kernel
In-Reply-To: <20190712081027.arybdoxr6nzrmkxt@flea>
12.07.2019 11:10, Maxime Ripard пишет:
> On Thu, Jul 11, 2019 at 06:55:03PM +0300, Dmitry Osipenko wrote:
>> 11.07.2019 12:03, Maxime Ripard пишет:
>>> On Wed, Jul 10, 2019 at 06:05:18PM +0300, Dmitry Osipenko wrote:
>>>> 10.07.2019 17:05, Maxime Ripard пишет:
>>>>> On Wed, Jul 10, 2019 at 04:29:19PM +0300, Dmitry Osipenko wrote:
>>>>>> This works:
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/drm_client_modeset.c b/drivers/gpu/drm/drm_client_modeset.c
>>>>>> index 56d36779d213..e5a2f9c8f404 100644
>>>>>> --- a/drivers/gpu/drm/drm_client_modeset.c
>>>>>> +++ b/drivers/gpu/drm/drm_client_modeset.c
>>>>>> @@ -182,6 +182,8 @@ drm_connector_pick_cmdline_mode(struct drm_connector *connector)
>>>>>> mode = drm_mode_create_from_cmdline_mode(connector->dev, cmdline_mode);
>>>>>> if (mode)
>>>>>> list_add(&mode->head, &connector->modes);
>>>>>> + else
>>>>>> + cmdline_mode->specified = false;
>>>>>
>>>>> Hmmm, it's not clear to me why that wouldn't be the case.
>>>>>
>>>>> If we come back to the beginning of that function, we retrieve the
>>>>> cmdline_mode buffer from the connector pointer, that will probably
>>>>> have been parsed a first time using drm_mode_create_from_cmdline_mode
>>>>> in drm_helper_probe_add_cmdline_mode.
>>>>>
>>>>> Now, I'm guessing that the issue is that in
>>>>> drm_mode_parse_command_line_for_connector, if we have a named mode, we
>>>>> just copy the mode over and set mode->specified.
>>>>>
>>>>> And we then move over to do other checks, and that's probably what
>>>>> fails and returns, but our drm_cmdline_mode will have been modified.
>>>>>
>>>>> I'm not entirely sure how to deal with that though.
>>>>>
>>>>> I guess we could allocate a drm_cmdline_mode structure on the stack,
>>>>> fill that, and if successful copy over its content to the one in
>>>>> drm_connector. That would allow us to only change the content on
>>>>> success, which is what I would expect from such a function?
>>>>>
>>>>> How does that sound?
>>>>
>>>> I now see that there is DRM_MODE_TYPE_USERDEF flag that is assigned only
>>>> for the "cmdline" mode and drm_client_rotation() is the only place in
>>>> DRM code that cares about whether mode is from cmdline, hence looks like
>>>> it will be more correct to do the following:
>>>
>>> I'm still under the impression that we're dealing with workarounds of
>>> a more central issue, which is that we shouldn't return a partially
>>> modified drm_cmdline_mode.
>>>
>>> You said it yourself, the breakage is in the commit changing the
>>> command line parsing logic, while you're fixing here some code that
>>> was introduced later on.
>>
>> The problem stems from assumption that *any* named mode is valid. It
>> looks to me that the ultimate solution would be to move the mode's name
>> comparison into the [1], if that's possible.
>>
>> [1] drm_mode_parse_command_line_for_connector()
>
> Well, one could argue that video=tegrafb is invalid and should be
> rejected as well, but we haven't cleared that up.
The video=tegrafb is invalid mode, there is nothing to argue here. And
the problem is that invalid modes and not rejected for the very beginning.
>>> Can you try the followintg patch?
>>> http://code.bulix.org/8cwk4c-794565?raw
>>
>> This doesn't help because the problem with the rotation_reflection is
>> that it's 0 if "rotation" not present in the cmdline and then ilog2(0)
>> returns -1. So the patch "drm/modes: Don't apply cmdline's rotation if
>> it wasn't specified" should be correct in any case.
>
> So we would have the same issue with rotate=0 then?
No, we won't. Rotation mode is parsed into the DRM_MODE bitmask and
rotate=0 corresponds to DRM_MODE_ROTATE_0, which is BIT(0) as you may
notice. Hence rotation_reflection=0 is always an invalid value, meaning
that "rotate" option does not present in the cmdline. Please consult the
code, in particular see drm_mode_parse_cmdline_options() which was
written by yourself ;)
^ permalink raw reply
* Re: [PATCH v2 1/6] ARM: tegra: Remove cpuidle drivers
From: Jon Hunter @ 2019-07-12 9:39 UTC (permalink / raw)
To: Dmitry Osipenko, Thierry Reding, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-arm-kernel, linux-kernel
In-Reply-To: <a6e4b43e-369c-c501-6d2e-69d5b940ff9c@gmail.com>
On 11/07/2019 18:03, Dmitry Osipenko wrote:
> 11.07.2019 12:26, Jon Hunter пишет:
>>
>> On 11/07/2019 04:13, Dmitry Osipenko wrote:
>>> Remove the old drivers to replace them cleanly with a new one later on.
>>>
>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>> ---
>>> arch/arm/mach-tegra/Makefile | 13 --
>>> arch/arm/mach-tegra/cpuidle-tegra114.c | 89 -----------
>>> arch/arm/mach-tegra/cpuidle-tegra20.c | 212 -------------------------
>>> arch/arm/mach-tegra/cpuidle-tegra30.c | 132 ---------------
>>> arch/arm/mach-tegra/cpuidle.c | 50 ------
>>> arch/arm/mach-tegra/cpuidle.h | 21 ---
>>> arch/arm/mach-tegra/irq.c | 18 ---
>>> arch/arm/mach-tegra/irq.h | 11 --
>>> arch/arm/mach-tegra/pm.c | 7 -
>>> arch/arm/mach-tegra/pm.h | 1 -
>>> arch/arm/mach-tegra/reset-handler.S | 11 --
>>> arch/arm/mach-tegra/reset.h | 9 +-
>>> arch/arm/mach-tegra/sleep-tegra20.S | 190 +---------------------
>>> arch/arm/mach-tegra/sleep.h | 12 --
>>> arch/arm/mach-tegra/tegra.c | 3 -
>>> drivers/soc/tegra/Kconfig | 1 -
>>> include/soc/tegra/cpuidle.h | 4 -
>>> 17 files changed, 5 insertions(+), 779 deletions(-)
>>> delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra114.c
>>> delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra20.c
>>> delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c
>>> delete mode 100644 arch/arm/mach-tegra/cpuidle.c
>>> delete mode 100644 arch/arm/mach-tegra/cpuidle.h
>>> delete mode 100644 arch/arm/mach-tegra/irq.h
>>
>> By removing all the above, it is really hard to review the diff. Is
>> there any way you could first consolidate the cpuidle drivers into say
>> the existing arch/arm/mach-tegra/cpuidle-tegra20.c and then move to
>> drivers/cpuidle?
>
> I'm afraid that it will make reviewing even more difficult because
> everything that is removed here is not returned in the further patches.
> The new driver is based on the older ones, but I wrote it from scratch
> and it's not only looks different, but also works a bit different as you
> may see.
>
> Could you please clarify what exactly makes it hard to review? The diff
> looks pretty clean to me, while squashing everything into existing
> driver should be quite a mess.
Ideally a patch should standalone and can be reviewed by itself.
However, to review this, we need to review patches 1, 2 and 3 at the
same time. So IMO it is not that convenient from a reviewers
perspective. Furthermore, patches 1 and 3 are large and so easy to miss
something.
Is there really no way to have a patch to combined the existing drivers,
then a patch to convert them into the newer rewritten version you have
implemented, then move the driver?
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH 5.1 000/138] 5.1.18-stable review
From: Jon Hunter @ 2019-07-12 13:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel
Cc: torvalds, akpm, linux, shuah, patches, ben.hutchings, lkft-triage,
stable, linux-tegra, j-keerthy
In-Reply-To: <20190712121628.731888964@linuxfoundation.org>
Hi Greg,
On 12/07/2019 13:17, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.1.18 release.
> There are 138 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
> Anything received after that time might be too late.
>
> The whole patch series can be found in one patch at:
> https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.1.18-rc1.gz
> or in the git tree and branch at:
> git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.1.y
> and the diffstat can be found below.
>
> thanks,
>
> greg k-h
>
> -------------
> Pseudo-Shortlog of commits:
...
> Keerthy <j-keerthy@ti.com>
> ARM: dts: dra71x: Disable usb4_tm target module
...
> Keerthy <j-keerthy@ti.com>
> ARM: dts: dra76x: Disable usb4_tm target module
The above commits are generating the following compilation errors for
ARM ...
Error:
/dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm/boot/dts/dra71x.dtsi:15.1-9
Label or path usb4_tm not found
Error:
/dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm/boot/dts/dra76x.dtsi:89.1-9
Label or path usb4_tm not found
After reverting these two, I no longer see these errors.
Cheers,
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH 4.19 00/91] 4.19.59-stable review
From: Jon Hunter @ 2019-07-12 13:36 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel
Cc: torvalds, akpm, linux, shuah, patches, ben.hutchings, lkft-triage,
stable, linux-tegra
In-Reply-To: <20190712121621.422224300@linuxfoundation.org>
On 12/07/2019 13:18, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.19.59 release.
> There are 91 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
> Anything received after that time might be too late.
>
> The whole patch series can be found in one patch at:
> https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.19.59-rc1.gz
> or in the git tree and branch at:
> git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-4.19.y
> and the diffstat can be found below.
>
> thanks,
>
> greg k-h
All tests are passing for Tegra ...
Test results for stable-v4.19:
12 builds: 12 pass, 0 fail
22 boots: 22 pass, 0 fail
32 tests: 32 pass, 0 fail
Linux version: 4.19.59-rc1-gd66f8e7f112f
Boards tested: tegra124-jetson-tk1, tegra186-p2771-0000,
tegra194-p2972-0000, tegra20-ventana,
tegra210-p2371-2180, tegra30-cardhu-a04
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH 5.2 00/61] 5.2.1-stable review
From: Jon Hunter @ 2019-07-12 13:36 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel
Cc: torvalds, akpm, linux, shuah, patches, ben.hutchings, lkft-triage,
stable, linux-tegra
In-Reply-To: <20190712121620.632595223@linuxfoundation.org>
On 12/07/2019 13:19, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.2.1 release.
> There are 61 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
> Anything received after that time might be too late.
>
> The whole patch series can be found in one patch at:
> https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.2.1-rc1.gz
> or in the git tree and branch at:
> git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.2.y
> and the diffstat can be found below.
>
> thanks,
>
> greg k-h
All tests are passing for Tegra ...
Test results for stable-v5.2:
12 builds: 12 pass, 0 fail
22 boots: 22 pass, 0 fail
38 tests: 38 pass, 0 fail
Linux version: 5.2.1-rc1-g61731e8fe278
Boards tested: tegra124-jetson-tk1, tegra186-p2771-0000,
tegra194-p2972-0000, tegra20-ventana,
tegra210-p2371-2180, tegra30-cardhu-a04
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH 5.1 000/138] 5.1.18-stable review
From: Greg Kroah-Hartman @ 2019-07-12 15:30 UTC (permalink / raw)
To: Jon Hunter
Cc: linux-kernel, torvalds, akpm, linux, shuah, patches,
ben.hutchings, lkft-triage, stable, linux-tegra, j-keerthy
In-Reply-To: <4dae64c8-046e-3647-52d6-43362e986d21@nvidia.com>
On Fri, Jul 12, 2019 at 02:26:57PM +0100, Jon Hunter wrote:
> Hi Greg,
>
> On 12/07/2019 13:17, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 5.1.18 release.
> > There are 138 patches in this series, all will be posted as a response
> > to this one. If anyone has any issues with these being applied, please
> > let me know.
> >
> > Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
> > Anything received after that time might be too late.
> >
> > The whole patch series can be found in one patch at:
> > https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.1.18-rc1.gz
> > or in the git tree and branch at:
> > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.1.y
> > and the diffstat can be found below.
> >
> > thanks,
> >
> > greg k-h
> >
> > -------------
> > Pseudo-Shortlog of commits:
>
> ...
>
> > Keerthy <j-keerthy@ti.com>
> > ARM: dts: dra71x: Disable usb4_tm target module
>
> ...
>
> > Keerthy <j-keerthy@ti.com>
> > ARM: dts: dra76x: Disable usb4_tm target module
>
> The above commits are generating the following compilation errors for
> ARM ...
>
> Error:
> /dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm/boot/dts/dra71x.dtsi:15.1-9
> Label or path usb4_tm not found
>
> Error:
> /dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm/boot/dts/dra76x.dtsi:89.1-9
> Label or path usb4_tm not found
>
> After reverting these two, I no longer see these errors.
Both are now dropped, thanks. I'll push out a -rc2 with that changed.
greg k-h
^ permalink raw reply
* Re: [PATCH 5.2 00/61] 5.2.1-stable review
From: Greg Kroah-Hartman @ 2019-07-12 15:31 UTC (permalink / raw)
To: Jon Hunter
Cc: linux-kernel, torvalds, akpm, linux, shuah, patches,
ben.hutchings, lkft-triage, stable, linux-tegra
In-Reply-To: <a1ae16a7-e8f7-b6fc-df4e-46079bebf9b3@nvidia.com>
On Fri, Jul 12, 2019 at 02:36:29PM +0100, Jon Hunter wrote:
>
> On 12/07/2019 13:19, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 5.2.1 release.
> > There are 61 patches in this series, all will be posted as a response
> > to this one. If anyone has any issues with these being applied, please
> > let me know.
> >
> > Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
> > Anything received after that time might be too late.
> >
> > The whole patch series can be found in one patch at:
> > https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.2.1-rc1.gz
> > or in the git tree and branch at:
> > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.2.y
> > and the diffstat can be found below.
> >
> > thanks,
> >
> > greg k-h
>
> All tests are passing for Tegra ...
>
> Test results for stable-v5.2:
> 12 builds: 12 pass, 0 fail
> 22 boots: 22 pass, 0 fail
> 38 tests: 38 pass, 0 fail
>
> Linux version: 5.2.1-rc1-g61731e8fe278
> Boards tested: tegra124-jetson-tk1, tegra186-p2771-0000,
> tegra194-p2972-0000, tegra20-ventana,
> tegra210-p2371-2180, tegra30-cardhu-a04
That was fast, thanks for testing all of these.
greg k-h
^ permalink raw reply
* Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
From: Vidya Sagar @ 2019-07-12 15:32 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: bhelgaas, robh+dt, mark.rutland, thierry.reding, jonathanh,
kishon, catalin.marinas, will.deacon, jingoohan1,
gustavo.pimentel, digetx, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-arm-kernel, kthota, mmaddireddy,
sagar.tv
In-Reply-To: <20190711125433.GB26088@e121166-lin.cambridge.arm.com>
On 7/11/2019 6:24 PM, Lorenzo Pieralisi wrote:
> On Wed, Jul 10, 2019 at 11:52:12AM +0530, Vidya Sagar wrote:
>
> [...]
>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> new file mode 100644
>> index 000000000000..189779edd976
>> --- /dev/null
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -0,0 +1,1632 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * PCIe host controller driver for Tegra194 SoC
>> + *
>> + * Copyright (C) 2019 NVIDIA Corporation.
>> + *
>> + * Author: Vidya Sagar <vidyas@nvidia.com>
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/debugfs.h>
>> +#include <linux/delay.h>
>> +#include <linux/gpio.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/kernel.h>
>> +#include <linux/kfifo.h>
>> +#include <linux/kthread.h>
>
> What do you need these two headers for ?
These were added for a different reason. They are not required
and I'll remove them.
>
> [...]
>
>> +struct tegra_pcie_dw {
>> + struct device *dev;
>> + struct resource *appl_res;
>> + struct resource *dbi_res;
>> + struct resource *atu_dma_res;
>> + void __iomem *appl_base;
>> + struct clk *core_clk;
>> + struct reset_control *core_apb_rst;
>> + struct reset_control *core_rst;
>> + struct dw_pcie pci;
>> + enum dw_pcie_device_mode mode;
>> + struct tegra_bpmp *bpmp;
>> +
>> + bool supports_clkreq;
>> + bool enable_cdm_check;
>> + u8 init_link_width;
>> + bool link_state;
>> + u32 msi_ctrl_int;
>> + u32 num_lanes;
>> + u32 max_speed;
>> + u32 cid;
>> + bool update_fc_fixup;
>> + u32 cfg_link_cap_l1sub;
>> + u32 pcie_cap_base;
>> + u32 aspm_cmrt;
>> + u32 aspm_pwr_on_t;
>> + u32 aspm_l0s_enter_lat;o
>
> Nit: You should try to group variables according to their usage,
> it would make sense to group booleans together.
Ok.
>
>> + struct regulator *pex_ctl_supply;
>> +
>> + unsigned int phy_count;
>> + struct phy **phys;
>> +
>> + struct dentry *debugfs;
>> +};
>> +
>> +static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
>> +{
>> + return container_of(pci, struct tegra_pcie_dw, pci);
>> +}
>> +
>> +static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
>> + const u32 reg)
>> +{
>> + writel_relaxed(value, pcie->appl_base + reg);
>> +}
>> +
>> +static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
>> +{
>> + return readl_relaxed(pcie->appl_base + reg);
>> +}
>> +
>> +struct tegra_pcie_soc {
>> + enum dw_pcie_device_mode mode;
>> +};
>> +
>> +static void apply_bad_link_workaround(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 current_link_width;
>> + u16 val;
>> +
>> + /*
>> + * NOTE:- Since this scenario is uncommon and link as such is not
>> + * stable anyway, not waiting to confirm if link is really
>> + * transitioning to Gen-2 speed
>> + */
>> + val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
>> + if (val & PCI_EXP_LNKSTA_LBMS) {
>> + current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>
>> + PCI_EXP_LNKSTA_NLW_SHIFT;
>> + if (pcie->init_link_width > current_link_width) {
>> + dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
>> + val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL2);
>> + val &= ~PCI_EXP_LNKCTL2_TLS;
>> + val |= PCI_EXP_LNKCTL2_TLS_2_5GT;
>> + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL2, val);
>> +
>> + val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL);
>> + val |= PCI_EXP_LNKCTL_RL;
>> + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL, val);
>> + }
>> + }
>> +}
>> +
>> +static irqreturn_t tegra_pcie_rp_irq_handler(struct tegra_pcie_dw *pcie)
>> +{
>> + struct dw_pcie *pci = &pcie->pci;
>> + struct pcie_port *pp = &pci->pp;
>> + u32 val, tmp;
>> + u16 val_w;
>> +
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L0);
>> + if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
>> + if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
>> + appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
>> +
>> + /* SBR & Surprise Link Down WAR */
>> + val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
>> + val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
>> + appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
>> + udelay(1);
>> + val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
>> + val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
>> + appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
>> +
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
>> + val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE;
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
>> + }
>> + }
>> +
>> + if (val & APPL_INTR_STATUS_L0_INT_INT) {
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
>> + if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
>> + appl_writel(pcie,
>> + APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,
>> + APPL_INTR_STATUS_L1_8_0);
>> + apply_bad_link_workaround(pp);
>> + }
>> + if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
>> + appl_writel(pcie,
>> + APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,
>> + APPL_INTR_STATUS_L1_8_0);
>> +
>> + val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKSTA);
>> + dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w &
>> + PCI_EXP_LNKSTA_CLS);
>> + }
>> + }
>> +
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L0);
>> + if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
>> + tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
>> + if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
>> + dev_info(pci->dev, "CDM check complete\n");
>> + tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
>> + }
>> + if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
>> + dev_err(pci->dev, "CDM comparison mismatch\n");
>> + tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
>> + }
>> + if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
>> + dev_err(pci->dev, "CDM Logic error\n");
>> + tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
>> + }
>> + dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp);
>> + tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
>> + dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp);
>> + }
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
>> +{
>> + struct tegra_pcie_dw *pcie = arg;
>> +
>> + if (pcie->mode == DW_PCIE_RC_TYPE)
>> + return tegra_pcie_rp_irq_handler(pcie);
>
> What's the point of registering the handler if mode != DW_PCIE_RC_TYPE ?
Currently this driver supports only root port mode but we have a plan to add
support for endpoint mode (as Tegra194 as dual mode controllers) also in future
and when that happens, we'll have a corresponding tegra_pcie_ep_irq_handler()
to take care of ep specific interrupts.
>
>> + return IRQ_NONE;
>> +}
>> +
>> +static int tegra_pcie_dw_rd_own_conf(struct pcie_port *pp, int where, int size,
>> + u32 *val)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> +
>> + /*
>> + * This is an endpoint mode specific register happen to appear even
>> + * when controller is operating in root port mode and system hangs
>> + * when it is accessed with link being in ASPM-L1 state.
>> + * So skip accessing it altogether
>> + */
>> + if (where == PORT_LOGIC_MSIX_DOORBELL) {
>> + *val = 0x00000000;
>> + return PCIBIOS_SUCCESSFUL;
>> + }
>> +
>> + return dw_pcie_read(pci->dbi_base + where, size, val);
>> +}
>> +
>> +static int tegra_pcie_dw_wr_own_conf(struct pcie_port *pp, int where, int size,
>> + u32 val)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> +
>> + /*
>> + * This is an endpoint mode specific register happen to appear even
>> + * when controller is operating in root port mode and system hangs
>> + * when it is accessed with link being in ASPM-L1 state.
>> + * So skip accessing it altogether
>> + */
>> + if (where == PORT_LOGIC_MSIX_DOORBELL)
>> + return PCIBIOS_SUCCESSFUL;
>> +
>> + return dw_pcie_write(pci->dbi_base + where, size, val);
>> +}
>> +
>> +#if defined(CONFIG_PCIEASPM)
>> +static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
>> +{
>> + u32 val;
>> +
>> + val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
>> + val &= ~PCI_L1SS_CAP_ASPM_L1_1;
>> + dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
>> +}
>> +
>> +static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
>> +{
>> + u32 val;
>> +
>> + val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
>> + val &= ~PCI_L1SS_CAP_ASPM_L1_2;
>> + dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
>> +}
>> +
>> +static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
>> +{
>> + u32 val;
>> +
>> + val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);
>> + val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
>> + val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
>> + val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
>> + val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
>> + dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
>> + val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);
>> + return val;
>> +}
>> +
>> +static int aspm_state_cnt(struct seq_file *s, void *data)
>> +{
>> + struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
>> + dev_get_drvdata(s->private);
>> + u32 val;
>> +
>> + seq_printf(s, "Tx L0s entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
>> +
>> + seq_printf(s, "Rx L0s entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
>> +
>> + seq_printf(s, "Link L1 entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
>> +
>> + seq_printf(s, "Link L1.1 entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
>> +
>> + seq_printf(s, "Link L1.2 entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
>> +
>> + /* Clear all counters */
>> + dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],
>> + EVENT_COUNTER_ALL_CLEAR);
>> +
>> + /* Re-enable counting */
>> + val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
>> + val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
>> + dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static int init_debugfs(struct tegra_pcie_dw *pcie)
>> +{
>> +#if defined(CONFIG_PCIEASPM)
>> + struct dentry *d;
>> +
>> + d = debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt",
>> + pcie->debugfs, aspm_state_cnt);
>> + if (IS_ERR_OR_NULL(d))
>> + dev_err(pcie->dev,
>> + "Failed to create debugfs file \"aspm_state_cnt\"\n");
>> +#endif
>> + return 0;
>> +}
>> +
>> +static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val;
>> + u16 val_w;
>> +
>> + val = appl_readl(pcie, APPL_INTR_EN_L0_0);
>> + val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>> +
>> + val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
>> + val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
>> +
>> + if (pcie->enable_cdm_check) {
>> + val = appl_readl(pcie, APPL_INTR_EN_L0_0);
>> + val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>> +
>> + val = appl_readl(pcie, APPL_INTR_EN_L1_18);
>> + val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR;
>> + val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR;
>> + appl_writel(pcie, val, APPL_INTR_EN_L1_18);
>> + }
>> +
>> + val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKSTA);
>> + pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>
>> + PCI_EXP_LNKSTA_NLW_SHIFT;
>> +
>> + val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL);
>> + val_w |= PCI_EXP_LNKCTL_LBMIE;
>> + dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
>> + val_w);
>> +}
>> +
>> +static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val;
>> +
>> + /* Enable legacy interrupt generation */
>> + val = appl_readl(pcie, APPL_INTR_EN_L0_0);
>> + val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
>> + val |= APPL_INTR_EN_L0_0_INT_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>> +
>> + val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
>> + val |= APPL_INTR_EN_L1_8_INTX_EN;
>> + val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
>> + val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
>> + if (IS_ENABLED(CONFIG_PCIEAER))
>> + val |= APPL_INTR_EN_L1_8_AER_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
>> +}
>> +
>> +static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val;
>> +
>> + dw_pcie_msi_init(pp);
>> +
>> + /* Enable MSI interrupt generation */
>> + val = appl_readl(pcie, APPL_INTR_EN_L0_0);
>> + val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
>> + val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>> +}
>> +
>> +static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> +
>> + /* Clear interrupt statuses before enabling interrupts */
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
>> +
>> + tegra_pcie_enable_system_interrupts(pp);
>> + tegra_pcie_enable_legacy_interrupts(pp);
>> + if (IS_ENABLED(CONFIG_PCI_MSI))
>> + tegra_pcie_enable_msi_interrupts(pp);
>> +}
>> +
>> +static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
>> +{
>> + struct dw_pcie *pci = &pcie->pci;
>> + u32 val, offset, i;
>> +
>> + /* Program init preset */
>> + for (i = 0; i < pcie->num_lanes; i++) {
>> + dw_pcie_read(pci->dbi_base + CAP_SPCIE_CAP_OFF
>> + + (i * 2), 2, &val);
>> + val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;
>> + val |= GEN3_GEN4_EQ_PRESET_INIT;
>> + val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;
>> + val |= (GEN3_GEN4_EQ_PRESET_INIT <<
>> + CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);
>> + dw_pcie_write(pci->dbi_base + CAP_SPCIE_CAP_OFF
>> + + (i * 2), 2, val);
>> +
>> + offset = dw_pcie_find_ext_capability(pci,
>> + PCI_EXT_CAP_ID_PL_16GT) +
>> + PCI_PL_16GT_LE_CTRL;
>> + dw_pcie_read(pci->dbi_base + offset + i, 1, &val);
>> + val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;
>> + val |= GEN3_GEN4_EQ_PRESET_INIT;
>> + val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;
>> + val |= (GEN3_GEN4_EQ_PRESET_INIT <<
>> + PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);
>> + dw_pcie_write(pci->dbi_base + offset + i, 1, val);
>> + }
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
>> + val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
>> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
>> + val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
>> + val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
>> + val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
>> + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
>> + val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
>> + val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
>> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
>> + val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
>> + val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
>> + val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
>> + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
>> + val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
>> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>> +}
>> +
>> +static int tegra_pcie_dw_host_init(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val, tmp, offset, speed;
>> + unsigned int count;
>> + u16 val_w;
>> +
>> +core_init:
>
> I think it would be cleaner to include all registers programming
> within a function and we remove this label (and goto) below.
Some background:
As per spec r4.0 v1.0, downstream ports that support 16.0 GT/s must
support Scaled Flow Control (sec 3.4.2) and Tegra194's downstream ports
being 16.0 GT/s capable, enable scaled flow control by having
Data Link Feature (sec 7.7.4) enabled by default. There is one
endpoint (ASMedia USB3.0 controller) that doesn't link up with root port
because of this (i.e. DLF being enabled). The way we are detecting this situation
is to check for partial linkup i.e. one of application logic registers (i.e. from
"appl" region) says link is up but the same is not reflected in configuration space
of root port. Recommendation from our hardware team in this situation is to disable
DLF in root port and try link up with endpoint again. To achieve this, we put the
core through reset cycle, disable DLF and proceed with configuring all other registers
and check for link up.
Initially in Patch-1, I didn't have goto statement but a recursion with depth-1 (as the
above situation occurs only once). It was reviewed @ http://patchwork.ozlabs.org/patch/1065707/
and Thierry said it would be simpler to use a goto instead of calling the same
function again. So, I modified the code accordingly. Please do let me know if you strongly
feel we should call tegra_pcie_dw_host_init() instead of goto here. I'll change it.
>
>> + count = 200;
>
> It would be easier to read if we could inizialize this value closer
> to where it is actually used. Actually explaining why 200 as value
> was chosen would be appreciated.
Ok.
>
>> +#if defined(CONFIG_PCIEASPM)
>> + offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
>> + pcie->cfg_link_cap_l1sub = offset + PCI_L1SS_CAP;
>> +#endif
>
> Please try to factor this out within a single #ifdef guard.
Ok.
>
>> + val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
>> + val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
>> + dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
>> + val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE;
>> + val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE;
>> + dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
>> +
>> + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
>> +
>> + /* Configure FTS */
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
>> + val &= ~(N_FTS_MASK << N_FTS_SHIFT);
>> + val |= N_FTS_VAL << N_FTS_SHIFT;
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
>> + val &= ~FTS_MASK;
>> + val |= FTS_VAL;
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
>> +
>> + /* Enable as 0xFFFF0001 response for CRS */
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
>> + val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT);
>> + val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 <<
>> + AMBA_ERROR_RESPONSE_CRS_SHIFT);
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
>> +
>> + /* Configure Max Speed from DT */
>> + if (pcie->max_speed && pcie->max_speed != -EINVAL) {
>> + val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCAP);
>> + val &= ~PCI_EXP_LNKCAP_SLS;
>> + val |= pcie->max_speed;
>> + dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP,
>> + val);
>> + }
>> +
>> + /* Configure Max lane width from DT */
>> + val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
>> + val &= ~PCI_EXP_LNKCAP_MLW;
>> + val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
>> + dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
>> +
>> + config_gen3_gen4_eq_presets(pcie);
>> +
>> +#if defined(CONFIG_PCIEASPM)
>> + /* Enable ASPM counters */
>> + val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
>> + val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
>> + dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);
>> +
>> + /* Program T_cmrt and T_pwr_on values */
>> + val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
>> + val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
>> + val |= (pcie->aspm_cmrt << 8);
>> + val |= (pcie->aspm_pwr_on_t << 19);
>> + dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
>> +
>> + /* Program L0s and L1 entrance latencies */
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
>> + val &= ~L0S_ENTRANCE_LAT_MASK;
>> + val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT);
>> + val |= ENTER_ASPM;
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
>> +#endif
>
> See above.
Ok.
>
>> + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
>> + val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
>> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>> +
>> + if (pcie->update_fc_fixup) {
>> + val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
>> + val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
>> + dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
>> + }
>> +
>> + dw_pcie_setup_rc(pp);
>> +
>> + clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
>> +
>> + /* Assert RST */
>> + val = appl_readl(pcie, APPL_PINMUX);
>> + val &= ~APPL_PINMUX_PEX_RST;
>> + appl_writel(pcie, val, APPL_PINMUX);
>> +
>> + usleep_range(100, 200);
>> +
>> + /* Enable LTSSM */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val |= APPL_CTRL_LTSSM_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> +
>> + /* De-assert RST */
>> + val = appl_readl(pcie, APPL_PINMUX);
>> + val |= APPL_PINMUX_PEX_RST;
>> + appl_writel(pcie, val, APPL_PINMUX);
>> +
>> + msleep(100);
>> +
>> + val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
>> + while (!(val_w & PCI_EXP_LNKSTA_DLLLA)) {
>> + if (count) {
>> + dev_dbg(pci->dev, "Waiting for link up\n");
>> + usleep_range(1000, 2000);
>> + val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKSTA);
>> + count--;
>> + continue;
>> + }
>> +
>> + val = appl_readl(pcie, APPL_DEBUG);
>> + val &= APPL_DEBUG_LTSSM_STATE_MASK;
>> + val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
>> + tmp = appl_readl(pcie, APPL_LINK_STATUS);
>> + tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
>> + if (!(val == 0x11 && !tmp)) {
>> + dev_info(pci->dev, "Link is down\n");
>> + return 0;
>> + }
>> +
>> + dev_info(pci->dev, "Link is down in DLL");
>> + dev_info(pci->dev, "Trying again with DLFE disabled\n");
>> + /* Disable LTSSM */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val &= ~APPL_CTRL_LTSSM_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> +
>> + reset_control_assert(pcie->core_rst);
>> + reset_control_deassert(pcie->core_rst);
>> +
>> + offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
>> + val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
>> + val &= ~PCI_DLF_EXCHANGE_ENABLE;
>> + dw_pcie_writel_dbi(pci, offset, val);
>> +
>> + /* Retry now with DLF Exchange disabled */
>> + goto core_init;
>
> This goto upwards honestly is a bit horrible. Use some functions
> to make the code more readable.
Updated my comments above.
>
>> + }
>> + dev_dbg(pci->dev, "Link is up\n");
>> +
>> + speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
>> + PCI_EXP_LNKSTA_CLS;
>> + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
>> +
>> + tegra_pcie_enable_interrupts(pp);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_pcie_dw_link_up(struct dw_pcie *pci)
>> +{
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
>> +
>> + return !!(val & PCI_EXP_LNKSTA_DLLLA);
>
> It looks like this can be common code reusable by other DWC drivers ?
>
> Not mandatory, just a hint.
Well, each DesignWare core based implementation has a different way to find out
if the link is up and hence this hook is provided by DWC framework to let host controller
drivers implement their implementation specific link up check. In Tegra194, we are just
relying on spec defined configuration space register for link up.
>
>> +}
>> +
>> +static void tegra_pcie_set_msi_vec_num(struct pcie_port *pp)
>> +{
>> + pp->num_vectors = MAX_MSI_IRQS;
>> +}
>> +
>> +static const struct dw_pcie_ops tegra_dw_pcie_ops = {
>> + .link_up = tegra_pcie_dw_link_up,
>> +};
>> +
>> +static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
>> + .rd_own_conf = tegra_pcie_dw_rd_own_conf,
>> + .wr_own_conf = tegra_pcie_dw_wr_own_conf,
>> + .host_init = tegra_pcie_dw_host_init,
>> + .set_num_vectors = tegra_pcie_set_msi_vec_num,
>> +};
>> +
>> +static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
>> +{
>> + unsigned int phy_count = pcie->phy_count;
>> +
>> + while (phy_count--) {
>> + phy_power_off(pcie->phys[phy_count]);
>> + phy_exit(pcie->phys[phy_count]);
>> + }
>> +}
>> +
>> +static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
>> +{
>> + unsigned int i;
>> + int ret;
>> +
>> + for (i = 0; i < pcie->phy_count; i++) {
>> + ret = phy_init(pcie->phys[i]);
>> + if (ret < 0)
>> + goto phy_power_off;
>> +
>> + ret = phy_power_on(pcie->phys[i]);
>> + if (ret < 0)
>> + goto phy_exit;
>> + }
>> +
>> + return 0;
>> +
>> +phy_power_off:
>> + while (i--) {
>> + phy_power_off(pcie->phys[i]);
>> +phy_exit:
>> + phy_exit(pcie->phys[i]);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
>> +{
>> + struct device_node *np = pcie->dev->of_node;
>> + int ret;
>> +
>> + ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
>> + if (ret < 0) {
>> + dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
>> + &pcie->aspm_pwr_on_t);
>> + if (ret < 0)
>> + dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
>> + ret);
>> +
>> + ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
>> + &pcie->aspm_l0s_enter_lat);
>> + if (ret < 0)
>> + dev_info(pcie->dev,
>> + "Failed to read ASPM L0s Entrance latency: %d\n", ret);
>> +
>> + ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
>> + if (ret < 0) {
>> + dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + pcie->max_speed = of_pci_get_max_link_speed(np);
>> +
>> + ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + pcie->phy_count = of_property_count_strings(np, "phy-names");
>> + if (pcie->phy_count < 0) {
>> + dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
>> + pcie->phy_count);
>> + return pcie->phy_count;
>> + }
>> +
>> + if (of_property_read_bool(np, "nvidia,update-fc-fixup"))
>> + pcie->update_fc_fixup = true;
>> +
>> + pcie->supports_clkreq =
>> + of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
>> +
>> + pcie->enable_cdm_check =
>> + of_property_read_bool(np, "snps,enable-cdm-check");
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
>> + bool enable)
>> +{
>> + struct mrq_uphy_response resp;
>> + struct tegra_bpmp_message msg;
>> + struct mrq_uphy_request req;
>> + int err;
>> +
>> + if (pcie->cid == 5)
>> + return 0;
>
> What's wrong with cid == 5 ? Explain please.
Controller with ID=5 doesn't need any programming to enable it which is
done here through calling firmware API.
>
>> + memset(&req, 0, sizeof(req));
>> + memset(&resp, 0, sizeof(resp));
>> +
>> + req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
>> + req.controller_state.pcie_controller = pcie->cid;
>> + req.controller_state.enable = enable;
>> +
>> + memset(&msg, 0, sizeof(msg));
>> + msg.mrq = MRQ_UPHY;
>> + msg.tx.data = &req;
>> + msg.tx.size = sizeof(req);
>> + msg.rx.data = &resp;
>> + msg.rx.size = sizeof(resp);
>> +
>> + if (irqs_disabled())
>
> Can you explain to me what this check is meant to achieve please ?
Firmware interface provides different APIs to be called when there are no
interrupts enabled in the system (noirq context) and otherwise hence
checking that situation here and calling appropriate API.
>
>> + err = tegra_bpmp_transfer_atomic(pcie->bpmp, &msg);
>> + else
>> + err = tegra_bpmp_transfer(pcie->bpmp, &msg);
>> +
>> + return err;
>> +}
>> +
>> +static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
>> +{
>> + struct pcie_port *pp = &pcie->pci.pp;
>> + struct pci_dev *pdev;
>> + struct pci_bus *child;
>> +
>> + list_for_each_entry(child, &pp->root_bus->children, node) {
>> + /* Bring downstream devices to D0 if they are not already in */
>> + if (child->parent == pp->root_bus)
>> + break;
>> + }
>> + list_for_each_entry(pdev, &child->devices, bus_list) {
>> + if (PCI_SLOT(pdev->devfn) == 0) {
>> + if (pci_set_power_state(pdev, PCI_D0))
>> + dev_err(pcie->dev,
>> + "Failed to transition %s to D0 state\n",
>> + dev_name(&pdev->dev));
>> + }
>> + }
>> +}
>> +
>> +static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>> + bool en_hw_hot_rst)
>> +{
>> + int ret;
>> + u32 val;
>> +
>> + ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
>> + if (ret) {
>> + dev_err(pcie->dev,
>> + "Failed to enable controller %u: %d\n", pcie->cid, ret);
>> + return ret;
>> + }
>> +
>> + ret = regulator_enable(pcie->pex_ctl_supply);
>> + if (ret < 0) {
>> + dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
>> + goto fail_reg_en;
>> + }
>> +
>> + ret = clk_prepare_enable(pcie->core_clk);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
>> + goto fail_core_clk;
>> + }
>> +
>> + ret = reset_control_deassert(pcie->core_apb_rst);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
>> + ret);
>> + goto fail_core_apb_rst;
>> + }
>> +
>> + if (en_hw_hot_rst) {
>> + /* Enable HW_HOT_RST mode */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
>> + val |= APPL_CTRL_HW_HOT_RST_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> + }
>> +
>> + ret = tegra_pcie_enable_phy(pcie);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
>> + goto fail_phy;
>> + }
>> +
>> + /* Update CFG base address */
>> + appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
>> + APPL_CFG_BASE_ADDR);
>> +
>> + /* Configure this core for RP mode operation */
>> + appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
>> +
>> + appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
>> +
>> + val = appl_readl(pcie, APPL_CTRL);
>> + appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
>> +
>> + val = appl_readl(pcie, APPL_CFG_MISC);
>> + val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
>> + appl_writel(pcie, val, APPL_CFG_MISC);
>> +
>> + if (!pcie->supports_clkreq) {
>> + val = appl_readl(pcie, APPL_PINMUX);
>> + val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
>> + val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
>> + appl_writel(pcie, val, APPL_PINMUX);
>> + }
>> +
>> + /* Update iATU_DMA base address */
>> + appl_writel(pcie,
>> + pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
>> + APPL_CFG_IATU_DMA_BASE_ADDR);
>> +
>> + reset_control_deassert(pcie->core_rst);
>> +
>> + pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
>> + PCI_CAP_ID_EXP);
>> +
>> +#if defined(CONFIG_PCIEASPM)
>> + /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */
>> + if (!pcie->supports_clkreq) {
>> + disable_aspm_l11(pcie);
>> + disable_aspm_l12(pcie);
>> + }
>> +#endif
>> + return ret;
>> +
>> +fail_phy:
>> + reset_control_assert(pcie->core_apb_rst);
>> +fail_core_apb_rst:
>> + clk_disable_unprepare(pcie->core_clk);
>> +fail_core_clk:
>> + regulator_disable(pcie->pex_ctl_supply);
>> +fail_reg_en:
>> + tegra_pcie_bpmp_set_ctrl_state(pcie, false);
>> +
>> + return ret;
>> +}
>> +
>> +static int __deinit_controller(struct tegra_pcie_dw *pcie)
>> +{
>> + int ret;
>> +
>> + ret = reset_control_assert(pcie->core_rst);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n",
>> + ret);
>> + return ret;
>> + }
>> + tegra_pcie_disable_phy(pcie);
>> + ret = reset_control_assert(pcie->core_apb_rst);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
>> + return ret;
>> + }
>> + clk_disable_unprepare(pcie->core_clk);
>> + ret = regulator_disable(pcie->pex_ctl_supply);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
>> + return ret;
>> + }
>> + ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
>> + pcie->cid, ret);
>> + return ret;
>> + }
>> + return ret;
>> +}
>> +
>> +static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
>> +{
>> + struct dw_pcie *pci = &pcie->pci;
>> + struct pcie_port *pp = &pci->pp;
>> + int ret;
>> +
>> + ret = tegra_pcie_config_controller(pcie, false);
>> + if (ret < 0)
>> + return ret;
>> +
>> + pp->root_bus_nr = -1;
>> + pp->ops = &tegra_pcie_dw_host_ops;
>> +
>> + ret = dw_pcie_host_init(pp);
>> + if (ret < 0) {
>> + dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
>> + goto fail_host_init;
>> + }
>> +
>> + return 0;
>> +
>> +fail_host_init:
>> + return __deinit_controller(pcie);
>> +}
>> +
>> +static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
>> +{
>> + u32 val;
>> +
>> + if (!tegra_pcie_dw_link_up(&pcie->pci))
>> + return 0;
>> +
>> + val = appl_readl(pcie, APPL_RADM_STATUS);
>> + val |= APPL_PM_XMT_TURNOFF_STATE;
>> + appl_writel(pcie, val, APPL_RADM_STATUS);
>> +
>> + return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
>> + val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
>> + 1, PME_ACK_TIMEOUT);
>> +}
>> +
>> +static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>> +{
>> + u32 data;
>> + int err;
>> +
>> + if (!tegra_pcie_dw_link_up(&pcie->pci)) {
>> + dev_dbg(pcie->dev, "PCIe link is not up...!\n");
>> + return;
>> + }
>> +
>> + if (tegra_pcie_try_link_l2(pcie)) {
>> + dev_info(pcie->dev, "Link didn't transition to L2 state\n");
>> + /*
>> + * TX lane clock freq will reset to Gen1 only if link is in L2
>> + * or detect state.
>> + * So apply pex_rst to end point to force RP to go into detect
>> + * state
>> + */
>> + data = appl_readl(pcie, APPL_PINMUX);
>> + data &= ~APPL_PINMUX_PEX_RST;
>> + appl_writel(pcie, data, APPL_PINMUX);
>> +
>> + err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
>> + data,
>> + ((data &
>> + APPL_DEBUG_LTSSM_STATE_MASK) >>
>> + APPL_DEBUG_LTSSM_STATE_SHIFT) ==
>> + LTSSM_STATE_PRE_DETECT,
>> + 1, LTSSM_TIMEOUT);
>> + if (err) {
>> + dev_info(pcie->dev, "Link didn't go to detect state\n");
>> + } else {
>> + /* Disable LTSSM after link is in detect state */
>> + data = appl_readl(pcie, APPL_CTRL);
>> + data &= ~APPL_CTRL_LTSSM_EN;
>> + appl_writel(pcie, data, APPL_CTRL);
>> + }
>> + }
>> + /*
>> + * DBI registers may not be accessible after this as PLL-E would be
>> + * down depending on how CLKREQ is pulled by end point
>> + */
>> + data = appl_readl(pcie, APPL_PINMUX);
>> + data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE);
>> + /* Cut REFCLK to slot */
>> + data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
>> + data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
>> + appl_writel(pcie, data, APPL_PINMUX);
>> +}
>> +
>> +static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
>> +{
>> + /*
>> + * link doesn't go into L2 state with some of the endpoints with Tegra
>> + * if they are not in D0 state. So, need to make sure that immediate
>> + * downstream devices are in D0 state before sending PME_TurnOff to put
>> + * link into L2 state
>> + */
>> + tegra_pcie_downstream_dev_to_D0(pcie);
>> + dw_pcie_host_deinit(&pcie->pci.pp);
>> + tegra_pcie_dw_pme_turnoff(pcie);
>> + return __deinit_controller(pcie);
>> +}
>> +
>> +static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>> +{
>> + struct pcie_port *pp = &pcie->pci.pp;
>> + struct device *dev = pcie->dev;
>> + char *name;
>> + int ret;
>> +
>> + if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> + pp->msi_irq = of_irq_get_byname(dev->of_node, "msi");
>> + if (!pp->msi_irq) {
>> + dev_err(dev, "Failed to get MSI interrupt\n");
>> + return -ENODEV;
>> + }
>> + }
>> +
>> + pm_runtime_enable(dev);
>> + ret = pm_runtime_get_sync(dev);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
>> + ret);
>> + pm_runtime_disable(dev);
>> + return ret;
>> + }
>> +
>> + tegra_pcie_init_controller(pcie);
>> +
>> + pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
>> +
>> + if (!pcie->link_state) {
>> + ret = -ENOMEDIUM;
>> + goto fail_host_init;
>> + }
>> +
>> + name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
>> + if (!name) {
>> + ret = -ENOMEM;
>> + goto fail_host_init;
>> + }
>> +
>> + pcie->debugfs = debugfs_create_dir(name, NULL);
>> + if (!pcie->debugfs)
>> + dev_err(dev, "Failed to create debugfs\n");
>> + else
>> + init_debugfs(pcie);
>> +
>> + return ret;
>> +
>> +fail_host_init:
>> + tegra_pcie_deinit_controller(pcie);
>> + pm_runtime_put_sync(dev);
>> + pm_runtime_disable(dev);
>> + return ret;
>> +}
>> +
>> +static const struct tegra_pcie_soc tegra_pcie_rc_of_data = {
>> + .mode = DW_PCIE_RC_TYPE,
>> +};
>> +
>> +static const struct of_device_id tegra_pcie_dw_of_match[] = {
>> + {
>> + .compatible = "nvidia,tegra194-pcie",
>> + .data = &tegra_pcie_rc_of_data,
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
>> +
>> +static int tegra_pcie_dw_probe(struct platform_device *pdev)
>> +{
>> + const struct tegra_pcie_soc *data;
>> + struct device *dev = &pdev->dev;
>> + struct resource *atu_dma_res;
>> + struct tegra_pcie_dw *pcie;
>> + struct resource *dbi_res;
>> + struct pcie_port *pp;
>> + struct dw_pcie *pci;
>> + struct phy **phys;
>> + char *name;
>> + int ret;
>> + u32 i;
>> +
>> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
>> + if (!pcie)
>> + return -ENOMEM;
>> +
>> + pci = &pcie->pci;
>> + pci->dev = &pdev->dev;
>> + pci->ops = &tegra_dw_pcie_ops;
>> + pp = &pci->pp;
>> + pcie->dev = &pdev->dev;
>> +
>> + data = (struct tegra_pcie_soc *)of_device_get_match_data(dev);
>> + if (!data)
>> + return -EINVAL;
>> + pcie->mode = (enum dw_pcie_device_mode)data->mode;
>> +
>> + ret = tegra_pcie_dw_parse_dt(pcie);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to parse device tree: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
>> + if (IS_ERR(pcie->pex_ctl_supply)) {
>> + dev_err(dev, "Failed to get regulator: %ld\n",
>> + PTR_ERR(pcie->pex_ctl_supply));
>> + return PTR_ERR(pcie->pex_ctl_supply);
>> + }
>> +
>> + pcie->core_clk = devm_clk_get(dev, "core");
>> + if (IS_ERR(pcie->core_clk)) {
>> + dev_err(dev, "Failed to get core clock: %ld\n",
>> + PTR_ERR(pcie->core_clk));
>> + return PTR_ERR(pcie->core_clk);
>> + }
>> +
>> + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> + "appl");
>> + if (!pcie->appl_res) {
>> + dev_err(dev, "Failed to find \"appl\" region\n");
>> + return PTR_ERR(pcie->appl_res);
>> + }
>> + pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
>> + if (IS_ERR(pcie->appl_base))
>> + return PTR_ERR(pcie->appl_base);
>> +
>> + pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
>> + if (IS_ERR(pcie->core_apb_rst)) {
>> + dev_err(dev, "Failed to get APB reset: %ld\n",
>> + PTR_ERR(pcie->core_apb_rst));
>> + return PTR_ERR(pcie->core_apb_rst);
>> + }
>> +
>> + phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
>> + if (!phys)
>> + return PTR_ERR(phys);
>> +
>> + for (i = 0; i < pcie->phy_count; i++) {
>> + name = kasprintf(GFP_KERNEL, "p2u-%u", i);
>> + if (!name) {
>> + dev_err(dev, "Failed to create P2U string\n");
>> + return -ENOMEM;
>> + }
>> + phys[i] = devm_phy_get(dev, name);
>> + kfree(name);
>> + if (IS_ERR(phys[i])) {
>> + ret = PTR_ERR(phys[i]);
>> + dev_err(dev, "Failed to get PHY: %d\n", ret);
>> + return ret;
>> + }
>> + }
>> +
>> + pcie->phys = phys;
>> +
>> + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
>> + if (!dbi_res) {
>> + dev_err(dev, "Failed to find \"dbi\" region\n");
>> + return PTR_ERR(dbi_res);
>> + }
>> + pcie->dbi_res = dbi_res;
>> +
>> + pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
>> + if (IS_ERR(pci->dbi_base))
>> + return PTR_ERR(pci->dbi_base);
>> +
>> + /* Tegra HW locates DBI2 at a fixed offset from DBI */
>> + pci->dbi_base2 = pci->dbi_base + 0x1000;
>> +
>> + atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> + "atu_dma");
>> + if (!atu_dma_res) {
>> + dev_err(dev, "Failed to find \"atu_dma\" region\n");
>> + return PTR_ERR(atu_dma_res);
>> + }
>> + pcie->atu_dma_res = atu_dma_res;
>> + pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
>> + if (IS_ERR(pci->atu_base))
>> + return PTR_ERR(pci->atu_base);
>> +
>> + pcie->core_rst = devm_reset_control_get(dev, "core");
>> + if (IS_ERR(pcie->core_rst)) {
>> + dev_err(dev, "Failed to get core reset: %ld\n",
>> + PTR_ERR(pcie->core_rst));
>> + return PTR_ERR(pcie->core_rst);
>> + }
>> +
>> + pp->irq = platform_get_irq_byname(pdev, "intr");
>> + if (!pp->irq) {
>> + dev_err(dev, "Failed to get \"intr\" interrupt\n");
>> + return -ENODEV;
>> + }
>> +
>> + ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler,
>> + IRQF_SHARED, "tegra-pcie-intr", pcie);
>> + if (ret) {
>> + dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, ret);
>> + return ret;
>> + }
>> +
>> + pcie->bpmp = tegra_bpmp_get(dev);
>> + if (IS_ERR(pcie->bpmp))
>> + return PTR_ERR(pcie->bpmp);
>> +
>> + platform_set_drvdata(pdev, pcie);
>> +
>> + if (pcie->mode == DW_PCIE_RC_TYPE) {
>> + ret = tegra_pcie_config_rp(pcie);
>> + if (ret && ret != -ENOMEDIUM)
>> + goto fail;
>> + else
>> + return 0;
>
> So if the link is not up we still go ahead and make probe
> succeed. What for ?
We may need root port to be available to support hot-plugging of endpoint
devices, so, we don't fail the probe.
>
>> + }
>> +
>> +fail:
>> + tegra_bpmp_put(pcie->bpmp);
>> + return ret;
>> +}
>> +
>> +static int tegra_pcie_dw_remove(struct platform_device *pdev)
>> +{
>> + struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
>> +
>> + if (pcie->mode != DW_PCIE_RC_TYPE)
>> + return 0;
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + debugfs_remove_recursive(pcie->debugfs);
>> + tegra_pcie_deinit_controller(pcie);
>> + pm_runtime_put_sync(pcie->dev);
>> + pm_runtime_disable(pcie->dev);
>> + tegra_bpmp_put(pcie->bpmp);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_pcie_dw_suspend_late(struct device *dev)
>> +{
>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> + u32 val;
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + /* Enable HW_HOT_RST mode */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
>> + val |= APPL_CTRL_HW_HOT_RST_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>> +{
>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + /* Save MSI interrupt vector */
>> + pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
>> + PORT_LOGIC_MSI_CTRL_INT_0_EN);
>> + tegra_pcie_downstream_dev_to_D0(pcie);
>
> I think this requires some comments. AFAIU this is allowed by
> the PCI specs (PCI Express Base 4.0 r1.0 September 29-2017,
> 5.2 Link State Power Management). However, I would like to
> understand how this plays with the D state the devices are left
> in upon system suspend.
>
> "As the following example illustrates, it is also possible to remove
> power without first placing all Functions into D3Hot".
>
> I assume that's what happens on this platform to allow L2 entry but
> again, this needs clarification.
Yes. It is true that in the case of Tegra194, it brings devices back to D0
before putting link to L2 state.
>
> Lorenzo
>
>> + tegra_pcie_dw_pme_turnoff(pcie);
>> + return __deinit_controller(pcie);
>> +}
>> +
>> +static int tegra_pcie_dw_resume_noirq(struct device *dev)
>> +{
>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + ret = tegra_pcie_config_controller(pcie, true);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to init host: %d\n", ret);
>> + goto fail_host_init;
>> + }
>> +
>> + /* Restore MSI interrupt vector */
>> + dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
>> + pcie->msi_ctrl_int);
>> +
>> + return 0;
>> +fail_host_init:
>> + return __deinit_controller(pcie);
>> +}
>> +
>> +static int tegra_pcie_dw_resume_early(struct device *dev)
>> +{
>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> + u32 val;
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + /* Disable HW_HOT_RST mode */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
>> + val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
>> + val &= ~APPL_CTRL_HW_HOT_RST_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
>> +{
>> + struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
>> +
>> + if (pcie->mode != DW_PCIE_RC_TYPE)
>> + return;
>> +
>> + if (!pcie->link_state)
>> + return;
>> +
>> + debugfs_remove_recursive(pcie->debugfs);
>> + tegra_pcie_downstream_dev_to_D0(pcie);
>> +
>> + disable_irq(pcie->pci.pp.irq);
>> + if (IS_ENABLED(CONFIG_PCI_MSI))
>> + disable_irq(pcie->pci.pp.msi_irq);
>> +
>> + tegra_pcie_dw_pme_turnoff(pcie);
>> + __deinit_controller(pcie);
>> +}
>> +
>> +static const struct dev_pm_ops tegra_pcie_dw_pm_ops = {
>> + .suspend_late = tegra_pcie_dw_suspend_late,
>> + .suspend_noirq = tegra_pcie_dw_suspend_noirq,
>> + .resume_noirq = tegra_pcie_dw_resume_noirq,
>> + .resume_early = tegra_pcie_dw_resume_early,
>> +};
>> +
>> +static struct platform_driver tegra_pcie_dw_driver = {
>> + .probe = tegra_pcie_dw_probe,
>> + .remove = tegra_pcie_dw_remove,
>> + .shutdown = tegra_pcie_dw_shutdown,
>> + .driver = {
>> + .name = "tegra194-pcie",
>> + .pm = &tegra_pcie_dw_pm_ops,
>> + .of_match_table = tegra_pcie_dw_of_match,
>> + },
>> +};
>> +module_platform_driver(tegra_pcie_dw_driver);
>> +
>> +MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
>> +MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.17.1
>>
^ permalink raw reply
* Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
From: Lorenzo Pieralisi @ 2019-07-12 16:07 UTC (permalink / raw)
To: Vidya Sagar
Cc: bhelgaas, robh+dt, mark.rutland, thierry.reding, jonathanh,
kishon, catalin.marinas, will.deacon, jingoohan1,
gustavo.pimentel, digetx, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-arm-kernel, kthota, mmaddireddy,
sagar.tv
In-Reply-To: <986d0b1a-666a-7b05-a9f3-e761518bdc92@nvidia.com>
On Fri, Jul 12, 2019 at 09:02:49PM +0530, Vidya Sagar wrote:
[...]
> > > +static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
> > > +{
> > > + struct tegra_pcie_dw *pcie = arg;
> > > +
> > > + if (pcie->mode == DW_PCIE_RC_TYPE)
> > > + return tegra_pcie_rp_irq_handler(pcie);
> >
> > What's the point of registering the handler if mode != DW_PCIE_RC_TYPE ?
> Currently this driver supports only root port mode but we have a plan
> to add support for endpoint mode (as Tegra194 as dual mode
> controllers) also in future and when that happens, we'll have a
> corresponding tegra_pcie_ep_irq_handler() to take care of ep specific
> interrupts.
Sure, that's why you should add tegra_pcie_dw->mode when it is needed,
not in this patch.
[...]
> > > +static int tegra_pcie_dw_host_init(struct pcie_port *pp)
> > > +{
> > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
> > > + u32 val, tmp, offset, speed;
> > > + unsigned int count;
> > > + u16 val_w;
> > > +
> > > +core_init:
> >
> > I think it would be cleaner to include all registers programming
> > within a function and we remove this label (and goto) below.
> Some background: As per spec r4.0 v1.0, downstream ports that support
> 16.0 GT/s must support Scaled Flow Control (sec 3.4.2) and Tegra194's
> downstream ports being 16.0 GT/s capable, enable scaled flow control
> by having Data Link Feature (sec 7.7.4) enabled by default. There is
> one endpoint (ASMedia USB3.0 controller) that doesn't link up with
> root port because of this (i.e. DLF being enabled). The way we are
> detecting this situation is to check for partial linkup i.e. one of
> application logic registers (i.e. from "appl" region) says link is up
> but the same is not reflected in configuration space of root port.
> Recommendation from our hardware team in this situation is to disable
> DLF in root port and try link up with endpoint again. To achieve
> this, we put the core through reset cycle, disable DLF and proceed
> with configuring all other registers and check for link up.
>
> Initially in Patch-1, I didn't have goto statement but a recursion
> with depth-1 (as the above situation occurs only once). It was
> reviewed @ http://patchwork.ozlabs.org/patch/1065707/ and Thierry said
> it would be simpler to use a goto instead of calling the same function
> again. So, I modified the code accordingly. Please do let me know if
> you strongly feel we should call tegra_pcie_dw_host_init() instead of
> goto here. I'll change it.
I did not say we should call tegra_pcie_dw_host_init(), sorry for
not being clear. What I asked is factoring out registers programming
in a function and call it where core_init: label is and call it
again if DLF enablement causes link up to fail.
[...]
> > > +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
> > > + bool enable)
> > > +{
> > > + struct mrq_uphy_response resp;
> > > + struct tegra_bpmp_message msg;
> > > + struct mrq_uphy_request req;
> > > + int err;
> > > +
> > > + if (pcie->cid == 5)
> > > + return 0;
> >
> > What's wrong with cid == 5 ? Explain please.
> Controller with ID=5 doesn't need any programming to enable it which is
> done here through calling firmware API.
>
> >
> > > + memset(&req, 0, sizeof(req));
> > > + memset(&resp, 0, sizeof(resp));
> > > +
> > > + req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
> > > + req.controller_state.pcie_controller = pcie->cid;
> > > + req.controller_state.enable = enable;
> > > +
> > > + memset(&msg, 0, sizeof(msg));
> > > + msg.mrq = MRQ_UPHY;
> > > + msg.tx.data = &req;
> > > + msg.tx.size = sizeof(req);
> > > + msg.rx.data = &resp;
> > > + msg.rx.size = sizeof(resp);
> > > +
> > > + if (irqs_disabled())
> >
> > Can you explain to me what this check is meant to achieve please ?
> Firmware interface provides different APIs to be called when there are
> no interrupts enabled in the system (noirq context) and otherwise
> hence checking that situation here and calling appropriate API.
That's what I am questioning. Being called from {suspend/resume}_noirq()
callbacks (if that's the code path this check caters for) does not mean
irqs_disabled() == true.
Actually, if tegra_bpmp_transfer() requires IRQs to be enabled you may
even end up in a situation where that blocking call does not wake up
because the IRQ in question was disabled in the NOIRQ suspend/resume
phase.
[...]
> > > +static int tegra_pcie_dw_probe(struct platform_device *pdev)
> > > +{
> > > + const struct tegra_pcie_soc *data;
> > > + struct device *dev = &pdev->dev;
> > > + struct resource *atu_dma_res;
> > > + struct tegra_pcie_dw *pcie;
> > > + struct resource *dbi_res;
> > > + struct pcie_port *pp;
> > > + struct dw_pcie *pci;
> > > + struct phy **phys;
> > > + char *name;
> > > + int ret;
> > > + u32 i;
> > > +
> > > + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > > + if (!pcie)
> > > + return -ENOMEM;
> > > +
> > > + pci = &pcie->pci;
> > > + pci->dev = &pdev->dev;
> > > + pci->ops = &tegra_dw_pcie_ops;
> > > + pp = &pci->pp;
> > > + pcie->dev = &pdev->dev;
> > > +
> > > + data = (struct tegra_pcie_soc *)of_device_get_match_data(dev);
> > > + if (!data)
> > > + return -EINVAL;
> > > + pcie->mode = (enum dw_pcie_device_mode)data->mode;
> > > +
> > > + ret = tegra_pcie_dw_parse_dt(pcie);
> > > + if (ret < 0) {
> > > + dev_err(dev, "Failed to parse device tree: %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > + pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
> > > + if (IS_ERR(pcie->pex_ctl_supply)) {
> > > + dev_err(dev, "Failed to get regulator: %ld\n",
> > > + PTR_ERR(pcie->pex_ctl_supply));
> > > + return PTR_ERR(pcie->pex_ctl_supply);
> > > + }
> > > +
> > > + pcie->core_clk = devm_clk_get(dev, "core");
> > > + if (IS_ERR(pcie->core_clk)) {
> > > + dev_err(dev, "Failed to get core clock: %ld\n",
> > > + PTR_ERR(pcie->core_clk));
> > > + return PTR_ERR(pcie->core_clk);
> > > + }
> > > +
> > > + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > + "appl");
> > > + if (!pcie->appl_res) {
> > > + dev_err(dev, "Failed to find \"appl\" region\n");
> > > + return PTR_ERR(pcie->appl_res);
> > > + }
> > > + pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
> > > + if (IS_ERR(pcie->appl_base))
> > > + return PTR_ERR(pcie->appl_base);
> > > +
> > > + pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
> > > + if (IS_ERR(pcie->core_apb_rst)) {
> > > + dev_err(dev, "Failed to get APB reset: %ld\n",
> > > + PTR_ERR(pcie->core_apb_rst));
> > > + return PTR_ERR(pcie->core_apb_rst);
> > > + }
> > > +
> > > + phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
> > > + if (!phys)
> > > + return PTR_ERR(phys);
> > > +
> > > + for (i = 0; i < pcie->phy_count; i++) {
> > > + name = kasprintf(GFP_KERNEL, "p2u-%u", i);
> > > + if (!name) {
> > > + dev_err(dev, "Failed to create P2U string\n");
> > > + return -ENOMEM;
> > > + }
> > > + phys[i] = devm_phy_get(dev, name);
> > > + kfree(name);
> > > + if (IS_ERR(phys[i])) {
> > > + ret = PTR_ERR(phys[i]);
> > > + dev_err(dev, "Failed to get PHY: %d\n", ret);
> > > + return ret;
> > > + }
> > > + }
> > > +
> > > + pcie->phys = phys;
> > > +
> > > + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> > > + if (!dbi_res) {
> > > + dev_err(dev, "Failed to find \"dbi\" region\n");
> > > + return PTR_ERR(dbi_res);
> > > + }
> > > + pcie->dbi_res = dbi_res;
> > > +
> > > + pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
> > > + if (IS_ERR(pci->dbi_base))
> > > + return PTR_ERR(pci->dbi_base);
> > > +
> > > + /* Tegra HW locates DBI2 at a fixed offset from DBI */
> > > + pci->dbi_base2 = pci->dbi_base + 0x1000;
> > > +
> > > + atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > + "atu_dma");
> > > + if (!atu_dma_res) {
> > > + dev_err(dev, "Failed to find \"atu_dma\" region\n");
> > > + return PTR_ERR(atu_dma_res);
> > > + }
> > > + pcie->atu_dma_res = atu_dma_res;
> > > + pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
> > > + if (IS_ERR(pci->atu_base))
> > > + return PTR_ERR(pci->atu_base);
> > > +
> > > + pcie->core_rst = devm_reset_control_get(dev, "core");
> > > + if (IS_ERR(pcie->core_rst)) {
> > > + dev_err(dev, "Failed to get core reset: %ld\n",
> > > + PTR_ERR(pcie->core_rst));
> > > + return PTR_ERR(pcie->core_rst);
> > > + }
> > > +
> > > + pp->irq = platform_get_irq_byname(pdev, "intr");
> > > + if (!pp->irq) {
> > > + dev_err(dev, "Failed to get \"intr\" interrupt\n");
> > > + return -ENODEV;
> > > + }
> > > +
> > > + ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler,
> > > + IRQF_SHARED, "tegra-pcie-intr", pcie);
> > > + if (ret) {
> > > + dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, ret);
> > > + return ret;
> > > + }
> > > +
> > > + pcie->bpmp = tegra_bpmp_get(dev);
> > > + if (IS_ERR(pcie->bpmp))
> > > + return PTR_ERR(pcie->bpmp);
> > > +
> > > + platform_set_drvdata(pdev, pcie);
> > > +
> > > + if (pcie->mode == DW_PCIE_RC_TYPE) {
> > > + ret = tegra_pcie_config_rp(pcie);
> > > + if (ret && ret != -ENOMEDIUM)
> > > + goto fail;
> > > + else
> > > + return 0;
> >
> > So if the link is not up we still go ahead and make probe
> > succeed. What for ?
> We may need root port to be available to support hot-plugging of
> endpoint devices, so, we don't fail the probe.
We need it or we don't. If you do support hotplugging of endpoint
devices point me at the code, otherwise link up failure means
failure to probe.
> > > + }
> > > +
> > > +fail:
> > > + tegra_bpmp_put(pcie->bpmp);
> > > + return ret;
> > > +}
> > > +
> > > +static int tegra_pcie_dw_remove(struct platform_device *pdev)
> > > +{
> > > + struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
> > > +
> > > + if (pcie->mode != DW_PCIE_RC_TYPE)
> > > + return 0;
> > > +
> > > + if (!pcie->link_state)
> > > + return 0;
> > > +
> > > + debugfs_remove_recursive(pcie->debugfs);
> > > + tegra_pcie_deinit_controller(pcie);
> > > + pm_runtime_put_sync(pcie->dev);
> > > + pm_runtime_disable(pcie->dev);
> > > + tegra_bpmp_put(pcie->bpmp);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int tegra_pcie_dw_suspend_late(struct device *dev)
> > > +{
> > > + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
> > > + u32 val;
> > > +
> > > + if (!pcie->link_state)
> > > + return 0;
> > > +
> > > + /* Enable HW_HOT_RST mode */
> > > + val = appl_readl(pcie, APPL_CTRL);
> > > + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
> > > + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
> > > + val |= APPL_CTRL_HW_HOT_RST_EN;
> > > + appl_writel(pcie, val, APPL_CTRL);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int tegra_pcie_dw_suspend_noirq(struct device *dev)
> > > +{
> > > + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
> > > +
> > > + if (!pcie->link_state)
> > > + return 0;
> > > +
> > > + /* Save MSI interrupt vector */
> > > + pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
> > > + PORT_LOGIC_MSI_CTRL_INT_0_EN);
> > > + tegra_pcie_downstream_dev_to_D0(pcie);
> >
> > I think this requires some comments. AFAIU this is allowed by
> > the PCI specs (PCI Express Base 4.0 r1.0 September 29-2017,
> > 5.2 Link State Power Management). However, I would like to
> > understand how this plays with the D state the devices are left
> > in upon system suspend.
> >
> > "As the following example illustrates, it is also possible to remove
> > power without first placing all Functions into D3Hot".
> >
> > I assume that's what happens on this platform to allow L2 entry but
> > again, this needs clarification.
> Yes. It is true that in the case of Tegra194, it brings devices back
> to D0 before putting link to L2 state.
Comment it, extensively, so that anyone reading the code understands
why it is done so and what happens to devices then.
Lorenzo
^ permalink raw reply
* Re: [PATCH 5.2 00/61] 5.2.1-stable review
From: Jon Hunter @ 2019-07-12 16:10 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: linux-kernel, torvalds, akpm, linux, shuah, patches,
ben.hutchings, lkft-triage, stable, linux-tegra
In-Reply-To: <20190712153108.GD13940@kroah.com>
On 12/07/2019 16:31, Greg Kroah-Hartman wrote:
> On Fri, Jul 12, 2019 at 02:36:29PM +0100, Jon Hunter wrote:
>>
>> On 12/07/2019 13:19, Greg Kroah-Hartman wrote:
>>> This is the start of the stable review cycle for the 5.2.1 release.
>>> There are 61 patches in this series, all will be posted as a response
>>> to this one. If anyone has any issues with these being applied, please
>>> let me know.
>>>
>>> Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
>>> Anything received after that time might be too late.
>>>
>>> The whole patch series can be found in one patch at:
>>> https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.2.1-rc1.gz
>>> or in the git tree and branch at:
>>> git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.2.y
>>> and the diffstat can be found below.
>>>
>>> thanks,
>>>
>>> greg k-h
>>
>> All tests are passing for Tegra ...
>>
>> Test results for stable-v5.2:
>> 12 builds: 12 pass, 0 fail
>> 22 boots: 22 pass, 0 fail
>> 38 tests: 38 pass, 0 fail
>>
>> Linux version: 5.2.1-rc1-g61731e8fe278
>> Boards tested: tegra124-jetson-tk1, tegra186-p2771-0000,
>> tegra194-p2972-0000, tegra20-ventana,
>> tegra210-p2371-2180, tegra30-cardhu-a04
>
> That was fast, thanks for testing all of these.
Friday afternoon for me and so I am even more motivated :-)
BTW, has anyone ever requested pushing out a deadline failing on the
weekend to the following Monday? There is a chance I could miss this if
I happen to leave early on a Friday.
Cheers!
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH v2 1/6] ARM: tegra: Remove cpuidle drivers
From: Dmitry Osipenko @ 2019-07-12 16:23 UTC (permalink / raw)
To: Jon Hunter, Thierry Reding, Peter De Schrijver, Rafael J. Wysocki,
Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-arm-kernel, linux-kernel
In-Reply-To: <73781434-d25a-b17b-aacb-95ace5ac5f95@nvidia.com>
12.07.2019 12:39, Jon Hunter пишет:
>
> On 11/07/2019 18:03, Dmitry Osipenko wrote:
>> 11.07.2019 12:26, Jon Hunter пишет:
>>>
>>> On 11/07/2019 04:13, Dmitry Osipenko wrote:
>>>> Remove the old drivers to replace them cleanly with a new one later on.
>>>>
>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>> ---
>>>> arch/arm/mach-tegra/Makefile | 13 --
>>>> arch/arm/mach-tegra/cpuidle-tegra114.c | 89 -----------
>>>> arch/arm/mach-tegra/cpuidle-tegra20.c | 212 -------------------------
>>>> arch/arm/mach-tegra/cpuidle-tegra30.c | 132 ---------------
>>>> arch/arm/mach-tegra/cpuidle.c | 50 ------
>>>> arch/arm/mach-tegra/cpuidle.h | 21 ---
>>>> arch/arm/mach-tegra/irq.c | 18 ---
>>>> arch/arm/mach-tegra/irq.h | 11 --
>>>> arch/arm/mach-tegra/pm.c | 7 -
>>>> arch/arm/mach-tegra/pm.h | 1 -
>>>> arch/arm/mach-tegra/reset-handler.S | 11 --
>>>> arch/arm/mach-tegra/reset.h | 9 +-
>>>> arch/arm/mach-tegra/sleep-tegra20.S | 190 +---------------------
>>>> arch/arm/mach-tegra/sleep.h | 12 --
>>>> arch/arm/mach-tegra/tegra.c | 3 -
>>>> drivers/soc/tegra/Kconfig | 1 -
>>>> include/soc/tegra/cpuidle.h | 4 -
>>>> 17 files changed, 5 insertions(+), 779 deletions(-)
>>>> delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra114.c
>>>> delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra20.c
>>>> delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c
>>>> delete mode 100644 arch/arm/mach-tegra/cpuidle.c
>>>> delete mode 100644 arch/arm/mach-tegra/cpuidle.h
>>>> delete mode 100644 arch/arm/mach-tegra/irq.h
>>>
>>> By removing all the above, it is really hard to review the diff. Is
>>> there any way you could first consolidate the cpuidle drivers into say
>>> the existing arch/arm/mach-tegra/cpuidle-tegra20.c and then move to
>>> drivers/cpuidle?
>>
>> I'm afraid that it will make reviewing even more difficult because
>> everything that is removed here is not returned in the further patches.
>> The new driver is based on the older ones, but I wrote it from scratch
>> and it's not only looks different, but also works a bit different as you
>> may see.
>>
>> Could you please clarify what exactly makes it hard to review? The diff
>> looks pretty clean to me, while squashing everything into existing
>> driver should be quite a mess.
>
> Ideally a patch should standalone and can be reviewed by itself.
> However, to review this, we need to review patches 1, 2 and 3 at the
> same time. So IMO it is not that convenient from a reviewers
> perspective. Furthermore, patches 1 and 3 are large and so easy to miss
> something.
>
> Is there really no way to have a patch to combined the existing drivers,
> then a patch to convert them into the newer rewritten version you have
> implemented, then move the driver?
Probably I spent a bit too much time with that code, so now yours
suggestion looks to me like an unnecessary step. But I will try and see
how it goes, at least it should be possible to break down the patch 1 a
bit more, hopefully it will help to better understand what's going on in
the further patches if you're not familiar or don't remember how it all
works.
^ permalink raw reply
* Re: [PATCH v2 3/6] cpuidle: Add unified driver for NVIDIA Tegra SoCs
From: Dmitry Osipenko @ 2019-07-12 16:41 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-arm-kernel, linux-kernel
In-Reply-To: <c54c43fd-9b11-4aa8-3acf-d2260d0fca4a@gmail.com>
11.07.2019 21:35, Dmitry Osipenko пишет:
> 11.07.2019 6:13, Dmitry Osipenko пишет:
>> The new driver is based on the old CPU Idle drivers that are removed now
>> from arm/arch/mach-tegra/ directory. Those removed drivers were reworked
>> and squashed into a single unified driver that covers multiple hardware
>> generations, starting from Tegra20 and ending with Tegra124.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>> arch/arm/mach-tegra/tegra.c | 4 +
>> drivers/cpuidle/Kconfig.arm | 8 +
>> drivers/cpuidle/Makefile | 1 +
>> drivers/cpuidle/cpuidle-tegra.c | 304 ++++++++++++++++++++++++++++++++
>> include/soc/tegra/cpuidle.h | 4 +
>> 5 files changed, 321 insertions(+)
>> create mode 100644 drivers/cpuidle/cpuidle-tegra.c
>>
>> diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
>> index d9237769a37c..f1ce2857a251 100644
>> --- a/arch/arm/mach-tegra/tegra.c
>> +++ b/arch/arm/mach-tegra/tegra.c
>> @@ -36,6 +36,7 @@
>> #include <asm/mach/arch.h>
>> #include <asm/mach/time.h>
>> #include <asm/mach-types.h>
>> +#include <asm/psci.h>
>> #include <asm/setup.h>
>>
>> #include "board.h"
>> @@ -92,6 +93,9 @@ static void __init tegra_dt_init_late(void)
>> if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
>> of_machine_is_compatible("nvidia,tegra20"))
>> platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
>> +
>> + if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
>> + platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
>> }
>>
>> static const char * const tegra_dt_board_compat[] = {
>> diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
>> index 48cb3d4bb7d1..d90861361f1d 100644
>> --- a/drivers/cpuidle/Kconfig.arm
>> +++ b/drivers/cpuidle/Kconfig.arm
>> @@ -76,3 +76,11 @@ config ARM_MVEBU_V7_CPUIDLE
>> depends on ARCH_MVEBU && !ARM64
>> help
>> Select this to enable cpuidle on Armada 370, 38x and XP processors.
>> +
>> +config ARM_TEGRA_CPUIDLE
>> + bool "CPU Idle Driver for NVIDIA Tegra SoCs"
>> + depends on ARCH_TEGRA && !ARM64
>> + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
>> + select ARM_CPU_SUSPEND
>> + help
>> + Select this to enable cpuidle for NVIDIA Tegra20/30/114/124 SoCs.
>> diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
>> index 9d7176cee3d3..470d17fa8746 100644
>> --- a/drivers/cpuidle/Makefile
>> +++ b/drivers/cpuidle/Makefile
>> @@ -20,6 +20,7 @@ obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o
>> obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o
>> obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o
>> obj-$(CONFIG_ARM_CPUIDLE) += cpuidle-arm.o
>> +obj-$(CONFIG_ARM_TEGRA_CPUIDLE) += cpuidle-tegra.o
>>
>> ###############################################################################
>> # MIPS drivers
>> diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c
>> new file mode 100644
>> index 000000000000..54974cd2255f
>> --- /dev/null
>> +++ b/drivers/cpuidle/cpuidle-tegra.c
>> @@ -0,0 +1,304 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * CPU idle driver for Tegra CPUs
>> + *
>> + * Copyright (c) 2010-2013, NVIDIA Corporation.
>> + * Copyright (c) 2011 Google, Inc.
>> + * Author: Colin Cross <ccross@android.com>
>> + * Gary King <gking@nvidia.com>
>> + *
>> + * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
>> + *
>> + * Tegra20/124 driver unification by Dmitry Osipenko <digetx@gmail.com>
>> + */
>> +
>> +#include <linux/cpuidle.h>
>> +#include <linux/cpumask.h>
>> +#include <linux/cpu_pm.h>
>> +#include <linux/errno.h>
>> +#include <linux/ktime.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/types.h>
>> +
>> +#include <linux/clk/tegra.h>
>> +#include <linux/firmware/trusted_foundations.h>
>> +
>> +#include <soc/tegra/cpuidle.h>
>> +#include <soc/tegra/flowctrl.h>
>> +#include <soc/tegra/fuse.h>
>> +#include <soc/tegra/pm.h>
>> +
>> +#include <asm/cpuidle.h>
>> +#include <asm/firmware.h>
>> +#include <asm/smp_plat.h>
>> +#include <asm/suspend.h>
>> +
>> +#define TEGRA_C1 0
>> +#define TEGRA_C7 1
>> +#define TEGRA_CC6 2
>> +
>> +static atomic_t tegra_idle_barrier;
>> +
>> +static inline bool tegra_cpuidle_using_firmware(void)
>> +{
>> + return firmware_ops->prepare_idle && firmware_ops->do_idle;
>> +}
>> +
>> +static int tegra_shutdown_secondary_cpu(unsigned long cpu)
>> +{
>> + tegra_cpu_die(cpu);
>> +
>> + return -EINVAL;
>> +}
>> +
>> +static int tegra_await_secondary_cpus_shutdown(void)
>> +{
>> + ktime_t timeout = ktime_add_ms(ktime_get(), 1);
>> +
>> + /*
>> + * The boot CPU shall await for the secondaries shutdown in order
>> + * to power-off CPU's cluster safely.
>> + */
>> + do {
>> + if (tegra_cpu_rail_off_ready())
>> + return 0;
>> +
>> + } while (ktime_compare(ktime_get(), timeout) < 0);
>> +
>> + return -ETIMEDOUT;
>> +}
>> +
>> +static void tegra_wake_up_secondary_cpus(void)
>> +{
>> + unsigned int cpu, lcpu;
>> +
>> + for_each_cpu(lcpu, cpu_online_mask) {
>> + cpu = cpu_logical_map(lcpu);
>> +
>> + if (cpu > 0) {
>> + tegra_enable_cpu_clock(cpu);
>> + tegra_cpu_out_of_reset(cpu);
>> + flowctrl_write_cpu_halt(cpu, 0);
>> + }
>> + }
>> +}
>> +
>> +static int tegra_cpuidle_cc6_enter(void)
>> +{
>> + int err;
>> +
>> + err = tegra_await_secondary_cpus_shutdown();
>> + if (err)
>> + return err;
>> +
>> + err = tegra_idle_lp2_last();
>> +
>> + tegra_wake_up_secondary_cpus();
>> +
>> + return err;
>> +}
>> +
>> +static int tegra_cpuidle_c7_enter(void)
>> +{
>> + int err;
>> +
>> + if (tegra_cpuidle_using_firmware()) {
>> + err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
>> + if (err)
>> + return err;
>> +
>> + return call_firmware_op(do_idle, 0);
>> + }
>> +
>> + return cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
>> +}
>> +
>> +static int tegra_cpuidle_enter(struct cpuidle_device *dev,
>> + int index, unsigned int cpu)
>> +{
>> + int err;
>> +
>> + local_fiq_disable();
>> + tegra_set_cpu_in_lp2();
>> + cpu_pm_enter();
>> +
>> + switch (index) {
>> + case TEGRA_C7:
>> + err = tegra_cpuidle_c7_enter();
>> + break;
>> + case TEGRA_CC6:
>> + cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier);
>
> I realized that this is not very correct. We still need to do a proper
> barrier with SGI checking in order to bail out if other CPU sent IPI
> during of the awaiting for a coupled barrier to avoid the overhead of
> unnecessary power-gating. Will correct that in the next revision.
UPDATE: Actually, turned out it's even a necessity to handle the SGI
because GIC's driver doesn't save and replay SGI across CPU cluster PM.
^ permalink raw reply
* Re: [PATCH 5.2 00/61] 5.2.1-stable review
From: Greg Kroah-Hartman @ 2019-07-12 16:51 UTC (permalink / raw)
To: Jon Hunter
Cc: linux-kernel, torvalds, akpm, linux, shuah, patches,
ben.hutchings, lkft-triage, stable, linux-tegra
In-Reply-To: <a0d871e7-a68c-5c77-1389-5b9a86f93ac9@nvidia.com>
On Fri, Jul 12, 2019 at 05:10:30PM +0100, Jon Hunter wrote:
>
> On 12/07/2019 16:31, Greg Kroah-Hartman wrote:
> > On Fri, Jul 12, 2019 at 02:36:29PM +0100, Jon Hunter wrote:
> >>
> >> On 12/07/2019 13:19, Greg Kroah-Hartman wrote:
> >>> This is the start of the stable review cycle for the 5.2.1 release.
> >>> There are 61 patches in this series, all will be posted as a response
> >>> to this one. If anyone has any issues with these being applied, please
> >>> let me know.
> >>>
> >>> Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
> >>> Anything received after that time might be too late.
> >>>
> >>> The whole patch series can be found in one patch at:
> >>> https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.2.1-rc1.gz
> >>> or in the git tree and branch at:
> >>> git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.2.y
> >>> and the diffstat can be found below.
> >>>
> >>> thanks,
> >>>
> >>> greg k-h
> >>
> >> All tests are passing for Tegra ...
> >>
> >> Test results for stable-v5.2:
> >> 12 builds: 12 pass, 0 fail
> >> 22 boots: 22 pass, 0 fail
> >> 38 tests: 38 pass, 0 fail
> >>
> >> Linux version: 5.2.1-rc1-g61731e8fe278
> >> Boards tested: tegra124-jetson-tk1, tegra186-p2771-0000,
> >> tegra194-p2972-0000, tegra20-ventana,
> >> tegra210-p2371-2180, tegra30-cardhu-a04
> >
> > That was fast, thanks for testing all of these.
>
> Friday afternoon for me and so I am even more motivated :-)
>
> BTW, has anyone ever requested pushing out a deadline failing on the
> weekend to the following Monday? There is a chance I could miss this if
> I happen to leave early on a Friday.
Sure, if things break and I notice them, I've delayed releases until
they get fixed in the past.
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH v1] drm/modes: Skip invalid cmdline mode
From: Maxime Ripard @ 2019-07-12 19:53 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Maarten Lankhorst, Sean Paul,
Daniel Vetter, David Airlie, dri-devel, linux-tegra, linux-kernel
In-Reply-To: <686a20ce-e09a-037c-a5db-bd1309790c3e@gmail.com>
On Fri, Jul 12, 2019 at 11:30:01AM +0300, Dmitry Osipenko wrote:
> 12.07.2019 11:10, Maxime Ripard пишет:
> > On Thu, Jul 11, 2019 at 06:55:03PM +0300, Dmitry Osipenko wrote:
> >> 11.07.2019 12:03, Maxime Ripard пишет:
> >>> On Wed, Jul 10, 2019 at 06:05:18PM +0300, Dmitry Osipenko wrote:
> >>>> 10.07.2019 17:05, Maxime Ripard пишет:
> >>>>> On Wed, Jul 10, 2019 at 04:29:19PM +0300, Dmitry Osipenko wrote:
> >>>>>> This works:
> >>>>>>
> >>>>>> diff --git a/drivers/gpu/drm/drm_client_modeset.c b/drivers/gpu/drm/drm_client_modeset.c
> >>>>>> index 56d36779d213..e5a2f9c8f404 100644
> >>>>>> --- a/drivers/gpu/drm/drm_client_modeset.c
> >>>>>> +++ b/drivers/gpu/drm/drm_client_modeset.c
> >>>>>> @@ -182,6 +182,8 @@ drm_connector_pick_cmdline_mode(struct drm_connector *connector)
> >>>>>> mode = drm_mode_create_from_cmdline_mode(connector->dev, cmdline_mode);
> >>>>>> if (mode)
> >>>>>> list_add(&mode->head, &connector->modes);
> >>>>>> + else
> >>>>>> + cmdline_mode->specified = false;
> >>>>>
> >>>>> Hmmm, it's not clear to me why that wouldn't be the case.
> >>>>>
> >>>>> If we come back to the beginning of that function, we retrieve the
> >>>>> cmdline_mode buffer from the connector pointer, that will probably
> >>>>> have been parsed a first time using drm_mode_create_from_cmdline_mode
> >>>>> in drm_helper_probe_add_cmdline_mode.
> >>>>>
> >>>>> Now, I'm guessing that the issue is that in
> >>>>> drm_mode_parse_command_line_for_connector, if we have a named mode, we
> >>>>> just copy the mode over and set mode->specified.
> >>>>>
> >>>>> And we then move over to do other checks, and that's probably what
> >>>>> fails and returns, but our drm_cmdline_mode will have been modified.
> >>>>>
> >>>>> I'm not entirely sure how to deal with that though.
> >>>>>
> >>>>> I guess we could allocate a drm_cmdline_mode structure on the stack,
> >>>>> fill that, and if successful copy over its content to the one in
> >>>>> drm_connector. That would allow us to only change the content on
> >>>>> success, which is what I would expect from such a function?
> >>>>>
> >>>>> How does that sound?
> >>>>
> >>>> I now see that there is DRM_MODE_TYPE_USERDEF flag that is assigned only
> >>>> for the "cmdline" mode and drm_client_rotation() is the only place in
> >>>> DRM code that cares about whether mode is from cmdline, hence looks like
> >>>> it will be more correct to do the following:
> >>>
> >>> I'm still under the impression that we're dealing with workarounds of
> >>> a more central issue, which is that we shouldn't return a partially
> >>> modified drm_cmdline_mode.
> >>>
> >>> You said it yourself, the breakage is in the commit changing the
> >>> command line parsing logic, while you're fixing here some code that
> >>> was introduced later on.
> >>
> >> The problem stems from assumption that *any* named mode is valid. It
> >> looks to me that the ultimate solution would be to move the mode's name
> >> comparison into the [1], if that's possible.
> >>
> >> [1] drm_mode_parse_command_line_for_connector()
> >
> > Well, one could argue that video=tegrafb is invalid and should be
> > rejected as well, but we haven't cleared that up.
>
> The video=tegrafb is invalid mode, there is nothing to argue here. And
> the problem is that invalid modes and not rejected for the very beginning.
Yeah, I guess fb_get_options should also return an error in such a
case, but I'm a bit worried about the side effects here.
> >>> Can you try the followintg patch?
> >>> http://code.bulix.org/8cwk4c-794565?raw
> >>
> >> This doesn't help because the problem with the rotation_reflection is
> >> that it's 0 if "rotation" not present in the cmdline and then ilog2(0)
> >> returns -1. So the patch "drm/modes: Don't apply cmdline's rotation if
> >> it wasn't specified" should be correct in any case.
> >
> > So we would have the same issue with rotate=0 then?
>
> No, we won't. Rotation mode is parsed into the DRM_MODE bitmask and
> rotate=0 corresponds to DRM_MODE_ROTATE_0, which is BIT(0) as you may
> notice. Hence rotation_reflection=0 is always an invalid value, meaning
> that "rotate" option does not present in the cmdline. Please consult the
> code, in particular see drm_mode_parse_cmdline_options() which was
> written by yourself ;)
Sigh... You're right :)
Sorry for that, I'll reply to the other patch
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v1] drm/modes: Don't apply cmdline's rotation if it wasn't specified
From: Maxime Ripard @ 2019-07-12 19:54 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Maarten Lankhorst, Sean Paul,
Daniel Vetter, David Airlie, dri-devel, linux-tegra, linux-kernel
In-Reply-To: <20190711021313.29445-1-digetx@gmail.com>
On Thu, Jul 11, 2019 at 05:13:13AM +0300, Dmitry Osipenko wrote:
> The rotation mode from cmdline shouldn't be taken into account if it
> wasn't specified in the cmdline. This fixes ignored default display
> orientation when display mode is given using cmdline without the
> rotation being specified.
>
> Fixes: 1bf4e09227c3 ("drm/modes: Allow to specify rotation and reflection on the commandline")
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH 5.1 000/138] 5.1.18-stable review
From: Guenter Roeck @ 2019-07-12 20:21 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Jon Hunter, linux-kernel, torvalds, akpm, shuah, patches,
ben.hutchings, lkft-triage, stable, linux-tegra, j-keerthy
In-Reply-To: <20190712153035.GC13940@kroah.com>
On Fri, Jul 12, 2019 at 05:30:35PM +0200, Greg Kroah-Hartman wrote:
> On Fri, Jul 12, 2019 at 02:26:57PM +0100, Jon Hunter wrote:
> > Hi Greg,
> >
> > On 12/07/2019 13:17, Greg Kroah-Hartman wrote:
> > > This is the start of the stable review cycle for the 5.1.18 release.
> > > There are 138 patches in this series, all will be posted as a response
> > > to this one. If anyone has any issues with these being applied, please
> > > let me know.
> > >
> > > Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
> > > Anything received after that time might be too late.
> > >
> > > The whole patch series can be found in one patch at:
> > > https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.1.18-rc1.gz
> > > or in the git tree and branch at:
> > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.1.y
> > > and the diffstat can be found below.
> > >
> > > thanks,
> > >
> > > greg k-h
> > >
> > > -------------
> > > Pseudo-Shortlog of commits:
> >
> Both are now dropped, thanks. I'll push out a -rc2 with that changed.
>
Can you push that update into the git repository ?
v5.1.17-137-gde182b90f76d still has the problem.
Also:
Building powerpc:ppc6xx_defconfig ... failed
drivers/crypto/talitos.c: In function ‘get_request_hdr’:
include/linux/kernel.h:979:51: error:
dereferencing pointer to incomplete type ‘struct talitos_edesc’
Seen with both v4.19.58-92-gd66f8e7 and v5.1.17-137-gde182b90f76d.
This problem is caused by "crypto: talitos - fix hash on SEC1.", which will
need a proper backport - struct talitos_edesc is declared later in the
source file.
Guenter
^ permalink raw reply
* Re: [PATCH V5 02/18] pinctrl: tegra: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-07-13 5:31 UTC (permalink / raw)
To: Dmitry Osipenko, Linus Walleij
Cc: thierry.reding@gmail.com, Jon Hunter, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Stefan Agner, Mark Rutland,
Peter De Schrijver, Prashant Gaikwad, Stephen Boyd, linux-clk,
open list:GPIO SUBSYSTEM, jckuo, Joseph Lo, talho, linux-tegra,
linux-kernel@vger.kernel.org, Mikko Perttunen, spatra,
Rob Herring
In-Reply-To: <66b5e81b-d468-e2aa-7336-3d4854c234ab@gmail.com>
On 7/4/19 3:40 AM, Dmitry Osipenko wrote:
> 04.07.2019 10:31, Linus Walleij пишет:
>> On Sat, Jun 29, 2019 at 5:58 PM Dmitry Osipenko <digetx@gmail.com> wrote:
>>
>>> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it okay that pinctrl
>>> will be resumed after GPIO? Shouldn't a proper pin-muxing be selected at first?
>> Thierry sent some initial patches about this I think. We need to use
>> device links for this to work properly so he adds support for
>> linking the pinctrl and GPIO devices through the ranges.
>>
>> For links between pin control handles and their consumers, see also:
>> 036f394dd77f pinctrl: Enable device link creation for pin control
>> c6045b4e3cad pinctrl: stmfx: enable links creations
>> 489b64d66325 pinctrl: stm32: Add links to consumers
>>
>> I am using STM32 as guinea pig for this, consider adding links also
>> from the Tegra pinctrl. I might simply make these pinctrl consumer
>> to producer links default because I think it makes a lot sense.
> IIUC, currently the plan is to resume pinctrl *after* GPIO for Tegra210 [1]. But this
> contradicts to what was traditionally done for older Tegras where pinctrl was always
> resumed first and apparently it won't work well for the GPIO ranges as well. I think this
> and the other patchsets related to suspend-resume still need some more thought.
>
> [1] https://patchwork.kernel.org/patch/11012077/
Park bit was introduced from Tegra210 onwards and during suspend/resume,
requirement of gpio restore prior to pinctrl restore is not required for
prior Tegra210.
Also currently pinctrl suspend/resume implementation for prior Tegra210
is not yet upstreamed but having gpio restore prior to pinmux during
suspend/resume should not cause any issue for prior tegra's as well as
gpio resume restores pins back to same gpio config as they were during
suspend entry.
^ permalink raw reply
* Re: [PATCH V5 02/18] pinctrl: tegra: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-07-13 5:48 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <a262cbb3-845c-3ad1-16cc-375a24b9f7e9@gmail.com>
On 6/29/19 8:46 AM, Dmitry Osipenko wrote:
> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>
>> During suspend, context of all pinctrl registers are stored and
>> on resume they are all restored to have all the pinmux and pad
>> configuration for normal operation.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++++++++++++++++++++++++++
>> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
>> drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
>> 3 files changed, 56 insertions(+)
>>
>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
>> index 34596b246578..e7c0a1011cba 100644
>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
>> @@ -621,6 +621,43 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
>> }
>> }
>>
>> +static int tegra_pinctrl_suspend(struct device *dev)
>> +{
>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>> + u32 *backup_regs = pmx->backup_regs;
>> + u32 *regs;
>> + unsigned int i, j;
>> +
>> + for (i = 0; i < pmx->nbanks; i++) {
>> + regs = pmx->regs[i];
>> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
>> + *backup_regs++ = readl(regs++);
>> + }
>> +
>> + return pinctrl_force_sleep(pmx->pctl);
>> +}
>> +
>> +static int tegra_pinctrl_resume(struct device *dev)
>> +{
>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>> + u32 *backup_regs = pmx->backup_regs;
>> + u32 *regs;
>> + unsigned int i, j;
>> +
>> + for (i = 0; i < pmx->nbanks; i++) {
>> + regs = pmx->regs[i];
>> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
>> + writel(*backup_regs++, regs++);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +const struct dev_pm_ops tegra_pinctrl_pm = {
>> + .suspend = &tegra_pinctrl_suspend,
>> + .resume = &tegra_pinctrl_resume
>> +};
> Hm, so this are the generic platform-driver suspend-resume OPS here, which is very
> nice! But.. shouldn't pinctrl be resumed before the CLK driver (which is syscore_ops
> in this version of the series)? .. Given that "clock" function may need to be
> selected for some of the pins.
selection of clock functions on some Tegra pins through corresponding
pinmux (like extperiph clks) can happen after clock driver resume as
well where clock source is restored to state during suspend before
selecting clock function on that pin.
^ permalink raw reply
* Re: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks
From: Sowjanya Komatineni @ 2019-07-13 5:54 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <a5e1a6df-dff7-9e0c-9551-f78103a5462f@gmail.com>
On 6/29/19 8:10 AM, Dmitry Osipenko wrote:
> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>> This patch adds system suspend and resume support for Tegra210
>> clocks.
>>
>> All the CAR controller settings are lost on suspend when core power
>> goes off.
>>
>> This patch has implementation for saving and restoring all the PLLs
>> and clocks context during system suspend and resume to have the
>> clocks back to same state for normal operation.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-tegra210.c | 115 ++++++++++++++++++++++++++++++++++++++-
>> drivers/clk/tegra/clk.c | 14 +++++
>> drivers/clk/tegra/clk.h | 1 +
>> 3 files changed, 127 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 1c08c53482a5..1b839544e086 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -9,10 +9,12 @@
>> #include <linux/clkdev.h>
>> #include <linux/of.h>
>> #include <linux/of_address.h>
>> +#include <linux/of_platform.h>
>> #include <linux/delay.h>
>> #include <linux/export.h>
>> #include <linux/mutex.h>
>> #include <linux/clk/tegra.h>
>> +#include <linux/syscore_ops.h>
>> #include <dt-bindings/clock/tegra210-car.h>
>> #include <dt-bindings/reset/tegra210-car.h>
>> #include <linux/iopoll.h>
>> @@ -20,6 +22,7 @@
>> #include <soc/tegra/pmc.h>
>>
>> #include "clk.h"
>> +#include "clk-dfll.h"
>> #include "clk-id.h"
>>
>> /*
>> @@ -225,6 +228,7 @@
>>
>> #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
>> #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
>> +#define CPU_SOFTRST_CTRL 0x380
>>
>> #define LVL2_CLK_GATE_OVRA 0xf8
>> #define LVL2_CLK_GATE_OVRC 0x3a0
>> @@ -2820,6 +2824,7 @@ static int tegra210_enable_pllu(void)
>> struct tegra_clk_pll_freq_table *fentry;
>> struct tegra_clk_pll pllu;
>> u32 reg;
>> + int ret;
>>
>> for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
>> if (fentry->input_rate == pll_ref_freq)
>> @@ -2847,10 +2852,10 @@ static int tegra210_enable_pllu(void)
>> fence_udelay(1, clk_base);
>> reg |= PLL_ENABLE;
>> writel(reg, clk_base + PLLU_BASE);
>> + fence_udelay(1, clk_base);
>>
>> - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
>> - reg & PLL_BASE_LOCK, 2, 1000);
>> - if (!(reg & PLL_BASE_LOCK)) {
>> + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
>> + if (ret) {
>> pr_err("Timed out waiting for PLL_U to lock\n");
>> return -ETIMEDOUT;
>> }
>> @@ -3283,6 +3288,103 @@ static void tegra210_disable_cpu_clock(u32 cpu)
>> }
>>
>> #ifdef CONFIG_PM_SLEEP
>> +static u32 cpu_softrst_ctx[3];
>> +static struct platform_device *dfll_pdev;
>> +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
>> +#define car_writel(_val, _base, _off) \
>> + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
>> +
>> +static int tegra210_clk_suspend(void)
>> +{
>> + unsigned int i;
>> + struct device_node *node;
>> +
>> + tegra_cclkg_burst_policy_save_context();
>> +
>> + if (!dfll_pdev) {
>> + node = of_find_compatible_node(NULL, NULL,
>> + "nvidia,tegra210-dfll");
>> + if (node)
>> + dfll_pdev = of_find_device_by_node(node);
>> +
>> + of_node_put(node);
>> + if (!dfll_pdev)
>> + pr_err("dfll node not found. no suspend for dfll\n");
>> + }
>> +
>> + if (dfll_pdev)
>> + tegra_dfll_suspend(dfll_pdev);
>> +
>> + /* Enable PLLP_OUT_CPU after dfll suspend */
>> + tegra_clk_set_pllp_out_cpu(true);
>> +
>> + tegra_sclk_cclklp_burst_policy_save_context();
>> +
>> + clk_save_context();
>> +
>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>> + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra210_clk_resume(void)
>> +{
>> + unsigned int i;
>> + struct clk_hw *parent;
>> + struct clk *clk;
>> +
>> + /*
>> + * clk_restore_context restores clocks as per the clock tree.
>> + *
>> + * dfllCPU_out is first in the clock tree to get restored and it
>> + * involves programming DFLL controller along with restoring CPUG
>> + * clock burst policy.
>> + *
>> + * DFLL programming needs dfll_ref and dfll_soc peripheral clocks
>> + * to be restores which are part ofthe peripheral clocks.
>> + * So, peripheral clocks restore should happen prior to dfll clock
>> + * restore.
>> + */
>> +
>> + tegra_clk_osc_resume(clk_base);
>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>> + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
>> +
>> + /* restore all plls and peripheral clocks */
>> + tegra210_init_pllu();
>> + clk_restore_context();
>> +
>> + fence_udelay(5, clk_base);
>> +
>> + /* resume SCLK and CPULP clocks */
>> + tegra_sclk_cpulp_burst_policy_restore_context();
>> +
>> + /*
>> + * restore CPUG clocks:
>> + * - enable DFLL in open loop mode
>> + * - switch CPUG to DFLL clock source
>> + * - close DFLL loop
>> + * - sync PLLX state
>> + */
>> + if (dfll_pdev)
>> + tegra_dfll_resume(dfll_pdev, false);
>> +
>> + tegra_cclkg_burst_policy_restore_context();
>> + fence_udelay(2, clk_base);
>> +
>> + if (dfll_pdev)
>> + tegra_dfll_resume(dfll_pdev, true);
>> +
>> + parent = clk_hw_get_parent(__clk_get_hw(clks[TEGRA210_CLK_CCLK_G]));
>> + clk = clks[TEGRA210_CLK_PLL_X];
>> + if (parent != __clk_get_hw(clk))
>> + tegra_clk_sync_state_pll(__clk_get_hw(clk));
>> +
>> + /* Disable PLL_OUT_CPU after DFLL resume */
>> + tegra_clk_set_pllp_out_cpu(false);
>> +}
>> +
>> static void tegra210_cpu_clock_suspend(void)
>> {
>> /* switch coresite to clk_m, save off original source */
>> @@ -3298,6 +3400,11 @@ static void tegra210_cpu_clock_resume(void)
>> }
>> #endif
>>
>> +static struct syscore_ops tegra_clk_syscore_ops = {
>> + .suspend = tegra210_clk_suspend,
>> + .resume = tegra210_clk_resume,
>> +};
>> +
>> static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
>> .wait_for_reset = tegra210_wait_cpu_in_reset,
>> .disable_clock = tegra210_disable_cpu_clock,
>> @@ -3583,5 +3690,7 @@ static void __init tegra210_clock_init(struct device_node *np)
>> tegra210_mbist_clk_init();
>>
>> tegra_cpu_car_ops = &tegra210_cpu_car_ops;
>> +
>> + register_syscore_ops(&tegra_clk_syscore_ops);
>> }
> Is it really worthwhile to use syscore_ops for suspend/resume given that drivers for
> won't resume before the CLK driver anyway? Are there any other options for CLK
> suspend/resume?
>
> I'm also not sure whether PM runtime API could be used at all in the context of
> syscore_ops ..
>
> Secondly, what about to use generic clk_save_context() / clk_restore_context()
> helpers for the suspend-resume? It looks to me that some other essential (and proper)
> platform driver (soc/tegra/? PMC?) should suspend-resume the clocks using the generic
> CLK Framework API.
Clock resume should happen very early to restore peripheral and cpu
clocks very early than peripheral drivers resume happens.
this patch series uses clk_save_context and clk_restore_context for
corresponding divider, pll, pllout.. save and restore context.
But as there is dependency on dfll resume and cpu and pllx clocks
restore, couldnt use clk_save_context and clk_restore_context for dfll.
So implemented recommended dfll resume sequence in main Tegra210 clock
driver along with invoking clk_save_context/clk_restore_context where
all other clocks save/restore happens as per clock tree traversal.
^ permalink raw reply
* Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
From: Vidya Sagar @ 2019-07-13 7:04 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: mark.rutland, devicetree, mperttunen, mmaddireddy, linux-pci,
catalin.marinas, will.deacon, linux-kernel, kthota, kishon,
linux-tegra, robh+dt, thierry.reding, gustavo.pimentel,
jingoohan1, bhelgaas, digetx, jonathanh, linux-arm-kernel,
sagar.tv
In-Reply-To: <20190712160754.GA24285@e121166-lin.cambridge.arm.com>
On 7/12/2019 9:37 PM, Lorenzo Pieralisi wrote:
> On Fri, Jul 12, 2019 at 09:02:49PM +0530, Vidya Sagar wrote:
>
> [...]
>
>>>> +static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
>>>> +{
>>>> + struct tegra_pcie_dw *pcie = arg;
>>>> +
>>>> + if (pcie->mode == DW_PCIE_RC_TYPE)
>>>> + return tegra_pcie_rp_irq_handler(pcie);
>>>
>>> What's the point of registering the handler if mode != DW_PCIE_RC_TYPE ?
>> Currently this driver supports only root port mode but we have a plan
>> to add support for endpoint mode (as Tegra194 as dual mode
>> controllers) also in future and when that happens, we'll have a
>> corresponding tegra_pcie_ep_irq_handler() to take care of ep specific
>> interrupts.
>
> Sure, that's why you should add tegra_pcie_dw->mode when it is needed,
> not in this patch.
Ok.
>
> [...]
>
>>>> +static int tegra_pcie_dw_host_init(struct pcie_port *pp)
>>>> +{
>>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>>>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>>>> + u32 val, tmp, offset, speed;
>>>> + unsigned int count;
>>>> + u16 val_w;
>>>> +
>>>> +core_init:
>>>
>>> I think it would be cleaner to include all registers programming
>>> within a function and we remove this label (and goto) below.
>> Some background: As per spec r4.0 v1.0, downstream ports that support
>> 16.0 GT/s must support Scaled Flow Control (sec 3.4.2) and Tegra194's
>> downstream ports being 16.0 GT/s capable, enable scaled flow control
>> by having Data Link Feature (sec 7.7.4) enabled by default. There is
>> one endpoint (ASMedia USB3.0 controller) that doesn't link up with
>> root port because of this (i.e. DLF being enabled). The way we are
>> detecting this situation is to check for partial linkup i.e. one of
>> application logic registers (i.e. from "appl" region) says link is up
>> but the same is not reflected in configuration space of root port.
>> Recommendation from our hardware team in this situation is to disable
>> DLF in root port and try link up with endpoint again. To achieve
>> this, we put the core through reset cycle, disable DLF and proceed
>> with configuring all other registers and check for link up.
>>
>> Initially in Patch-1, I didn't have goto statement but a recursion
>> with depth-1 (as the above situation occurs only once). It was
>> reviewed @ http://patchwork.ozlabs.org/patch/1065707/ and Thierry said
>> it would be simpler to use a goto instead of calling the same function
>> again. So, I modified the code accordingly. Please do let me know if
>> you strongly feel we should call tegra_pcie_dw_host_init() instead of
>> goto here. I'll change it.
>
> I did not say we should call tegra_pcie_dw_host_init(), sorry for
> not being clear. What I asked is factoring out registers programming
> in a function and call it where core_init: label is and call it
> again if DLF enablement causes link up to fail.
Ok.
>
> [...]
>
>>>> +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
>>>> + bool enable)
>>>> +{
>>>> + struct mrq_uphy_response resp;
>>>> + struct tegra_bpmp_message msg;
>>>> + struct mrq_uphy_request req;
>>>> + int err;
>>>> +
>>>> + if (pcie->cid == 5)
>>>> + return 0;
>>>
>>> What's wrong with cid == 5 ? Explain please.
>> Controller with ID=5 doesn't need any programming to enable it which is
>> done here through calling firmware API.
>>
>>>
>>>> + memset(&req, 0, sizeof(req));
>>>> + memset(&resp, 0, sizeof(resp));
>>>> +
>>>> + req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
>>>> + req.controller_state.pcie_controller = pcie->cid;
>>>> + req.controller_state.enable = enable;
>>>> +
>>>> + memset(&msg, 0, sizeof(msg));
>>>> + msg.mrq = MRQ_UPHY;
>>>> + msg.tx.data = &req;
>>>> + msg.tx.size = sizeof(req);
>>>> + msg.rx.data = &resp;
>>>> + msg.rx.size = sizeof(resp);
>>>> +
>>>> + if (irqs_disabled())
>>>
>>> Can you explain to me what this check is meant to achieve please ?
>> Firmware interface provides different APIs to be called when there are
>> no interrupts enabled in the system (noirq context) and otherwise
>> hence checking that situation here and calling appropriate API.
>
> That's what I am questioning. Being called from {suspend/resume}_noirq()
> callbacks (if that's the code path this check caters for) does not mean
> irqs_disabled() == true.
Agree.
Actually, I got a hint of having this check from the following.
Both tegra_bpmp_transfer_atomic() and tegra_bpmp_transfer() are indirectly
called by APIs registered with .master_xfer() and .master_xfer_atomic() hooks of
struct i2c_algorithm and the decision to call which one of these is made using the
following check in i2c-core.h file.
static inline bool i2c_in_atomic_xfer_mode(void)
{
return system_state > SYSTEM_RUNNING && irqs_disabled();
}
I think I should use this condition as is IIUC.
Please let me know if there are any concerns with this.
>
> Actually, if tegra_bpmp_transfer() requires IRQs to be enabled you may
> even end up in a situation where that blocking call does not wake up
> because the IRQ in question was disabled in the NOIRQ suspend/resume
> phase.
>
> [...]
>
>>>> +static int tegra_pcie_dw_probe(struct platform_device *pdev)
>>>> +{
>>>> + const struct tegra_pcie_soc *data;
>>>> + struct device *dev = &pdev->dev;
>>>> + struct resource *atu_dma_res;
>>>> + struct tegra_pcie_dw *pcie;
>>>> + struct resource *dbi_res;
>>>> + struct pcie_port *pp;
>>>> + struct dw_pcie *pci;
>>>> + struct phy **phys;
>>>> + char *name;
>>>> + int ret;
>>>> + u32 i;
>>>> +
>>>> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
>>>> + if (!pcie)
>>>> + return -ENOMEM;
>>>> +
>>>> + pci = &pcie->pci;
>>>> + pci->dev = &pdev->dev;
>>>> + pci->ops = &tegra_dw_pcie_ops;
>>>> + pp = &pci->pp;
>>>> + pcie->dev = &pdev->dev;
>>>> +
>>>> + data = (struct tegra_pcie_soc *)of_device_get_match_data(dev);
>>>> + if (!data)
>>>> + return -EINVAL;
>>>> + pcie->mode = (enum dw_pcie_device_mode)data->mode;
>>>> +
>>>> + ret = tegra_pcie_dw_parse_dt(pcie);
>>>> + if (ret < 0) {
>>>> + dev_err(dev, "Failed to parse device tree: %d\n", ret);
>>>> + return ret;
>>>> + }
>>>> +
>>>> + pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
>>>> + if (IS_ERR(pcie->pex_ctl_supply)) {
>>>> + dev_err(dev, "Failed to get regulator: %ld\n",
>>>> + PTR_ERR(pcie->pex_ctl_supply));
>>>> + return PTR_ERR(pcie->pex_ctl_supply);
>>>> + }
>>>> +
>>>> + pcie->core_clk = devm_clk_get(dev, "core");
>>>> + if (IS_ERR(pcie->core_clk)) {
>>>> + dev_err(dev, "Failed to get core clock: %ld\n",
>>>> + PTR_ERR(pcie->core_clk));
>>>> + return PTR_ERR(pcie->core_clk);
>>>> + }
>>>> +
>>>> + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>>>> + "appl");
>>>> + if (!pcie->appl_res) {
>>>> + dev_err(dev, "Failed to find \"appl\" region\n");
>>>> + return PTR_ERR(pcie->appl_res);
>>>> + }
>>>> + pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
>>>> + if (IS_ERR(pcie->appl_base))
>>>> + return PTR_ERR(pcie->appl_base);
>>>> +
>>>> + pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
>>>> + if (IS_ERR(pcie->core_apb_rst)) {
>>>> + dev_err(dev, "Failed to get APB reset: %ld\n",
>>>> + PTR_ERR(pcie->core_apb_rst));
>>>> + return PTR_ERR(pcie->core_apb_rst);
>>>> + }
>>>> +
>>>> + phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
>>>> + if (!phys)
>>>> + return PTR_ERR(phys);
>>>> +
>>>> + for (i = 0; i < pcie->phy_count; i++) {
>>>> + name = kasprintf(GFP_KERNEL, "p2u-%u", i);
>>>> + if (!name) {
>>>> + dev_err(dev, "Failed to create P2U string\n");
>>>> + return -ENOMEM;
>>>> + }
>>>> + phys[i] = devm_phy_get(dev, name);
>>>> + kfree(name);
>>>> + if (IS_ERR(phys[i])) {
>>>> + ret = PTR_ERR(phys[i]);
>>>> + dev_err(dev, "Failed to get PHY: %d\n", ret);
>>>> + return ret;
>>>> + }
>>>> + }
>>>> +
>>>> + pcie->phys = phys;
>>>> +
>>>> + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
>>>> + if (!dbi_res) {
>>>> + dev_err(dev, "Failed to find \"dbi\" region\n");
>>>> + return PTR_ERR(dbi_res);
>>>> + }
>>>> + pcie->dbi_res = dbi_res;
>>>> +
>>>> + pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
>>>> + if (IS_ERR(pci->dbi_base))
>>>> + return PTR_ERR(pci->dbi_base);
>>>> +
>>>> + /* Tegra HW locates DBI2 at a fixed offset from DBI */
>>>> + pci->dbi_base2 = pci->dbi_base + 0x1000;
>>>> +
>>>> + atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>>>> + "atu_dma");
>>>> + if (!atu_dma_res) {
>>>> + dev_err(dev, "Failed to find \"atu_dma\" region\n");
>>>> + return PTR_ERR(atu_dma_res);
>>>> + }
>>>> + pcie->atu_dma_res = atu_dma_res;
>>>> + pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
>>>> + if (IS_ERR(pci->atu_base))
>>>> + return PTR_ERR(pci->atu_base);
>>>> +
>>>> + pcie->core_rst = devm_reset_control_get(dev, "core");
>>>> + if (IS_ERR(pcie->core_rst)) {
>>>> + dev_err(dev, "Failed to get core reset: %ld\n",
>>>> + PTR_ERR(pcie->core_rst));
>>>> + return PTR_ERR(pcie->core_rst);
>>>> + }
>>>> +
>>>> + pp->irq = platform_get_irq_byname(pdev, "intr");
>>>> + if (!pp->irq) {
>>>> + dev_err(dev, "Failed to get \"intr\" interrupt\n");
>>>> + return -ENODEV;
>>>> + }
>>>> +
>>>> + ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler,
>>>> + IRQF_SHARED, "tegra-pcie-intr", pcie);
>>>> + if (ret) {
>>>> + dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, ret);
>>>> + return ret;
>>>> + }
>>>> +
>>>> + pcie->bpmp = tegra_bpmp_get(dev);
>>>> + if (IS_ERR(pcie->bpmp))
>>>> + return PTR_ERR(pcie->bpmp);
>>>> +
>>>> + platform_set_drvdata(pdev, pcie);
>>>> +
>>>> + if (pcie->mode == DW_PCIE_RC_TYPE) {
>>>> + ret = tegra_pcie_config_rp(pcie);
>>>> + if (ret && ret != -ENOMEDIUM)
>>>> + goto fail;
>>>> + else
>>>> + return 0;
>>>
>>> So if the link is not up we still go ahead and make probe
>>> succeed. What for ?
>> We may need root port to be available to support hot-plugging of
>> endpoint devices, so, we don't fail the probe.
>
> We need it or we don't. If you do support hotplugging of endpoint
> devices point me at the code, otherwise link up failure means
> failure to probe.
Currently hotplugging of endpoint is not supported, but it is one of the use cases that
we may add support for in future.
But, why should we fail probe if link up doesn't happen? As such, nothing went wrong in
terms of root port initialization right?
I checked other DWC based implementations and following are not failing the probe
pci-dra7xx.c, pcie-armada8k.c, pcie-artpec6.c, pcie-histb.c, pcie-kirin.c, pcie-spear13xx.c,
pci-exynos.c, pci-imx6.c, pci-keystone.c, pci-layerscape.c
Although following do fail the probe if link is not up.
pcie-qcom.c, pcie-uniphier.c, pci-meson.c
So, to me, it looks more like a choice we can make whether to fail the probe or not and in this
case we are choosing not to fail.
>
>>>> + }
>>>> +
>>>> +fail:
>>>> + tegra_bpmp_put(pcie->bpmp);
>>>> + return ret;
>>>> +}
>>>> +
>>>> +static int tegra_pcie_dw_remove(struct platform_device *pdev)
>>>> +{
>>>> + struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
>>>> +
>>>> + if (pcie->mode != DW_PCIE_RC_TYPE)
>>>> + return 0;
>>>> +
>>>> + if (!pcie->link_state)
>>>> + return 0;
>>>> +
>>>> + debugfs_remove_recursive(pcie->debugfs);
>>>> + tegra_pcie_deinit_controller(pcie);
>>>> + pm_runtime_put_sync(pcie->dev);
>>>> + pm_runtime_disable(pcie->dev);
>>>> + tegra_bpmp_put(pcie->bpmp);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int tegra_pcie_dw_suspend_late(struct device *dev)
>>>> +{
>>>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>>>> + u32 val;
>>>> +
>>>> + if (!pcie->link_state)
>>>> + return 0;
>>>> +
>>>> + /* Enable HW_HOT_RST mode */
>>>> + val = appl_readl(pcie, APPL_CTRL);
>>>> + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
>>>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
>>>> + val |= APPL_CTRL_HW_HOT_RST_EN;
>>>> + appl_writel(pcie, val, APPL_CTRL);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>>>> +{
>>>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>>>> +
>>>> + if (!pcie->link_state)
>>>> + return 0;
>>>> +
>>>> + /* Save MSI interrupt vector */
>>>> + pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
>>>> + PORT_LOGIC_MSI_CTRL_INT_0_EN);
>>>> + tegra_pcie_downstream_dev_to_D0(pcie);
>>>
>>> I think this requires some comments. AFAIU this is allowed by
>>> the PCI specs (PCI Express Base 4.0 r1.0 September 29-2017,
>>> 5.2 Link State Power Management). However, I would like to
>>> understand how this plays with the D state the devices are left
>>> in upon system suspend.
>>>
>>> "As the following example illustrates, it is also possible to remove
>>> power without first placing all Functions into D3Hot".
>>>
>>> I assume that's what happens on this platform to allow L2 entry but
>>> again, this needs clarification.
>> Yes. It is true that in the case of Tegra194, it brings devices back
>> to D0 before putting link to L2 state.
>
> Comment it, extensively, so that anyone reading the code understands
> why it is done so and what happens to devices then.
I added comment in tegra_pcie_deinit_controller() where this API is called
but I think I should move the comment inside tegra_pcie_downstream_dev_to_D0()
API and also add more info to it.
I'll take care of it in the next patch.
>
> Lorenzo
>
^ permalink raw reply
* Re: [PATCH 5.1 000/138] 5.1.18-stable review
From: Greg Kroah-Hartman @ 2019-07-13 8:22 UTC (permalink / raw)
To: Guenter Roeck
Cc: Jon Hunter, linux-kernel, torvalds, akpm, shuah, patches,
ben.hutchings, lkft-triage, stable, linux-tegra, j-keerthy
In-Reply-To: <20190712202141.GA18698@roeck-us.net>
On Fri, Jul 12, 2019 at 01:21:41PM -0700, Guenter Roeck wrote:
> On Fri, Jul 12, 2019 at 05:30:35PM +0200, Greg Kroah-Hartman wrote:
> > On Fri, Jul 12, 2019 at 02:26:57PM +0100, Jon Hunter wrote:
> > > Hi Greg,
> > >
> > > On 12/07/2019 13:17, Greg Kroah-Hartman wrote:
> > > > This is the start of the stable review cycle for the 5.1.18 release.
> > > > There are 138 patches in this series, all will be posted as a response
> > > > to this one. If anyone has any issues with these being applied, please
> > > > let me know.
> > > >
> > > > Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
> > > > Anything received after that time might be too late.
> > > >
> > > > The whole patch series can be found in one patch at:
> > > > https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.1.18-rc1.gz
> > > > or in the git tree and branch at:
> > > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.1.y
> > > > and the diffstat can be found below.
> > > >
> > > > thanks,
> > > >
> > > > greg k-h
> > > >
> > > > -------------
> > > > Pseudo-Shortlog of commits:
> > >
> > Both are now dropped, thanks. I'll push out a -rc2 with that changed.
> >
>
> Can you push that update into the git repository ?
> v5.1.17-137-gde182b90f76d still has the problem.
Odd, I thought I did this. Pushed out again just to be sure.
> Also:
>
> Building powerpc:ppc6xx_defconfig ... failed
>
> drivers/crypto/talitos.c: In function ‘get_request_hdr’:
> include/linux/kernel.h:979:51: error:
> dereferencing pointer to incomplete type ‘struct talitos_edesc’
>
> Seen with both v4.19.58-92-gd66f8e7 and v5.1.17-137-gde182b90f76d.
>
> This problem is caused by "crypto: talitos - fix hash on SEC1.", which will
> need a proper backport - struct talitos_edesc is declared later in the
> source file.
Ick, let me go drop this one after breakfast...
greg k-h
^ permalink raw reply
* Re: [PATCH 5.1 000/138] 5.1.18-stable review
From: Jon Hunter @ 2019-07-13 9:16 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: linux-kernel, torvalds, akpm, linux, shuah, patches,
ben.hutchings, lkft-triage, stable, linux-tegra, j-keerthy
In-Reply-To: <20190712153035.GC13940@kroah.com>
On 12/07/2019 16:30, Greg Kroah-Hartman wrote:
> On Fri, Jul 12, 2019 at 02:26:57PM +0100, Jon Hunter wrote:
>> Hi Greg,
>>
>> On 12/07/2019 13:17, Greg Kroah-Hartman wrote:
>>> This is the start of the stable review cycle for the 5.1.18 release.
>>> There are 138 patches in this series, all will be posted as a response
>>> to this one. If anyone has any issues with these being applied, please
>>> let me know.
>>>
>>> Responses should be made by Sun 14 Jul 2019 12:14:36 PM UTC.
>>> Anything received after that time might be too late.
>>>
>>> The whole patch series can be found in one patch at:
>>> https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.1.18-rc1.gz
>>> or in the git tree and branch at:
>>> git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.1.y
>>> and the diffstat can be found below.
>>>
>>> thanks,
>>>
>>> greg k-h
>>>
>>> -------------
>>> Pseudo-Shortlog of commits:
>>
>> ...
>>
>>> Keerthy <j-keerthy@ti.com>
>>> ARM: dts: dra71x: Disable usb4_tm target module
>>
>> ...
>>
>>> Keerthy <j-keerthy@ti.com>
>>> ARM: dts: dra76x: Disable usb4_tm target module
>>
>> The above commits are generating the following compilation errors for
>> ARM ...
>>
>> Error:
>> /dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm/boot/dts/dra71x.dtsi:15.1-9
>> Label or path usb4_tm not found
>>
>> Error:
>> /dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm/boot/dts/dra76x.dtsi:89.1-9
>> Label or path usb4_tm not found
>>
>> After reverting these two, I no longer see these errors.
>
> Both are now dropped, thanks. I'll push out a -rc2 with that changed.
Hmmm ... -rc2 still not building ...
Error:
/dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm/boot/dts/dra71x.dtsi:11.1-11
Label or path rtctarget not found
Error:
/dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm/boot/dts/dra71x.dtsi:15.1-9
Label or path usb4_tm not found
I still see the following commit in -rc2 ...
commit 0caa574b3244cd863dd74bde680a6309cb8803ad
Author: Keerthy <j-keerthy@ti.com>
Date: Fri May 17 06:44:09 2019 +0530
ARM: dts: dra71x: Disable usb4_tm target module
In -rc1 I see there were 4 changes from Keerthy, any chance you reverted
one of the rtc patches and not the above? Looks like the following is
missing from -rc2 ...
Keerthy <j-keerthy@ti.com>
ARM: dts: dra76x: Disable rtc target module
Cheers
Jon
--
nvpublic
^ permalink raw reply
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