messages from 2026-10-29 14:58:07 to 2026-10-29 23:21:56 UTC [more...]
[PATCH v5 0/2] Add SMCCC cache clean/invalidate provider
2026-10-29 23:21 UTC (3+ messages)
` [PATCH v5 2/2] cache: add SMCCC-backed cache invalidate provider
[PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices
2026-10-29 23:03 UTC (5+ messages)
` [PATCH v16 17/18] PCI/CXL: Restore CXL state after CXL bus reset
` [PATCH v16 18/18] cxl: Add KUnit checks for HDM decoder unpacking
[PATCH 5.10.y] serial: tegra: Add missing clk_disable_unprepare() in tegra_uart_hw_init()
2026-10-29 18:43 UTC (2+ messages)
[PATCH] PCI/CXL: Flush host and device caches for CXL bus reset
2026-10-29 18:09 UTC (2+ messages)
[RFC PATCH 0/6] dma-buf: Phase out is_signaled() race
2026-10-29 16:00 UTC (3+ messages)
` [RFC PATCH 5/6] dma-buf: dma-fence: Close race in dma_fence_is_signaled() by default
[PATCH v5 00/11] drm/tegra: Add support for Tegra20/Tegra30 8-bit CPU interface
2026-10-29 15:29 UTC (12+ messages)
` [PATCH v5 01/11] drm: Add MIPI DBI bus support
` [PATCH v5 02/11] dt-bindings: display: panel: Document Hitachi TX10D07VM0BAA and LG LH400WV3 panels
` [PATCH v5 03/11] drm/panel: Add Hitachi TX10D07VM0BAA MIPI DBI Type B panel driver
` [PATCH v5 04/11] drm/panel: Add LG LH400WV3-SD04 "
` [PATCH v5 05/11] drm/tegra: dc: Refactor and expand header
` [PATCH v5 06/11] dt-bindings: display: tegra: Document Tegra20 DSI port
` [PATCH v5 07/11] drm/tegra: Make panel parsing by tegra_output_probe() optional
` [PATCH v5 08/11] drm/tegra: Convert to use atomic versions of drm_encoder_helper_funcs
` [PATCH v5 09/11] drm/tegra: rgb: Parameterize configuration based on bus flags
` [PATCH v5 10/11] dt-bindings: display: tegra: Document 8-bit CPU parallel interface
` [PATCH v5 11/11] drm/tegra: Add support for 8-bit CPU interface
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