messages from 2026-10-29 16:00:35 to 2026-10-30 05:54:31 UTC [more...]
[PATCH v2] pwm: tegra: Fix value discarding for duty and period
2026-10-30 5:54 UTC (2+ messages)
[PATCH] drm/tegra: Fix dma-buf reference on import errors
2026-10-30 5:32 UTC (2+ messages)
[PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices
2026-10-30 4:01 UTC (9+ messages)
` [PATCH v16 06/18] cxl: Move HDM decoder helpers to built-in code
` [PATCH v16 12/18] PCI/CXL: Add CXL Device Reset sequencing
` [PATCH v16 13/18] cxl: Validate and synchronize HDM ranges around reset
[PATCH 00/35] drm/panel: let the panels use the atomic state
2026-10-30 3:06 UTC (3+ messages)
` [PATCH 20/35] drm/sun4i: set the panel orientation on the connector
[PATCH v3 00/10] Make the 32-bit ARM DMA API work with normal IOMMU DMA default domains (+ Tegra PoC)
2026-10-30 2:37 UTC (3+ messages)
[PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices
2026-10-30 1:43 UTC (19+ messages)
` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration
` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing
` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset
` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset
` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks
[PATCH v5 0/2] Add SMCCC cache clean/invalidate provider
2026-10-29 23:21 UTC (3+ messages)
` [PATCH v5 2/2] cache: add SMCCC-backed cache invalidate provider
[PATCH 5.10.y] serial: tegra: Add missing clk_disable_unprepare() in tegra_uart_hw_init()
2026-10-29 18:43 UTC (2+ messages)
[PATCH] PCI/CXL: Flush host and device caches for CXL bus reset
2026-10-29 18:09 UTC (2+ messages)
[RFC PATCH 0/6] dma-buf: Phase out is_signaled() race
2026-10-29 16:00 UTC (3+ messages)
` [RFC PATCH 5/6] dma-buf: dma-fence: Close race in dma_fence_is_signaled() by default
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