From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Bresticker Subject: Re: [PATCH v10 3/9] dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support Date: Fri, 4 Mar 2016 13:41:11 -0800 Message-ID: References: <1457108379-20794-1-git-send-email-thierry.reding@gmail.com> <1457108379-20794-3-git-send-email-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <1457108379-20794-3-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding Cc: Kishon Vijay Abraham I , Linus Walleij , Stephen Warren , Alexandre Courbot , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala List-Id: linux-tegra@vger.kernel.org On Fri, Mar 4, 2016 at 8:19 AM, Thierry Reding wrote: > From: Thierry Reding > > Extend the binding to cover the set of feature found in Tegra210. > > Signed-off-by: Thierry Reding > +PCIe pad: > +--------- > + > +Required properties: > +- clocks: Must contain an entry for each entry in clock-names. > +- clock-names: Must contain the following entries: > + - "pll": phandle and specifier referring to the PLLE > +- resets: Must contain an entry for each entry in reset-names. > +- reset-names: Must contain the following entries: > + - "phy": reset for the PCIe UPHY block > + > +SATA pad: > +--------- > + > +Required properties: > +- resets: Must contain an entry for each entry in reset-names. > +- reset-names: Must contain the following entries: > + - "phy": reset for the SATA UPHY block Doesn't the SATA pad require PLLE as well? You've included it in the example DT fragment, but it's absent here.