Re: [PATCH v2 1/2] clocksource/drivers/timer-tegra186: add WDIOC_GETTIMELEFT support

["Thierry Reding" <thierry.reding@gmail.com>]

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On Sat Feb 24, 2024 at 12:51 AM CET, Pohsun Su wrote:
> Hi Thierry,
>
> >> +static unsigned int tegra186_wdt_get_timeleft(struct watchdog_device *wdd)
> >> +{
> >> +     struct tegra186_wdt *wdt = to_tegra186_wdt(wdd);
> >> +     u32 timeleft;
> >> +     u32 expiration;
> >> +
> >> +     if (!watchdog_active(&wdt->base)) {
> >> +             /* return zero if the watchdog timer is not activated. */
> >> +             return 0;
> >> +     }
> >> +
> >> +     /*
> >> +      * System power-on reset occurs on the fifth expiration of the watchdog timer and so
> >
> >Is "system power-on reset" really what this is called? Power-on reset
> >sounds like something that only happens after you power the device on,
> >not something that can be triggered by the watchdog.
>
> I will change it from "system power-on reset" to "System POR(Power On Reset)" in next patch.
> AFAIK Power On Reset is used for decribing resetting circuits and initialing whatever it needs
> when received a POR signal after powered up. This term should also be applicable for
> hardware watchdog reset since the system is already powered up at that moment and 

"System POR" isn't an improvement over "system power-on reset". I'm
mainly concerned that somebody might mistake this to somehow mean that
there's an actual power cycle, which, as I understand, there isn't. So
maybe just explain that this type of reset will put the system into the
same state that it would be after a power cycle?

Thierry

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