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Wed, 08 Dec 2021 06:36:06 -0800 (PST) Received: from orome ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id p8sm2823298wrx.25.2021.12.08.06.36.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 06:36:05 -0800 (PST) Date: Wed, 8 Dec 2021 15:36:02 +0100 From: Thierry Reding To: Mark Rutland Cc: Will Deacon , Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs Message-ID: References: <20211207150746.444478-1-thierry.reding@gmail.com> <20211207150746.444478-2-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="r4zROj/eHft3UgPF" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.1.3 (987dde4c) (2021-09-10) Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org --r4zROj/eHft3UgPF Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote: > On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote: > > From: Thierry Reding > >=20 > > Add support for the NVIDIA Denver and Carmel PMUs using the generic > > PMUv3 event map for now. > >=20 > > Signed-off-by: Thierry Reding > > --- > > arch/arm64/kernel/perf_event.c | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > >=20 > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_ev= ent.c > > index b4044469527e..8c8cf369c450 100644 > > --- a/arch/arm64/kernel/perf_event.c > > +++ b/arch/arm64/kernel/perf_event.c > > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu = *cpu_pmu) > > armv8_vulcan_map_event); > > } > > =20 > > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu) > > +{ > > + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver", > > + armv8_pmuv3_map_event); > > +} > > + > > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu) > > +{ > > + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel", > > + armv8_pmuv3_map_event); > > +} > > + > > static const struct of_device_id armv8_pmu_of_device_ids[] =3D { > > {.compatible =3D "arm,armv8-pmuv3", .data =3D armv8_pmuv3_init}, > > {.compatible =3D "arm,cortex-a34-pmu", .data =3D armv8_a34_pmu_init}, > > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_dev= ice_ids[] =3D { > > {.compatible =3D "arm,neoverse-n1-pmu", .data =3D armv8_n1_pmu_init}, > > {.compatible =3D "cavium,thunder-pmu", .data =3D armv8_thunder_pmu_in= it}, > > {.compatible =3D "brcm,vulcan-pmu", .data =3D armv8_vulcan_pmu_init}, > > + {.compatible =3D "nvidia,denver-pmu", .data =3D armv8_denver_pmu_init= }, > > + {.compatible =3D "nvidia,carmel-pmu", .data =3D armv8_carmel_pmu_init= }, >=20 > Super trivial nit, but could we please organise this alphabetically (i.e.= with carmel first?) >=20 > With that: >=20 > Acked-by: Mark Rutland >=20 > I see now that we messed up the order of "cavium,thunder-pmu" and > "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to kee= p it > that way. I can fix the order of those two in a separate patch. I ordered this chronologically (Denver for Tegra186 and Carmel for Tegra194), which seemed a bit more natural, but I can reorder this alphabetically if you prefer. Would Will be the right person to pick this up or should I take it through the Tegra tree and then ARM SoC? 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