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Fri, 10 Dec 2021 05:42:34 -0800 (PST) Received: from orome ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id w22sm2872790wmi.27.2021.12.10.05.42.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Dec 2021 05:42:34 -0800 (PST) Date: Fri, 10 Dec 2021 14:42:31 +0100 From: Thierry Reding To: Dmitry Osipenko Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: Re: [PATCH 06/25] ARM: tegra: Fix compatible string for Tegra30+ timer Message-ID: References: <20211209173356.618460-1-thierry.reding@gmail.com> <20211209173356.618460-7-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="zMsqUpjgjZ8MIwwL" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.1.3 (987dde4c) (2021-09-10) Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org --zMsqUpjgjZ8MIwwL Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Dec 09, 2021 at 10:36:43PM +0300, Dmitry Osipenko wrote: > 09.12.2021 20:33, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > From: Thierry Reding > >=20 > > The TKE (time-keeping engine) found on Tegra30 and later is not > > backwards compatible with the version found on Tegra20, so update the > > compatible string list accordingly. > >=20 > > Signed-off-by: Thierry Reding > > --- > > arch/arm/boot/dts/tegra114.dtsi | 2 +- > > arch/arm/boot/dts/tegra124.dtsi | 2 +- > > arch/arm/boot/dts/tegra30.dtsi | 2 +- > > 3 files changed, 3 insertions(+), 3 deletions(-) > >=20 > > diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra1= 14.dtsi > > index 546272e396b4..328425dba023 100644 > > --- a/arch/arm/boot/dts/tegra114.dtsi > > +++ b/arch/arm/boot/dts/tegra114.dtsi > > @@ -164,7 +164,7 @@ lic: interrupt-controller@60004000 { > > }; > > =20 > > timer@60005000 { > > - compatible =3D "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvi= dia,tegra20-timer"; > > + compatible =3D "nvidia,tegra114-timer", "nvidia,tegra30-timer"; > > reg =3D <0x60005000 0x400>; > > interrupts =3D , > > , > > diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra1= 24.dtsi > > index 63a64171b422..f4ac0c327c2e 100644 > > --- a/arch/arm/boot/dts/tegra124.dtsi > > +++ b/arch/arm/boot/dts/tegra124.dtsi > > @@ -259,7 +259,7 @@ lic: interrupt-controller@60004000 { > > }; > > =20 > > timer@60005000 { > > - compatible =3D "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvi= dia,tegra20-timer"; > > + compatible =3D "nvidia,tegra124-timer", "nvidia,tegra30-timer"; > > reg =3D <0x0 0x60005000 0x0 0x400>; > > interrupts =3D , > > , > > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30= =2Edtsi > > index ae3df73c20a7..4c04b9c28484 100644 > > --- a/arch/arm/boot/dts/tegra30.dtsi > > +++ b/arch/arm/boot/dts/tegra30.dtsi > > @@ -342,7 +342,7 @@ lic: interrupt-controller@60004000 { > > }; > > =20 > > timer@60005000 { > > - compatible =3D "nvidia,tegra30-timer", "nvidia,tegra20-timer"; > > + compatible =3D "nvidia,tegra30-timer"; > > reg =3D <0x60005000 0x400>; > > interrupts =3D , > > , > >=20 >=20 > What exactly is incompatible? IIRC, T30+ is a superset of T20. This > patch should be wrong, also see [1]. As the comment in that location explains, Tegra114 and later have an architectural timer that is preferred over the legacy timer. So while this doesn't technically make Tegra114 incompatible (in terms of register programming, etc.) with Tegra20, in practice we don't want Tegra20 behaviour on Tegra114 and later. For Tegra30, you're indeed correct, there shouldn't be a difference, so I can add that back in. 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