From: Thierry Reding <thierry.reding@gmail.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: jonathanh@nvidia.com, mperttunen@nvidia.com,
sudeep.holla@arm.com, talho@nvidia.com, robh@kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
stefank@nvidia.com, krzysztof.kozlowski@linaro.org
Subject: Re: [PATCH v4 6/6] firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
Date: Wed, 7 Jun 2023 17:57:39 +0200 [thread overview]
Message-ID: <ZICo8wYqM8tmCEob@orome> (raw)
In-Reply-To: <ZGNS9w+i9Y9gpz6R@44189d9-lcedt>
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On Tue, May 16, 2023 at 12:55:03PM +0300, Peter De Schrijver wrote:
> On Tue, May 16, 2023 at 11:35:24AM +0200, Thierry Reding wrote:
> > On Thu, May 11, 2023 at 04:20:51PM +0300, Peter De Schrijver wrote:
> > > Implement support for DRAM MRQ GSCs.
> > >
> > > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > > ---
> > > drivers/firmware/tegra/bpmp-tegra186.c | 232 ++++++++++++++++++-------
> > > drivers/firmware/tegra/bpmp.c | 4 +-
> > > 2 files changed, 168 insertions(+), 68 deletions(-)
> > >
> > > diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmware/tegra/bpmp-tegra186.c
> > > index 2e26199041cd..74575c9f0014 100644
> > > --- a/drivers/firmware/tegra/bpmp-tegra186.c
> > > +++ b/drivers/firmware/tegra/bpmp-tegra186.c
> > > @@ -4,7 +4,9 @@
> > > */
> > >
> > > #include <linux/genalloc.h>
> > > +#include <linux/io.h>
> > > #include <linux/mailbox_client.h>
> > > +#include <linux/of_address.h>
> > > #include <linux/platform_device.h>
> > >
> > > #include <soc/tegra/bpmp.h>
> > > @@ -13,12 +15,21 @@
> > >
> > > #include "bpmp-private.h"
> > >
> > > +enum tegra_bpmp_mem_type { TEGRA_INVALID, TEGRA_SRAM, TEGRA_DRAM };
> >
> > Still not convinced about this one.
> >
> > > +
> > > struct tegra186_bpmp {
> > > struct tegra_bpmp *parent;
> > >
> > > struct {
> > > - struct gen_pool *pool;
> > > - void __iomem *virt;
> > > + union {
> > > + struct {
> > > + void __iomem *virt;
> > > + struct gen_pool *pool;
> > > + } sram;
> > > + struct {
> > > + void *virt;
> > > + } dram;
> > > + };
> >
> > The drawback of these unions is that they can lead to ambiguity, so you
> > need the tegra_bpmp_mem_type enum to differentiate between the two.
> >
>
> No, on the contrary, now it's clear you can either have void __iomem *
> and struct gen_pool * or void *virt but not both.
No, it's not clear. You can have one part of your driver write the
sram.virt field and another read dram.virt and they'll end up pointing
at the same memory location but with different meaning. That's why you
need to introduce the enumeration in order to specify which one of the
two you want to pick.
And that's exactly where you start introducing the potential for
inconsistency: now you need to be extra careful that the enumeration and
the unions are set correctly. You effectively have two sources of truth
and they don't necessarily match. You can also end up (at least
theoretically) with the invalid value, so you need an extra check for
that too.
You can avoid all of those inconsistencies if you reduce this to one
source of truth, namely the pointers that you're going to use.
Your variant would be slightly better if you omitted the invalid value
because then you could still have an internal inconsistency, but the
likelihood is much reduced.
> > If you change this to something like:
> >
> > struct {
> > struct gen_pool *pool;
> > void __iomem *sram;
> > void *dram;
> > dma_addr_t phys;
> > } tx, rx;
> >
> > you eliminate all ambiguity because you can either have pool and sram
> > set, or you can have dram set, and depending on which are set you know
> > which type of memory you're dealing with.
> >
>
> No. You just add ambiguity. It's not clear from looking at the data
> structure which fields are valid for which case.
That's easily fixed by adding comments explaining what you use them for.
But the code should make that pretty clear already.
Thierry
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next prev parent reply other threads:[~2023-06-07 15:58 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-11 13:20 [PATCH v4 0/6] firmware: tegra: Add MRQ support for Tegra264 Peter De Schrijver
2023-05-11 13:20 ` [PATCH v4 1/6] dt-bindings: mailbox: tegra: Document Tegra264 HSP Peter De Schrijver
2023-05-11 13:20 ` [PATCH v4 2/6] mailbox: tegra: add support for Tegra264 Peter De Schrijver
2023-05-11 13:20 ` [PATCH v4 3/6] soc/tegra: fuse: Add " Peter De Schrijver
2023-05-16 9:08 ` Thierry Reding
2023-05-11 13:20 ` [PATCH v4 4/6] dt-bindings: Add support for DRAM MRQ GSCs Peter De Schrijver
2023-05-11 19:21 ` Conor Dooley
2023-05-12 6:39 ` Krzysztof Kozlowski
2023-05-16 9:12 ` Thierry Reding
2023-05-16 11:53 ` Conor Dooley
2023-05-12 6:42 ` Krzysztof Kozlowski
2023-05-11 13:20 ` [PATCH v4 5/6] dt-bindings: Add support for tegra186-bpmp " Peter De Schrijver
2023-05-11 19:25 ` Conor Dooley
2023-05-12 6:45 ` Krzysztof Kozlowski
2023-05-16 9:14 ` Thierry Reding
2023-05-11 13:20 ` [PATCH v4 6/6] firmware: tegra: bpmp: Add support for " Peter De Schrijver
2023-05-16 9:35 ` Thierry Reding
2023-05-16 9:55 ` Peter De Schrijver
2023-06-07 15:57 ` Thierry Reding [this message]
2023-06-08 9:06 ` Peter De Schrijver
2023-06-08 16:05 ` Thierry Reding
2023-06-08 11:22 ` Peter De Schrijver
2023-06-08 16:12 ` Thierry Reding
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