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From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: <jonathanh@nvidia.com>, <mperttunen@nvidia.com>,
	<sudeep.holla@arm.com>, <talho@nvidia.com>, <robh@kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<stefank@nvidia.com>, <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v4 6/6] firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
Date: Thu, 8 Jun 2023 14:22:23 +0300	[thread overview]
Message-ID: <ZIG571modfPCnl2p@44189d9-lcedt> (raw)
In-Reply-To: <ZICo8wYqM8tmCEob@orome>

On Wed, Jun 07, 2023 at 05:57:39PM +0200, Thierry Reding wrote:
> > No, on the contrary, now it's clear you can either have void __iomem *
> > and struct gen_pool * or void *virt but not both.
> 
> No, it's not clear. You can have one part of your driver write the
> sram.virt field and another read dram.virt and they'll end up pointing
> at the same memory location but with different meaning. That's why you
> need to introduce the enumeration in order to specify which one of the
> two you want to pick.
> 
> And that's exactly where you start introducing the potential for
> inconsistency: now you need to be extra careful that the enumeration and
> the unions are set correctly. You effectively have two sources of truth
> and they don't necessarily match. You can also end up (at least
> theoretically) with the invalid value, so you need an extra check for
> that too.
> 
> You can avoid all of those inconsistencies if you reduce this to one
> source of truth, namely the pointers that you're going to use.
> 

There are 4 possible states for these pointers:
both NULL
both non-NULL
sram pointer NULL, dram pointer non-NULL
dram pointer NULL, sram pointer non-NULL

So how is this one source of truth?

Peter.

  parent reply	other threads:[~2023-06-08 11:22 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-11 13:20 [PATCH v4 0/6] firmware: tegra: Add MRQ support for Tegra264 Peter De Schrijver
2023-05-11 13:20 ` [PATCH v4 1/6] dt-bindings: mailbox: tegra: Document Tegra264 HSP Peter De Schrijver
2023-05-11 13:20 ` [PATCH v4 2/6] mailbox: tegra: add support for Tegra264 Peter De Schrijver
2023-05-11 13:20 ` [PATCH v4 3/6] soc/tegra: fuse: Add " Peter De Schrijver
2023-05-16  9:08   ` Thierry Reding
2023-05-11 13:20 ` [PATCH v4 4/6] dt-bindings: Add support for DRAM MRQ GSCs Peter De Schrijver
2023-05-11 19:21   ` Conor Dooley
2023-05-12  6:39     ` Krzysztof Kozlowski
2023-05-16  9:12     ` Thierry Reding
2023-05-16 11:53       ` Conor Dooley
2023-05-12  6:42   ` Krzysztof Kozlowski
2023-05-11 13:20 ` [PATCH v4 5/6] dt-bindings: Add support for tegra186-bpmp " Peter De Schrijver
2023-05-11 19:25   ` Conor Dooley
2023-05-12  6:45   ` Krzysztof Kozlowski
2023-05-16  9:14     ` Thierry Reding
2023-05-11 13:20 ` [PATCH v4 6/6] firmware: tegra: bpmp: Add support for " Peter De Schrijver
2023-05-16  9:35   ` Thierry Reding
2023-05-16  9:55     ` Peter De Schrijver
2023-06-07 15:57       ` Thierry Reding
2023-06-08  9:06         ` Peter De Schrijver
2023-06-08 16:05           ` Thierry Reding
2023-06-08 11:22         ` Peter De Schrijver [this message]
2023-06-08 16:12           ` Thierry Reding

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