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Mon, 8 Jul 2024 10:59:56 -0700 Date: Mon, 8 Jul 2024 10:59:54 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , , , Subject: Re: [PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV Message-ID: References: <20240702174307.GB4740@willie-the-truck> <20240702184942.GD5167@willie-the-truck> <20240705152721.GA9485@willie-the-truck> <20240708112928.GB11567@willie-the-truck> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240708112928.GB11567@willie-the-truck> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AD:EE_|SA3PR12MB8021:EE_ X-MS-Office365-Filtering-Correlation-Id: e17d9c03-375e-4615-e652-08dc9f77d2cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 18:00:16.4995 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e17d9c03-375e-4615-e652-08dc9f77d2cd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8021 On Mon, Jul 08, 2024 at 12:29:28PM +0100, Will Deacon wrote: > > With that, we cannot avoid an unconditional hard-coding tegra > > function call even if we switch to an impl design: > > > > +static int acpi_smmu_impl_init(u32 model, struct arm_smmu_device *smmu) > > +{ > > + /* > > + * unconditional go through ACPI table to detect if there is a tegra241 > > + * implementation that extends SMMU with a CMDQV. The probe() will fill > > + * the smmu->impl pointer upon success. Otherwise, fall back to regular > > + * SMMU CMDQ. > > + */ > > + tegra241_impl_acpi_probe(smmu); > > In-line the minimal DSDT parsing to figure out if we're on a Tegra part. > If it's that bad, put it in a static inline in arm-smmu-v3.h. OK. How about the following? /* arm-smmu-v3.h */ static inline void arm_smmu_impl_acpi_dsdt_probe(struct arm_smmu_device *smmu, struct acpi_iort_node *node) { tegra241_cmdqv_acpi_dsdt_probe(smmu, node); } /* arm-smmu-v3.c */ static int arm_smmu_impl_acpi_probe(struct arm_smmu_device *smmu, struct acpi_iort_node *node) { /* * DSDT might holds some SMMU extension, so we have no option but to go * through ACPI tables unconditionally. This probe function should fill * the smmu->impl pointer upon success. Otherwise, just carry on with a * standard SMMU. */ arm_smmu_impl_acpi_dsdt_probe(smmu, node); return 0; } > > + return 0; > > +} > > > > As for arm_smmu_cmdq_needs_busy_polling, it doesn't really look > > very optimal to me. > > "optimal" in what sense? In that you don't like how it smells, or that > it's measurably bad? It would potentially not work if someday an implementation has two secondary queues? I got your point of making it an option just like the existing ARM_SMMU_OPT_MSIPOLL though.. Thanks Nicolin