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Fri, 16 Aug 2024 10:34:20 -0700 Date: Fri, 16 Aug 2024 10:34:18 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , , , Subject: Re: [PATCH v11 9/9] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF Message-ID: References: <153fb887cf4bf6318c6f313a4be9b40a25a24e7d.1722993435.git.nicolinc@nvidia.com> <20240816132103.GA24411@willie-the-truck> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240816132103.GA24411@willie-the-truck> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4B:EE_|CY8PR12MB7684:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fbfdaf9-9a29-4dc2-a455-08dcbe19b541 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WzhoJ961Wgnyem3g2EjVOZxv6uvbaN9mi+L8WGhAe4oUMtqpaCrBDGDor85y?= =?us-ascii?Q?i+TxvmHuq6yQeLQG++/tudF0aA7ECZ+LPh/Yg3PHkj0GA1eViOIXiJF/989n?= =?us-ascii?Q?K1q8xDOBYKBT3aa1QoiZe9WevugS6wYh//HHRbydio5wJszAq3yt17g3nd+e?= =?us-ascii?Q?6EqE+4BPZgt0xXKbagvKIQGtpPTg6eTTsPwYPILmsOCNNgIBO1/l18PPp/r8?= =?us-ascii?Q?5n8bx4CwjKIdoW7AP/tsCVO83hJwTv/YDi39LQyh4sxSeDw4/XKFeE0FtcSK?= =?us-ascii?Q?CD8bsUdtFAi2S1gYQgzGoblo0qVOlyVkgtX0x4vbHx+5W7bUdRphSv5kLe0r?= =?us-ascii?Q?iZrrnSTT/u4ITFCznu5oQBJwqHP3yWtajnQ/y1JYIkIugbP1yfBpuvvtH+rM?= =?us-ascii?Q?rNiE86B1wO/VhV6DJdKnVNhwf6jaOxUCmzQpevnrCsqfez8rFbpUCGzWG4mA?= =?us-ascii?Q?l2Gc7IU84avzcqVZni2rn9JEaQrjLwrRO/tD2NuGjoT3DHkciLYSTfhaQ17W?= =?us-ascii?Q?qQPN5rW0Uupyd+i671YNsz5qf/92nZGy0xxQLjOL0HaFdVH4AaqGdfvq4ZzP?= =?us-ascii?Q?skofFlzi7fdR5H+mQX6Z6qpAWfEps/KgDo7ciKzSkIwztQna3ARXG0W7khtQ?= =?us-ascii?Q?+tM32xiBQEQm89HYhKMOLLL03YYF0bUEe5mc9XwTQIO9Dj48Urdy4Ldx76lw?= =?us-ascii?Q?/zU4ov1GZzVCS63i6BPvrJQWIAXYzFNRlj75gsrLrw5YsTTDOg6KrE7IzpQw?= =?us-ascii?Q?PeG/LWqKsZChSOosYJpue3EzGM1ciz50SVzrgVAlItn1CvH4etLsAqZsLNye?= =?us-ascii?Q?Fe3EmPRwsr0IXNhC5acC2b4OMV9hEbOkcnQWg/OKX37h6v/gkhjHH3qp7LPa?= =?us-ascii?Q?zVLRlxvoNF1ml/47NMhBQFXqKYelV2yjNWM9/e97CdMg7XQchk46dALbDoI0?= =?us-ascii?Q?El3wTqaD54E3hXmk9RUbg/i7Yo3Yzbcw17I008fvRkqFIs7tcQzN4WGkeJEn?= =?us-ascii?Q?tdz6DLuvqkSRqR2lzlurXmQBZSZN7TYUW+fRbpTfdFLSb2vdqV6XeJn+tAgi?= =?us-ascii?Q?s51mbOPlKCxxYiN2Uzz94o2gc9MfxWK5/eB+iDH6SX+v7EWYp+Lbs7uFPEsn?= =?us-ascii?Q?ApewXZto5Oi20W5HKr9UvNnVcZwhTDT+qlahT6u30mMmr/ISn0sWB39jbX6U?= =?us-ascii?Q?olpm2hSaOXO1r1AupV6VIiriYypqgUQfqeqrIytdGvVuPJe5tWqVbAkbEfba?= =?us-ascii?Q?VcnAbJiJX1iOvqCLneknZ9WrTF9WHV7/9dEGnG6cOAX00DtofSI1U3RJsy0I?= =?us-ascii?Q?mqVpYj1+WwXcDxNVslKAxWOLyBwKnOb9y8lTHD5sgO8u0el2idPbCjX8m12e?= =?us-ascii?Q?1QCPJvvpx8cFmL+kJVkOEDkW8K2URPNEqrNvmFOs1Fi5sj+1bwliWCQSoyoR?= =?us-ascii?Q?Yu2AxRrVAnqYvBKwvqvVxSxktmusvbOL?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 17:34:40.2330 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fbfdaf9-9a29-4dc2-a455-08dcbe19b541 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7684 On Fri, Aug 16, 2024 at 02:21:03PM +0100, Will Deacon wrote: > > static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, > > - struct arm_smmu_cmdq_batch *cmds) > > + struct arm_smmu_cmdq_batch *cmds, > > + u8 opcode) > > { > > + WARN_ON_ONCE(!opcode); > > This seems like a fairly arbitrary warning. Remove it? OK. > > + > > cmds->num = 0; > > - cmds->cmdq = arm_smmu_get_cmdq(smmu); > > + cmds->cmdq = arm_smmu_get_cmdq(smmu, opcode); > > If we stashed the opcode here, we could actually just enforce that all > commands in the batch are the same type in arm_smmu_cmdq_batch_add(). > > Would that work better for you or not? A guested-owned queue is okay to mix different command types: CMDQ_OP_TLBI_NH_ASID CMDQ_OP_TLBI_NH_VA CMDQ_OP_ATC_INV So, limiting a batch to one single opcode isn't ideal. Instead, if we really have to apply an enforcement to every batch_add(), I think the cmdq structure would need a scan function pointer: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d0d7c75c030a..1a83ad5ebadc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -918,2 +918,10 @@ static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, +static bool arm_smmu_cmdq_supports_cmd(struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmdq_ent *ent) +{ + if (!cmdq->supports_cmd) + return true; + return cmdq->supports_cmd(ent); +} + static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, @@ -924,4 +932,5 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, - if (cmds->num == CMDQ_BATCH_ENTRIES - 1 && - (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) { + if ((cmds->num == CMDQ_BATCH_ENTRIES - 1 && + (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) || + !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd)) { arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index e131d8170b90..c4872af6232c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -616,2 +616,3 @@ struct arm_smmu_cmdq { atomic_t lock; + bool (*supports_cmd)(struct arm_smmu_cmdq_ent *ent); }; That being said, the whole thing doesn't seem to have a lot value at this moment, since the SMMU driver doesn't mix commands? Thanks Nicolin