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[34.143.210.2]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db5104cd5sm127537775ad.199.2025.04.30.15.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 15:04:04 -0700 (PDT) Date: Wed, 30 Apr 2025 22:03:53 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: jgg@nvidia.com, kevin.tian@intel.com, corbet@lwn.net, will@kernel.org, bagasdotme@gmail.com, robin.murphy@arm.com, joro@8bytes.org, thierry.reding@gmail.com, vdumpa@nvidia.com, jonathanh@nvidia.com, shuah@kernel.org, jsnitsel@redhat.com, nathan@kernel.org, peterz@infradead.org, yi.l.liu@intel.com, mshavit@google.com, zhangzekun11@huawei.com, iommu@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kselftest@vger.kernel.org, patches@lists.linux.dev, mochs@nvidia.com, alok.a.tiwari@oracle.com, vasant.hegde@amd.com Subject: Re: [PATCH v2 22/22] iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support Message-ID: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Apr 25, 2025 at 10:58:17PM -0700, Nicolin Chen wrote: > Add a new vEVENTQ type for VINTFs that are assigned to the user space. > Simply report the two 64-bit LVCMDQ_ERR_MAPs register values. > > Signed-off-by: Nicolin Chen Reviewed-by: Pranjal Shrivastava Thanks, Praan > --- > include/uapi/linux/iommufd.h | 15 +++++++++++++ > .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 22 +++++++++++++++++++ > 2 files changed, 37 insertions(+) > > diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h > index d69e7c1d39ea..d814b0f61fad 100644 > --- a/include/uapi/linux/iommufd.h > +++ b/include/uapi/linux/iommufd.h > @@ -1113,10 +1113,12 @@ struct iommufd_vevent_header { > * enum iommu_veventq_type - Virtual Event Queue Type > * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use > * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue > + * @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ > */ > enum iommu_veventq_type { > IOMMU_VEVENTQ_TYPE_DEFAULT = 0, > IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, > + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2, > }; > > /** > @@ -1140,6 +1142,19 @@ struct iommu_vevent_arm_smmuv3 { > __aligned_le64 evt[4]; > }; > > +/** > + * struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ > + * (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV) > + * @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian. > + * (Refer to register LVCMDQ_ERR_MAPs per VINTF ) > + * > + * The 128-bit register value from HW exclusively reflect the error bits for a > + * Virtual Interface represented by a vIOMMU object. Read and report directly. > + */ > +struct iommu_vevent_tegra241_cmdqv { > + __aligned_le64 lvcmdq_err_map[2]; > +}; > + > /** > * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) > * @size: sizeof(struct iommu_veventq_alloc) > diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c > index 88e2b6506b3a..d8830b526601 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c > +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c > @@ -292,6 +292,20 @@ static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval) > > /* ISR Functions */ > > +static void tegra241_vintf_user_handle_error(struct tegra241_vintf *vintf) > +{ > + struct iommufd_viommu *viommu = &vintf->vsmmu.core; > + struct iommu_vevent_tegra241_cmdqv vevent_data; > + int i; > + > + for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) > + vevent_data.lvcmdq_err_map[i] = > + readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); > + > + iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, > + &vevent_data, sizeof(vevent_data)); > +} > + > static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) > { > int i; > @@ -337,6 +351,14 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) > vintf_map &= ~BIT_ULL(0); > } > > + /* Handle other user VINTFs and their LVCMDQs */ > + while (vintf_map) { > + unsigned long idx = __ffs64(vintf_map); > + > + tegra241_vintf_user_handle_error(cmdqv->vintfs[idx]); > + vintf_map &= ~BIT_ULL(idx); > + } > + > return IRQ_HANDLED; > } > > -- > 2.43.0 >