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[34.126.98.232]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23acb2e39d4sm158508935ad.18.2025.07.03.07.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jul 2025 07:46:12 -0700 (PDT) Date: Thu, 3 Jul 2025 14:46:03 +0000 From: Pranjal Shrivastava To: Jason Gunthorpe Cc: Nicolin Chen , kevin.tian@intel.com, corbet@lwn.net, will@kernel.org, bagasdotme@gmail.com, robin.murphy@arm.com, joro@8bytes.org, thierry.reding@gmail.com, vdumpa@nvidia.com, jonathanh@nvidia.com, shuah@kernel.org, jsnitsel@redhat.com, nathan@kernel.org, peterz@infradead.org, yi.l.liu@intel.com, mshavit@google.com, zhangzekun11@huawei.com, iommu@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kselftest@vger.kernel.org, patches@lists.linux.dev, mochs@nvidia.com, alok.a.tiwari@oracle.com, vasant.hegde@amd.com, dwmw2@infradead.org, baolu.lu@linux.intel.com Subject: Re: [PATCH v7 27/28] iommu/tegra241-cmdqv: Add user-space use support Message-ID: References: <20250702180541.GD1139770@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250702180541.GD1139770@nvidia.com> On Wed, Jul 02, 2025 at 03:05:41PM -0300, Jason Gunthorpe wrote: > On Wed, Jul 02, 2025 at 01:38:33AM +0000, Pranjal Shrivastava wrote: > > On Tue, Jul 01, 2025 at 05:46:06PM -0700, Nicolin Chen wrote: > > > On Wed, Jul 02, 2025 at 12:14:28AM +0000, Pranjal Shrivastava wrote: > > > > Thus, coming back to the two initial points: > > > > > > > > 1) Issuing "non-invalidation" commands through .cache_invalidate could > > > > be confusing, I'm not asking to change the op name here, but if we > > > > plan to label it, let's label them as "Trapped commands" OR > > > > "non-accelerated" commands as you suggested. > > > > > > VCMDQ only accelerates limited invalidation commands, not all of > > > them: STE cache invalidation and CD cache invalidation commands > > > still go down to that op. > > > > > > > Right, I'm just saying the "other" non-accelerated commands that are > > NOT invalidations also go down that op. So, if we add a comment, let's > > not call them "non-invalidation" commands. > > There are no non-invalidation commands: > > static int arm_vsmmu_convert_user_cmd(struct arm_vsmmu *vsmmu, > struct arm_vsmmu_invalidation_cmd *cmd) > { > switch (cmd->cmd[0] & CMDQ_0_OP) { > case CMDQ_OP_TLBI_NSNH_ALL: > case CMDQ_OP_TLBI_NH_VA: > case CMDQ_OP_TLBI_NH_VAA: > case CMDQ_OP_TLBI_NH_ALL: > case CMDQ_OP_TLBI_NH_ASID: > case CMDQ_OP_ATC_INV: > case CMDQ_OP_CFGI_CD: > case CMDQ_OP_CFGI_CD_ALL: > > Those are only invalidations. > > CD invalidation can't go through the vCMDQ path. > Right.. I was however hoping we'd also trap commands like CMD_PRI_RESP and CMD_RESUME...I'm not sure if they should be accelerated via CMDQV.. I guess I'll need to look and understand a little more if they are.. > > > > 2) The "FIXME" confusion: The comment in arm_vsmmu_cache_invalidate > > > > mentions we'd like to "fix" the issuing of commands through the main > > > > cmdq and instead like to group by "type", if that "type" is the queue > > > > type (which I assume it is because IOMMU_TYPE has to be arm-smmu-v3), > > > > > > I recall that FIXME is noted by Jason at that time. And it should > > > be interpreted as "group by opcode", IIUIC. > > > > I see.. I misunderstood that.. > > Yes, we could use the vCMDQ in the SMMU driver for invalidations which > would give some minor locking advantage. But it is not really > important to anyone. > Alright, I see. Makes sense. Thanks for the clarification. > > > The thing is that for a host kernel that enabled in-kernel VCMDQs, > > > those trapped user commands can be just issued to the smmu->cmdq > > > or a vcmdq (picked via the get_secondary_cmdq impl_op). > > > > Ohh.. so maybe some sort of a load balancing thing? > > The goal of the SMMU driver when it detects CMDQV support is to route > all supported invalidations to CMDQV queues and then balance those > queues across CPUs to reduce lock contention. > I see.. that makes sense.. so it's a relatively small gain (but a nice one). Thanks for clarifying! > Jason Praan