* [PATCH v2 1/5] PCI: endpoint: Add reserved region type for MSI-X Table and PBA
2026-03-03 7:19 [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manikanta Maddireddy
@ 2026-03-03 7:20 ` Manikanta Maddireddy
2026-03-03 13:46 ` Niklas Cassel
2026-03-03 7:20 ` [PATCH v2 2/5] PCI: endpoint: Allow only_64bit on BAR_RESERVED Manikanta Maddireddy
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Manikanta Maddireddy @ 2026-03-03 7:20 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, cassel, 18255117159
Cc: linux-pci, linux-tegra, linux-kernel, Manikanta Maddireddy
Add PCI_EPC_BAR_RSVD_MSIX_TBL_RAM and PCI_EPC_BAR_RSVD_MSIX_PBA_RAM to
enum pci_epc_bar_rsvd_region_type so that Endpoint controllers can
describe hardware-owned MSI-X Table and PBA (Pending Bit Array) regions
behind a BAR_RESERVED BAR.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
v2: Split MSI-X pci_epc_bar_rsvd_region_type for both MSI-X table and PBA
include/linux/pci-epc.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index c181c6d107b7..fb3f34829d2b 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -214,6 +214,8 @@ enum pci_epc_bar_type {
/**
* enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
* @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
+ * @PCI_EPC_BAR_RSVD_MSIX_TBL_RAM: MSI-X table structure
+ * @PCI_EPC_BAR_RSVD_MSIX_PBA_RAM: MSI-X PBA structures
*
* BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be
* reprogrammed by EPF drivers. Some of them still expose fixed subregions that
@@ -221,6 +223,8 @@ enum pci_epc_bar_type {
*/
enum pci_epc_bar_rsvd_region_type {
PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0,
+ PCI_EPC_BAR_RSVD_MSIX_TBL_RAM,
+ PCI_EPC_BAR_RSVD_MSIX_PBA_RAM,
};
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/5] PCI: endpoint: Add reserved region type for MSI-X Table and PBA
2026-03-03 7:20 ` [PATCH v2 1/5] PCI: endpoint: Add reserved region type for MSI-X Table and PBA Manikanta Maddireddy
@ 2026-03-03 13:46 ` Niklas Cassel
0 siblings, 0 replies; 12+ messages in thread
From: Niklas Cassel @ 2026-03-03 13:46 UTC (permalink / raw)
To: Manikanta Maddireddy
Cc: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, 18255117159, linux-pci,
linux-tegra, linux-kernel
On Tue, Mar 03, 2026 at 12:50:00PM +0530, Manikanta Maddireddy wrote:
> Add PCI_EPC_BAR_RSVD_MSIX_TBL_RAM and PCI_EPC_BAR_RSVD_MSIX_PBA_RAM to
> enum pci_epc_bar_rsvd_region_type so that Endpoint controllers can
> describe hardware-owned MSI-X Table and PBA (Pending Bit Array) regions
> behind a BAR_RESERVED BAR.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> v2: Split MSI-X pci_epc_bar_rsvd_region_type for both MSI-X table and PBA
>
> include/linux/pci-epc.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index c181c6d107b7..fb3f34829d2b 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -214,6 +214,8 @@ enum pci_epc_bar_type {
> /**
> * enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
> * @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
> + * @PCI_EPC_BAR_RSVD_MSIX_TBL_RAM: MSI-X table structure
> + * @PCI_EPC_BAR_RSVD_MSIX_PBA_RAM: MSI-X PBA structures
s/MSI-X PBA structures/MSI-X PBA structure/
PCIe 6.0 7.7.2 MSI-X Capability and Table Structure
references this as:
MSI-X Table structure and an MSI-X PBA structure
With that:
Reviewed-by: Niklas Cassel <cassel@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/5] PCI: endpoint: Allow only_64bit on BAR_RESERVED
2026-03-03 7:19 [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manikanta Maddireddy
2026-03-03 7:20 ` [PATCH v2 1/5] PCI: endpoint: Add reserved region type for MSI-X Table and PBA Manikanta Maddireddy
@ 2026-03-03 7:20 ` Manikanta Maddireddy
2026-03-03 13:46 ` Niklas Cassel
2026-03-03 7:20 ` [PATCH v2 3/5] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit Manikanta Maddireddy
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Manikanta Maddireddy @ 2026-03-03 7:20 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, cassel, 18255117159
Cc: linux-pci, linux-tegra, linux-kernel, Manikanta Maddireddy
Remove the documentation that forbids setting only_64bit on a BAR of
type BAR_RESERVED.
When a reserved BAR is 64-bit by default, setting only_64bit is the
most accurate description. If we later add support to disable a
reserved BAR (e.g. disable_bar() for BARs that were never set via
set_bar()), the implementation will need to clear the adjacent BAR
(upper 32 bits) as well; having only_64bit set documents that
requirement.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
v2: New patch in v2
include/linux/pci-epc.h | 5 -----
1 file changed, 5 deletions(-)
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index fb3f34829d2b..8ed000dbeca4 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -247,11 +247,6 @@ struct pci_epc_bar_rsvd_region {
* should be configured as 32-bit or 64-bit, the EPF driver must
* configure this BAR as 64-bit. Additionally, the BAR succeeding
* this BAR must be set to type BAR_64BIT_UPPER.
- *
- * only_64bit should not be set on a BAR of type BAR_RESERVED.
- * (If BARx is a 64-bit BAR that an EPF driver is not allowed to
- * reprogram, then both BARx and BARx+1 must be set to type
- * BAR_RESERVED.)
* @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
* @rsvd_regions: fixed subregions behind BAR_RESERVED
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/5] PCI: endpoint: Allow only_64bit on BAR_RESERVED
2026-03-03 7:20 ` [PATCH v2 2/5] PCI: endpoint: Allow only_64bit on BAR_RESERVED Manikanta Maddireddy
@ 2026-03-03 13:46 ` Niklas Cassel
0 siblings, 0 replies; 12+ messages in thread
From: Niklas Cassel @ 2026-03-03 13:46 UTC (permalink / raw)
To: Manikanta Maddireddy
Cc: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, 18255117159, linux-pci,
linux-tegra, linux-kernel
On Tue, Mar 03, 2026 at 12:50:01PM +0530, Manikanta Maddireddy wrote:
> Remove the documentation that forbids setting only_64bit on a BAR of
> type BAR_RESERVED.
>
> When a reserved BAR is 64-bit by default, setting only_64bit is the
> most accurate description. If we later add support to disable a
> reserved BAR (e.g. disable_bar() for BARs that were never set via
> set_bar()), the implementation will need to clear the adjacent BAR
> (upper 32 bits) as well; having only_64bit set documents that
> requirement.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
Reviewed-by: Niklas Cassel <cassel@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/5] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit
2026-03-03 7:19 [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manikanta Maddireddy
2026-03-03 7:20 ` [PATCH v2 1/5] PCI: endpoint: Add reserved region type for MSI-X Table and PBA Manikanta Maddireddy
2026-03-03 7:20 ` [PATCH v2 2/5] PCI: endpoint: Allow only_64bit on BAR_RESERVED Manikanta Maddireddy
@ 2026-03-03 7:20 ` Manikanta Maddireddy
2026-03-03 13:48 ` Niklas Cassel
2026-03-03 7:20 ` [PATCH v2 4/5] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED Manikanta Maddireddy
` (2 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Manikanta Maddireddy @ 2026-03-03 7:20 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, cassel, 18255117159
Cc: linux-pci, linux-tegra, linux-kernel, Manikanta Maddireddy
The Tegra194/234 Endpoint does not support the Resizable BAR capability,
but BAR0 can be programmed to different sizes via the DBI2 BAR registers
in dw_pcie_ep_set_bar_programmable(). The BAR0 size is set once during
initialization.
Remove the fixed 1MB limit from pci_epc_features so Endpoint function
drivers can configure the BAR0 size they need.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
v2: drop .type init for BAR_0
drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index ddb1570e257d..2f35f18ba766 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2001,11 +2001,11 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+/* Tegra EP: BAR0 = 64-bit programmable BAR */
static const struct pci_epc_features tegra_pcie_epc_features = {
.linkup_notifier = true,
.msi_capable = true,
- .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
- .only_64bit = true, },
+ .bar[BAR_0] = { .only_64bit = true, },
.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
.bar[BAR_2] = { .type = BAR_DISABLED, },
.bar[BAR_3] = { .type = BAR_DISABLED, },
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/5] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit
2026-03-03 7:20 ` [PATCH v2 3/5] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit Manikanta Maddireddy
@ 2026-03-03 13:48 ` Niklas Cassel
0 siblings, 0 replies; 12+ messages in thread
From: Niklas Cassel @ 2026-03-03 13:48 UTC (permalink / raw)
To: Manikanta Maddireddy
Cc: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, 18255117159, linux-pci,
linux-tegra, linux-kernel
On Tue, Mar 03, 2026 at 12:50:02PM +0530, Manikanta Maddireddy wrote:
> The Tegra194/234 Endpoint does not support the Resizable BAR capability,
> but BAR0 can be programmed to different sizes via the DBI2 BAR registers
> in dw_pcie_ep_set_bar_programmable(). The BAR0 size is set once during
> initialization.
>
> Remove the fixed 1MB limit from pci_epc_features so Endpoint function
> drivers can configure the BAR0 size they need.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
Reviewed-by: Niklas Cassel <cassel@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/5] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED
2026-03-03 7:19 [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manikanta Maddireddy
` (2 preceding siblings ...)
2026-03-03 7:20 ` [PATCH v2 3/5] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit Manikanta Maddireddy
@ 2026-03-03 7:20 ` Manikanta Maddireddy
2026-03-03 13:51 ` Niklas Cassel
2026-03-03 7:20 ` [PATCH v2 5/5] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries Manikanta Maddireddy
2026-03-21 12:32 ` [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manivannan Sadhasivam
5 siblings, 1 reply; 12+ messages in thread
From: Manikanta Maddireddy @ 2026-03-03 7:20 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, cassel, 18255117159
Cc: linux-pci, linux-tegra, linux-kernel, Manikanta Maddireddy
Tegra Endpoint exposes three 64-bit BARs at indices 0, 2, and 4:
- BAR0+BAR1: EPF test/data (programmable 64-bit BAR)
- BAR2+BAR3: MSI-X table (hardware-backed)
- BAR4+BAR5: DMA registers (hardware-backed)
Update tegra_pcie_epc_features so that BAR2 is BAR_RESERVED with
PCI_EPC_BAR_RSVD_MSIX_TBL_RAM (64 KB) & PCI_EPC_BAR_RSVD_MSIX_PBA_RAM (64 KB),
BAR3 is BAR_64BIT_UPPER, BAR4 is BAR_RESERVED with
PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO (4KB), and BAR5 is BAR_64BIT_UPPER.
This keeps CONSECUTIVE_BAR_TEST working while allowing the host to use
64-bit BAR2 (MSI-X) and BAR4 (DMA).
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
v2: Split MSI-X table and PBA reserved region
drivers/pci/controller/dwc/pcie-tegra194.c | 44 +++++++++++++++++++---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 2f35f18ba766..be60f80ccf6b 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2001,16 +2001,50 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
-/* Tegra EP: BAR0 = 64-bit programmable BAR */
+static const struct pci_epc_bar_rsvd_region tegra194_bar2_rsvd[] = {
+ {
+ /* MSI-X table structure */
+ .type = PCI_EPC_BAR_RSVD_MSIX_TBL_RAM,
+ .offset = 0x0,
+ .size = SZ_64K,
+ },
+ {
+ /* MSI-X PBA structure */
+ .type = PCI_EPC_BAR_RSVD_MSIX_PBA_RAM,
+ .offset = 0x10000,
+ .size = SZ_64K,
+ },
+};
+
+static const struct pci_epc_bar_rsvd_region tegra194_bar4_rsvd[] = {
+ {
+ /* DMA_CAP (BAR4: DMA Port Logic Structure) */
+ .type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
+ .offset = 0x0,
+ .size = SZ_4K,
+ },
+};
+
+/* Tegra EP: BAR0 = 64-bit programmable BAR, BAR2 = 64-bit MSI-X table, BAR4 = 64-bit DMA regs. */
static const struct pci_epc_features tegra_pcie_epc_features = {
.linkup_notifier = true,
.msi_capable = true,
.bar[BAR_0] = { .only_64bit = true, },
.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
- .bar[BAR_2] = { .type = BAR_DISABLED, },
- .bar[BAR_3] = { .type = BAR_DISABLED, },
- .bar[BAR_4] = { .type = BAR_DISABLED, },
- .bar[BAR_5] = { .type = BAR_DISABLED, },
+ .bar[BAR_2] = {
+ .type = BAR_RESERVED,
+ .only_64bit = true,
+ .nr_rsvd_regions = ARRAY_SIZE(tegra194_bar2_rsvd),
+ .rsvd_regions = tegra194_bar2_rsvd,
+ },
+ .bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
+ .bar[BAR_4] = {
+ .type = BAR_RESERVED,
+ .only_64bit = true,
+ .nr_rsvd_regions = ARRAY_SIZE(tegra194_bar4_rsvd),
+ .rsvd_regions = tegra194_bar4_rsvd,
+ },
+ .bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
.align = SZ_64K,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 4/5] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED
2026-03-03 7:20 ` [PATCH v2 4/5] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED Manikanta Maddireddy
@ 2026-03-03 13:51 ` Niklas Cassel
0 siblings, 0 replies; 12+ messages in thread
From: Niklas Cassel @ 2026-03-03 13:51 UTC (permalink / raw)
To: Manikanta Maddireddy
Cc: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, 18255117159, linux-pci,
linux-tegra, linux-kernel
On Tue, Mar 03, 2026 at 12:50:03PM +0530, Manikanta Maddireddy wrote:
> Tegra Endpoint exposes three 64-bit BARs at indices 0, 2, and 4:
> - BAR0+BAR1: EPF test/data (programmable 64-bit BAR)
> - BAR2+BAR3: MSI-X table (hardware-backed)
> - BAR4+BAR5: DMA registers (hardware-backed)
>
> Update tegra_pcie_epc_features so that BAR2 is BAR_RESERVED with
> PCI_EPC_BAR_RSVD_MSIX_TBL_RAM (64 KB) & PCI_EPC_BAR_RSVD_MSIX_PBA_RAM (64 KB),
> BAR3 is BAR_64BIT_UPPER, BAR4 is BAR_RESERVED with
> PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO (4KB), and BAR5 is BAR_64BIT_UPPER.
> This keeps CONSECUTIVE_BAR_TEST working while allowing the host to use
> 64-bit BAR2 (MSI-X) and BAR4 (DMA).
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
Reviewed-by: Niklas Cassel <cassel@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 5/5] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries
2026-03-03 7:19 [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manikanta Maddireddy
` (3 preceding siblings ...)
2026-03-03 7:20 ` [PATCH v2 4/5] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED Manikanta Maddireddy
@ 2026-03-03 7:20 ` Manikanta Maddireddy
2026-03-03 13:49 ` Niklas Cassel
2026-03-21 12:32 ` [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manivannan Sadhasivam
5 siblings, 1 reply; 12+ messages in thread
From: Manikanta Maddireddy @ 2026-03-03 7:20 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, cassel, 18255117159
Cc: linux-pci, linux-tegra, linux-kernel, Manikanta Maddireddy
Add PCI device IDs for Tegra194 (0x1ad4) and Tegra234(0x229b) Endpoint
controllers, so that pci_endpoint_test can bind and run on these
controllers.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
v2: Remove pci_endpoint_test_data
drivers/misc/pci_endpoint_test.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index f166b6fea698..fe370c94b191 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -106,6 +106,9 @@
#define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588
+#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP 0x1ad4
+#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP 0x229b
+
static DEFINE_IDA(pci_endpoint_test_ida);
#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
@@ -1246,6 +1249,10 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588),
.driver_data = (kernel_ulong_t)&rk3588_data,
},
+ { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA194_EP),
+ },
+ { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA234_EP),
+ },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 5/5] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries
2026-03-03 7:20 ` [PATCH v2 5/5] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries Manikanta Maddireddy
@ 2026-03-03 13:49 ` Niklas Cassel
0 siblings, 0 replies; 12+ messages in thread
From: Niklas Cassel @ 2026-03-03 13:49 UTC (permalink / raw)
To: Manikanta Maddireddy
Cc: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, 18255117159, linux-pci,
linux-tegra, linux-kernel
On Tue, Mar 03, 2026 at 12:50:04PM +0530, Manikanta Maddireddy wrote:
> Add PCI device IDs for Tegra194 (0x1ad4) and Tegra234(0x229b) Endpoint
> controllers, so that pci_endpoint_test can bind and run on these
> controllers.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> v2: Remove pci_endpoint_test_data
>
> drivers/misc/pci_endpoint_test.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> index f166b6fea698..fe370c94b191 100644
> --- a/drivers/misc/pci_endpoint_test.c
> +++ b/drivers/misc/pci_endpoint_test.c
> @@ -106,6 +106,9 @@
>
> #define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588
>
> +#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP 0x1ad4
> +#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP 0x229b
> +
> static DEFINE_IDA(pci_endpoint_test_ida);
>
> #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
> @@ -1246,6 +1249,10 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588),
> .driver_data = (kernel_ulong_t)&rk3588_data,
> },
> + { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA194_EP),
> + },
> + { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA234_EP),
> + },
I think these two entries can be a single line each, as the existing entries
without .driver_data.
With that:
Reviewed-by: Niklas Cassel <cassel@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support
2026-03-03 7:19 [PATCH v2 0/5] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manikanta Maddireddy
` (4 preceding siblings ...)
2026-03-03 7:20 ` [PATCH v2 5/5] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries Manikanta Maddireddy
@ 2026-03-21 12:32 ` Manivannan Sadhasivam
5 siblings, 0 replies; 12+ messages in thread
From: Manivannan Sadhasivam @ 2026-03-21 12:32 UTC (permalink / raw)
To: Manikanta Maddireddy
Cc: bhelgaas, lpieralisi, kwilczynski, robh, krzk+dt, conor+dt,
thierry.reding, jonathanh, kishon, arnd, gregkh, Frank.Li, den,
hongxing.zhu, jingoohan1, vidyas, cassel, 18255117159, linux-pci,
linux-tegra, linux-kernel
On Tue, Mar 03, 2026 at 12:49:59PM +0530, Manikanta Maddireddy wrote:
> This series is on top of https://lore.kernel.org/linux-pci/20260217212707.2450423-11-cassel@kernel.org/T/#u
>
> This series wires up Tegra194 and Tegra234 PCI endpoint controllers to the
> shared PCI endpoint and test infrastructure:
>
> 1. Add a new reserved-region type for MSI-X (Table and PBA) so EPC drivers
> can describe hardware-owned MSI-X regions behind a BAR_RESERVED BAR.
>
> 2. Make Tegra194 BAR0 programmable and drop the 1MB fixed size so EPF
> drivers can use it with arbitrary sizes via the existing DBI2 BAR
> programmable path.
>
> 3. Expose Tegra194 BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED with
> the appropriate reserved subregions (MSI-X 128KB, DMA 4KB), keeping
> CONSECUTIVE_BAR_TEST working while allowing the host to use these BARs.
>
> 4. Add Tegra194 and Tegra234 to the pci_endpoint_test device table so the
> endpoint test driver can bind and run on these controllers.
>
> Tested with pci_endpoint_test on Tegra194/Tegra234 endpoint.
>
This series need to be respinned on top of pci/endpoint as we merged patches
that conflict with this.
- Mani
> ./pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -V dma
> TAP version 13
> 1..13
> # Starting 13 tests from 8 test cases.
> # RUN pci_ep_bar.BAR0.BAR_TEST ...
> # OK pci_ep_bar.BAR0.BAR_TEST
> ok 1 pci_ep_bar.BAR0.BAR_TEST
> # RUN pci_ep_bar.BAR1.BAR_TEST ...
> # SKIP BAR is disabled
> # OK pci_ep_bar.BAR1.BAR_TEST
> ok 2 pci_ep_bar.BAR1.BAR_TEST # SKIP BAR is disabled
> # RUN pci_ep_bar.BAR2.BAR_TEST ...
> # SKIP BAR is reserved
> # OK pci_ep_bar.BAR2.BAR_TEST
> ok 3 pci_ep_bar.BAR2.BAR_TEST # SKIP BAR is reserved
> # RUN pci_ep_bar.BAR3.BAR_TEST ...
> # SKIP BAR is disabled
> # OK pci_ep_bar.BAR3.BAR_TEST
> ok 4 pci_ep_bar.BAR3.BAR_TEST # SKIP BAR is disabled
> # RUN pci_ep_bar.BAR4.BAR_TEST ...
> # SKIP BAR is reserved
> # OK pci_ep_bar.BAR4.BAR_TEST
> ok 5 pci_ep_bar.BAR4.BAR_TEST # SKIP BAR is reserved
> # RUN pci_ep_bar.BAR5.BAR_TEST ...
> # SKIP BAR is disabled
> # OK pci_ep_bar.BAR5.BAR_TEST
> ok 6 pci_ep_bar.BAR5.BAR_TEST # SKIP BAR is disabled
> # RUN pci_ep_basic.CONSECUTIVE_BAR_TEST ...
> # OK pci_ep_basic.CONSECUTIVE_BAR_TEST
> ok 7 pci_ep_basic.CONSECUTIVE_BAR_TEST
> # RUN pci_ep_basic.LEGACY_IRQ_TEST ...
> # OK pci_ep_basic.LEGACY_IRQ_TEST
> ok 8 pci_ep_basic.LEGACY_IRQ_TEST
> # RUN pci_ep_basic.MSI_TEST ...
> # SKIP MSI17 is disabled
> # OK pci_ep_basic.MSI_TEST
> ok 9 pci_ep_basic.MSI_TEST # SKIP MSI17 is disabled
> # RUN pci_ep_basic.MSIX_TEST ...
> # pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
> # pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X1
> # pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
> # pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X2
> # pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
> # pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X3
> # pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
> # pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X4
> # pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
> # pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X5
> # pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
> # pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X6
> # pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
> # pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X7
> # pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
> # pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X8
> # SKIP MSI-X9 is disabled
> # OK pci_ep_basic.MSIX_TEST
> ok 10 pci_ep_basic.MSIX_TEST # SKIP MSI-X9 is disabled
> # RUN pci_ep_data_transfer.memcpy.READ_TEST ...
> # OK pci_ep_data_transfer.memcpy.READ_TEST
> ok 11 pci_ep_data_transfer.memcpy.READ_TEST
> # RUN pci_ep_data_transfer.memcpy.WRITE_TEST ...
> # OK pci_ep_data_transfer.memcpy.WRITE_TEST
> ok 12 pci_ep_data_transfer.memcpy.WRITE_TEST
> # RUN pci_ep_data_transfer.memcpy.COPY_TEST ...
> # OK pci_ep_data_transfer.memcpy.COPY_TEST
> ok 13 pci_ep_data_transfer.memcpy.COPY_TEST
> # PASSED: 13 / 13 tests passed.
> # 7 skipped test(s) detected. Consider enabling relevant config options to improve coverage.
> # Totals: pass:6 fail:0 xfail:0 xpass:0 skip:7 error:0
>
> lspci output displays all three BARs with this series,
>
> 0005:01:00.0 Unassigned class [ff00]: NVIDIA Corporation Device 229b
> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
> Latency: 0
> Interrupt: pin A routed to IRQ 165
> IOMMU group: 13
> Region 0: Memory at 2b28001000 (64-bit, non-prefetchable) [size=256]
> Region 2: Memory at 2800000000 (64-bit, prefetchable) [size=128K]
> Region 4: Memory at 2b28000000 (64-bit, non-prefetchable) [size=4K]
>
> Manikanta Maddireddy (5):
> PCI: endpoint: Add reserved region type for MSI-X Table and PBA
> PCI: endpoint: Allow only_64bit on BAR_RESERVED
> PCI: tegra194: Make BAR0 programmable and remove 1MB size limit
> PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit
> BAR_RESERVED
> misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table
> entries
>
> drivers/misc/pci_endpoint_test.c | 7 ++++
> drivers/pci/controller/dwc/pcie-tegra194.c | 46 +++++++++++++++++++---
> include/linux/pci-epc.h | 9 ++---
> 3 files changed, 51 insertions(+), 11 deletions(-)
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 12+ messages in thread