On Tue, Mar 24, 2026 at 11:28:42AM +0530, Kartik Rajput wrote:
> Tegra410 use different offsets for existing I2C registers, update
> the logic to use appropriate offsets per SoC.
> 
> As the register offsets are now defined in the SoC-specific
> tegra_i2c_regs structures, the tegra_i2c_reg_addr() function is no
> longer needed to translate register offsets and has been removed.
> 
> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> Changes in v9:
> 	* Do not remove dvc_writel() and dvc_readl() calls.
> Changes in v8:
> 	* Replace usage of dvc_writel() with writel_relaxed().
> 	* Remove dvc_writel().
> Changes in v7:
> 	* Fix Tegra256 reg offsets, change it to tegra264_i2c_regs as it
> 	  supports SW mutex.
> Changes in v6:
> 	* Do not remove dvc_writel().
> 	* Keep DVC registers defined as a macro.
> 	* Correct Tegra20 DVC register offsets.
> 	* Remove sl_cnfg, sl_addr1 and sl_addr2 registers for DVC and VI
> 	  as they are not used.
> Changes in v2:
> 	* Replace individual is_dvc and is_vi flags with an I2C variant.
> 	* Add tegra20_dvc_i2c_hw and tegra210_vi_i2c_hw in a separate
> 	  patch.
> 	* Use calculated offsets for tegra20_dvc_i2c_regs and
> 	  tegra210_vi_i2c_regs.
> 	* Initialize registers only if they are used on the given SoC.
> ---
>  drivers/i2c/busses/i2c-tegra.c | 359 ++++++++++++++++++++++-----------
>  1 file changed, 237 insertions(+), 122 deletions(-)

Acked-by: Thierry Reding <treding@nvidia.com>