From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [PATCH net-next 3/3] net: stmmac: Introducing support for Page Pool Date: Tue, 23 Jul 2019 22:39:29 +0100 Message-ID: References: <1b254bb7fc6044c5e6e2fdd9e00088d1d13a808b.1562149883.git.joabreu@synopsys.com> <29dcc161-f7c8-026e-c3cc-5adb04df128c@nvidia.com> <20190722101830.GA24948@apalos> <11557fe0-0cba-cb49-0fb6-ad24792d4a53@nvidia.com> <6c769226-bdd9-6fe0-b96b-5a0d800fed24@arm.com> <8756d681-e167-fe4a-c6f0-47ae2dcbb100@nvidia.com> <3255edfa-4465-204b-4751-8d40c8fb1382@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <3255edfa-4465-204b-4751-8d40c8fb1382@arm.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Robin Murphy , Jose Abreu , Lars Persson , Ilias Apalodimas Cc: Joao Pinto , Alexandre Torgue , Maxime Ripard , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , Chen-Yu Tsai , Maxime Coquelin , linux-tegra , Giuseppe Cavallaro , "David S . Miller" , "linux-arm-kernel@lists.infradead.org" List-Id: linux-tegra@vger.kernel.org On 23/07/2019 14:19, Robin Murphy wrote: ... >>> Do you know if the SMMU interrupts are working correctly? If not, it's >>> possible that an incorrect address or mapping direction could lead to >>> the DMA transaction just being silently terminated without any fault >>> indication, which generally presents as inexplicable weirdness (I've >>> certainly seen that on another platform with the mix of an unsupported >>> interrupt controller and an 'imperfect' ethernet driver). >> >> If I simply remove the iommu node for the ethernet controller, then I >> see lots of ... >> >> [=C2=A0=C2=A0=C2=A0 6.296121] arm-smmu 12000000.iommu: Unexpected global= fault, this >> could be serious >> [=C2=A0=C2=A0=C2=A0 6.296125] arm-smmu 12000000.iommu:=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GFSR 0x00000002, >> GFSYNR0 0x00000000, GFSYNR1 0x00000014, GFSYNR2 0x00000000 >> >> So I assume that this is triggering the SMMU interrupt correctly. >=20 > According to tegra186.dtsi it appears you're using the MMU-500 combined > interrupt, so if global faults are being delivered then context faults > *should* also, but I'd be inclined to try a quick hack of the relevant > stmmac_desc_ops::set_addr callback to write some bogus unmapped address > just to make sure arm_smmu_context_fault() then screams as expected, and > we're not missing anything else. I hacked the driver and forced the address to zero for a test and in doing so I see ... [ 10.440072] arm-smmu 12000000.iommu: Unhandled context fault: fsr=3D0x40= 2, iova=3D0x00000000, fsynr=3D0x1c0011, cbfrsynra=3D0x14, cb=3D0 So looks like the interrupts are working AFAICT. Cheers Jon --=20 nvpublic