From: Nicolin Chen <nicolinc@nvidia.com>
To: Ashish Mhetre <amhetre@nvidia.com>
Cc: <joro@8bytes.org>, <will@kernel.org>, <robin.murphy@arm.com>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<jonathanh@nvidia.com>, <thierry.reding@kernel.org>,
<iommu@lists.linux.dev>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] arm64: tegra: Fix CMDQV interrupt type on Tegra264
Date: Mon, 22 Jun 2026 13:58:11 -0700 [thread overview]
Message-ID: <ajmh4/bnq8rB/eCW@nvidia.com> (raw)
In-Reply-To: <20260622065410.2780215-2-amhetre@nvidia.com>
On Mon, Jun 22, 2026 at 06:54:10AM +0000, Ashish Mhetre wrote:
> The CMDQV interrupts on Tegra264 are described as level-triggered, but
> per the hardware interrupt documentation these interrupts are actually
> edge-triggered.
>
> Correct the interrupt type for all CMDQV nodes from IRQ_TYPE_LEVEL_HIGH
> to IRQ_TYPE_EDGE_RISING.
>
> Fixes: fe57d0ac4835 ("arm64: tegra: Add nodes for CMDQV")
> Reported-by: Nicolin Chen <nicolinc@nvidia.com>
> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
next prev parent reply other threads:[~2026-06-22 20:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 6:54 [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example Ashish Mhetre
2026-06-22 6:54 ` [PATCH 2/2] arm64: tegra: Fix CMDQV interrupt type on Tegra264 Ashish Mhetre
2026-06-22 20:58 ` Nicolin Chen [this message]
2026-06-22 16:38 ` [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example Conor Dooley
2026-06-22 20:52 ` Nicolin Chen
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