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Fri, 17 Jul 2026 14:16:55 -0700 Date: Fri, 17 Jul 2026 14:16:53 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: Ashish Mhetre , , , , , , , , , , , Subject: Re: [PATCH v7 2/3] iommu/arm-smmu-v3: Introduce CFGI/TLBI-repeat workaround infrastructure Message-ID: References: <20260714104202.1664187-1-amhetre@nvidia.com> <20260714104202.1664187-3-amhetre@nvidia.com> <20260717201841.GC701389@ziepe.ca> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260717201841.GC701389@ziepe.ca> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|BN7PPF0D942FA9A:EE_ X-MS-Office365-Filtering-Correlation-Id: 442c223d-dea6-4aac-a97e-08dee448c178 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|7416014|376014|23010399003|6133799003|3023799007|5023799004|4143699003|11063799006|56012099006|10067099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WF+oZbWQYg/Q+tdWeeC/9EYKxMlsbs2T2ZIlxl8PrzIrZsOpjAIfK9xyzUaZ3yzFn77yeF96Y18VIv5yjxGcL1QZOblssUXXAqmLev01PFy0dPKahEkTFcOgdBGJxfNt0sGGkE/pZ6hFj2PXL/Q7vbHuLhdDBT7JbpE6cYprk5Q+ktUOKVYFE89jMtY6kQYiwBQd3SWIY9Pi80RdFi8UUdqcJoiJk+svZTA9pOPkTK/7NlkuWURnxIQGMzEtXT8z93JQl3ARwcGKqc4E0FGhdZUBjLfHdTbirv0nUhGKwAgD4P+uSJ7aRGQNIZ3kD/DbFXF1oPUnSIsutXXGnBm4FJTHCXF5vnfvqP2vTHj3e/PskxDQLs9zhpA7ypIQ6upO/FoYOxRPQXg/7xCBCjvfJ4QHVzVFSCTGJurrOaHqocDlbdB6ZY460zlxtFi0D5XO X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 21:17:06.6581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 442c223d-dea6-4aac-a97e-08dee448c178 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF0D942FA9A On Fri, Jul 17, 2026 at 05:18:41PM -0300, Jason Gunthorpe wrote: > On Tue, Jul 14, 2026 at 10:42:01AM +0000, Ashish Mhetre wrote: > Because the VM has access to VCMDQ/etc it can issue commands directly > (maybe not on this chip, but as a general comment), thus invalidation > errata need to be made visible to the VM and we need to expect the VM > will generate invalidations to properly deal with any errata. > > Ie I'd expect the VM to see a "nvidia,tegra264-smmu" compatible string > to activate the errata fix. > > If so then we will already get duplicated invalidations here and then > we will duplicate them again. That's not great. Oh, that's a good point. > On the other hand if you want to emulate a generic and actually > functional SMMU device that has nothing like VCMDQ/etc then you must > do something like this in this patch. Tegra264 has virtualization use case. And It's built with VCMDQ, which should be the default case than the generic vSMMU case. > I was imagining a general direction that we would expose the errata > information to the guest and the guest would have to deal with it. > > Given this is the opposite I wonder if we want to do it. It does make > sense for a chip that probably doesn't have vCMDQ and I don't think > qemu can even create a DT description to trigger the errata anyhow. I don't have the source code of the VMM used on Tegra264, but I believe the guest kernel can be the same copy of kernel as the host. So, its VMM is likely to use the "nvidia,tegra264-smmu" DT compatible string, to trigger the errata at the guest level. > But it starts to become confusing down the road if we decide other > invalidation errata (like the CONT must be RIL thing) must be delt > with by the guest. > > So.. Maybe add a comment why this one is different, or maybe just > disable FEAT_NESTING if there isn't a use case? Given the use cases on Tegra264, instead of patching the iommufd path as this patch does, perhaps we should simply spit a WARN in arm_vsmmu_init(): if (static_branch_unlikely(&arm_smmu_erratum_repeat_tlbi_cfgi_key)) dev_warn(smmu->dev, "guest must WAR the repeat_tlbi_cfgi erratum\n"); ? Thanks Nicolin