On Thu, Aug 27, 2026 at 05:39:19PM +0800, Linmao Li wrote:
> The PCI Express Link Capabilities and Link Status registers are at offsets
> 0x0c and 0x12 from the capability header, respectively.  Since the driver
> uses 0x5a for Link Status, Link Capabilities starts at 0x54, not 0x56.
> 
> Reading a 16-bit value at 0x56 returns the upper half of the Link
> Capabilities register.  When a hotplug-capable port has no link during
> probe, tegra264_pcie_icc_set() consequently derives the maximum speed and
> width from unrelated bits and requests the wrong interconnect bandwidth.
> 
> Use the correct Link Capabilities offset.
> 
> Fixes: 01c3c27a0ef6 ("PCI: tegra264: Add Tegra264 support")
> Signed-off-by: Linmao Li <lilinmao@kylinos.cn>
> ---
>  drivers/pci/controller/pcie-tegra264.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Yes, that's what the manual says, too. /o\

Acked-by: Thierry Reding <treding@nvidia.com>