From: Richard Cheng <icheng@nvidia.com>
To: Srirangan Madhavan <smadhavan@nvidia.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, Li Ming <ming.li@zohomail.com>,
Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v16 07/18] cxl: Share HDM decoder register unpacking
Date: Fri, 30 Oct 2026 14:21:40 +0800 [thread overview]
Message-ID: <auQ27s1rSCcbdRJ3@MWDK4CY14F> (raw)
In-Reply-To: <20261029145703.2185231-8-smadhavan@nvidia.com>
On Thu, Oct 29, 2026 at 02:56:52PM +0800, Srirangan Madhavan wrote:
> Factor common HDM register parsing into cxl_hdm_unpack_decoder().
> Validate range and interleave parameters in locals before publishing the
> decoder configuration, including enable and lock flags. Reject nonzero
> ranges whose end overflows the address space while preserving the
> zero-size range representation.
>
> Read decoder base and size registers low then high through a shared
> helper used by enumeration and the reset snapshot.
>
> Read switch target lists and endpoint DPA skip in their respective
> branches of init_hdm_decoder().
>
> Preserve the decoder ID allocated by cxl_decoder_init() when publishing
> the parsed configuration.
>
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> Assisted-by: LLM
>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
I like this change, LGTM.
Just a small nit below.
> ---
> Reference branch: https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/commit/?id=7d6ed7faf7d8e14abce8ae23902d5323738868d2
> ---
> drivers/cxl/core/core.h | 5 +++
> drivers/cxl/core/hdm.c | 65 ++++++++------------------------
> drivers/cxl/core/hdm_regs.c | 74 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 95 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index fb14b222f3ca..ea539f00e55d 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -147,6 +147,11 @@ void cxl_commit_start_switch(const struct cxl_decoder_config *config,
> u64 targets, void __iomem *hdm);
> int cxld_await_commit(void __iomem *hdm, int id);
>
> +int cxl_hdm_unpack_decoder(struct cxl_decoder_config *config, int id,
> + u32 ctrl, u64 base, u64 size);
> +int cxl_hdm_read_decoder(struct cxl_decoder_config *config, void __iomem *hdm,
> + int id, u32 ctrl);
> +
> int cxl_memdev_init(void);
> void cxl_memdev_exit(void);
> void cxl_mbox_init(void);
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 2c373dfbc070..5b5f5f22ea32 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -938,11 +938,11 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> u64 *dpa_base, struct cxl_endpoint_dvsec_info *info)
> {
> struct cxl_endpoint_decoder *cxled = NULL;
> - u64 size, base, skip, dpa_size, lo, hi;
> - bool committed;
> + u64 size, skip, dpa_size, lo, hi;
> + struct cxl_decoder_config config;
> u32 remainder;
> - int i, rc;
> u32 ctrl;
> + int i, rc;
> union {
> u64 value;
> unsigned char target_id[8];
> @@ -953,41 +953,25 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> which, info);
>
> ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));
> - lo = readl(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(which));
> - hi = readl(hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(which));
> - base = (hi << 32) + lo;
> - lo = readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(which));
> - hi = readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(which));
> - size = (hi << 32) + lo;
> - committed = !!(ctrl & CXL_HDM_DECODER0_CTRL_COMMITTED);
> + rc = cxl_hdm_read_decoder(&config, hdm, which, ctrl);
> + if (rc) {
> + dev_warn(&port->dev,
> + "decoder%d.%d: Invalid decoder configuration (ctrl: %#x): %d\n",
> + port->id, cxld->config.id, ctrl, rc);
> + return rc;
> + }
> +
> + config.id = cxld->config.id;
> cxld->commit = cxl_decoder_commit;
> cxld->reset = cxl_decoder_reset;
> -
> - if (!committed)
> - size = 0;
> - if (base == U64_MAX || size == U64_MAX) {
> - dev_warn(&port->dev, "decoder%d.%d: Invalid resource range\n",
> - port->id, cxld->config.id);
> - return -ENXIO;
> - }
> + cxld->config = config;
> + size = range_len(&cxld->config.hpa_range);
>
> if (info)
> cxled = to_cxl_endpoint_decoder(&cxld->dev);
> - cxld->config.hpa_range = (struct range) {
> - .start = base,
> - .end = base + size - 1,
> - };
>
> /* decoders are enabled if committed */
> - if (committed) {
> - cxld->config.flags |= CXL_DECODER_F_ENABLE;
> - if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)
> - cxld->config.flags |= CXL_DECODER_F_LOCK;
> - if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl))
> - cxld->config.target_type = CXL_DECODER_HOSTONLYMEM;
> - else
> - cxld->config.target_type = CXL_DECODER_DEVMEM;
> -
> + if (cxld->config.flags & CXL_DECODER_F_ENABLE) {
> guard(rwsem_write)(&cxl_rwsem.region);
> if (cxld->config.id != cxl_num_decoders_committed(port)) {
> dev_warn(&port->dev,
> @@ -1021,23 +1005,6 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));
> }
> }
> - rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
> - &cxld->config.interleave_ways);
> - if (rc) {
> - dev_warn(&port->dev,
> - "decoder%d.%d: Invalid interleave ways (ctrl: %#x)\n",
> - port->id, cxld->config.id, ctrl);
> - return rc;
> - }
> - rc = eig_to_granularity(FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl),
> - &cxld->config.interleave_granularity);
> - if (rc) {
> - dev_warn(&port->dev,
> - "decoder%d.%d: Invalid interleave granularity (ctrl: %#x)\n",
> - port->id, cxld->config.id, ctrl);
> - return rc;
> - }
> -
> dev_dbg(&port->dev, "decoder%d.%d: range: %#llx-%#llx iw: %d ig: %d\n",
> port->id, cxld->config.id, cxld->config.hpa_range.start, cxld->config.hpa_range.end,
> cxld->config.interleave_ways, cxld->config.interleave_granularity);
> @@ -1052,7 +1019,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> return 0;
> }
>
> - if (!committed)
> + if (!(cxld->config.flags & CXL_DECODER_F_ENABLE))
> return 0;
>
> dpa_size = div_u64_rem(size, cxld->config.interleave_ways, &remainder);
> diff --git a/drivers/cxl/core/hdm_regs.c b/drivers/cxl/core/hdm_regs.c
> index 53d2f236e49c..684a17e9a601 100644
> --- a/drivers/cxl/core/hdm_regs.c
> +++ b/drivers/cxl/core/hdm_regs.c
> @@ -116,3 +116,77 @@ void cxl_commit_start_switch(const struct cxl_decoder_config *config,
> writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
> }
> EXPORT_SYMBOL_FOR_MODULES(cxl_commit_start_switch, "cxl_core");
> +
> +int cxl_hdm_unpack_decoder(struct cxl_decoder_config *config, int id,
> + u32 ctrl, u64 base, u64 size)
> +{
> + bool committed = FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl);
> + enum cxl_decoder_type target_type = 0;
> + int interleave_granularity;
> + unsigned long flags = 0;
> + struct range hpa_range;
> + int interleave_ways;
> + u64 end;
> + int rc;
> +
> + if (!committed)
> + size = 0;
> + if (base == U64_MAX || size == U64_MAX)
> + return -ENXIO;
> + if (size && check_add_overflow(base, size - 1, &end))
> + return -ENXIO;
> + if (!size)
> + end = base - 1;
> +
What about making "end = base - 1" the default value of "end" and then call
"check_add_overflow()", this would preserve the same behavior while elimate one branch.
Just I think we can add some comments describing it's for the case of zero-size HDM.
Best regards,
Richard Cheng.
> + hpa_range = (struct range) {
> + .start = base,
> + .end = end,
> + };
> +
> + if (committed) {
> + flags |= CXL_DECODER_F_ENABLE;
> + if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)
> + flags |= CXL_DECODER_F_LOCK;
> + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl))
> + target_type = CXL_DECODER_HOSTONLYMEM;
> + else
> + target_type = CXL_DECODER_DEVMEM;
> + }
> +
> + rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
> + &interleave_ways);
> + if (rc)
> + return rc;
> + rc = eig_to_granularity(FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl),
> + &interleave_granularity);
> + if (rc)
> + return rc;
> +
> + *config = (struct cxl_decoder_config) {
> + .id = id,
> + .hpa_range = hpa_range,
> + .interleave_ways = interleave_ways,
> + .interleave_granularity = interleave_granularity,
> + .target_type = target_type,
> + .flags = flags,
> + };
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_FOR_MODULES(cxl_hdm_unpack_decoder, "cxl_core");
> +
> +int cxl_hdm_read_decoder(struct cxl_decoder_config *config, void __iomem *hdm,
> + int id, u32 ctrl)
> +{
> + u64 lo, hi, base, size;
> +
> + lo = readl(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id));
> + hi = readl(hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id));
> + base = (hi << 32) | lo;
> + lo = readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id));
> + hi = readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(id));
> + size = (hi << 32) | lo;
> +
> + return cxl_hdm_unpack_decoder(config, id, ctrl, base, size);
> +}
> +EXPORT_SYMBOL_FOR_MODULES(cxl_hdm_read_decoder, "cxl_core");
> --
> 2.43.0
>
next prev parent reply other threads:[~2026-10-30 6:21 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 14:56 [PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 01/18] cxl: Clarify decoder interleave limit Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 02/18] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 03/18] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 04/18] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 05/18] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 06/18] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-30 4:01 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 07/18] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-30 6:21 ` Richard Cheng [this message]
2026-10-29 14:56 ` [PATCH v16 08/18] cxl: Move cxl_rwsem into built-in code Srirangan Madhavan
2026-10-30 6:26 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 09/18] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-30 6:58 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 10/18] cxl: Build register block helpers into the kernel Srirangan Madhavan
2026-10-30 7:02 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 11/18] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-30 8:22 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 12/18] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-30 3:22 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 13/18] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-30 3:45 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 14/18] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-30 8:37 ` Richard Cheng
2026-10-29 14:57 ` [PATCH v16 15/18] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-29 14:57 ` [PATCH v16 16/18] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-30 8:36 ` Richard Cheng
2026-10-29 14:57 ` [PATCH v16 17/18] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-30 9:22 ` Richard Cheng
2026-10-29 14:57 ` [PATCH v16 18/18] cxl: Add KUnit checks for HDM decoder unpacking Srirangan Madhavan
2026-10-29 18:58 ` [PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices Alison Schofield
2026-10-29 23:03 ` Srirangan Madhavan
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