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Export the interfaces used by > cxl_core and preserve the BAR and offset in the register map. > > Signed-off-by: Srirangan Madhavan Reviewed-by: Richard Cheng > --- > drivers/cxl/core/Makefile | 3 +-- > drivers/cxl/core/regs.c | 9 +++++++++ > drivers/cxl/cxl.h | 3 --- > include/cxl/cxl.h | 6 ++++++ > include/cxl/pci.h | 13 +++++++++++++ > tools/testing/cxl/Kbuild | 1 - > 6 files changed, 29 insertions(+), 6 deletions(-) > > diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile > index 9971efb237fb..9a77e68d44ce 100644 > --- a/drivers/cxl/core/Makefile > +++ b/drivers/cxl/core/Makefile > @@ -1,6 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > obj-$(CONFIG_CXL_BUS) += cxl_core.o > -obj-$(subst m,y,$(CONFIG_CXL_BUS)) += hdm_regs.o hdm_state.o > +obj-$(subst m,y,$(CONFIG_CXL_BUS)) += hdm_regs.o hdm_state.o regs.o > obj-$(CONFIG_CXL_SUSPEND) += suspend.o > > ccflags-y += -I$(srctree)/drivers/cxl > @@ -8,7 +8,6 @@ CFLAGS_trace.o = -DTRACE_INCLUDE_PATH=. -I$(src) > > cxl_core-y := port.o > cxl_core-y += pmem.o > -cxl_core-y += regs.o > cxl_core-y += memdev.o > cxl_core-y += mbox.o > cxl_core-y += pci.o > diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c > index 20c2d9fbcfe7..def3c20d1a7a 100644 > --- a/drivers/cxl/core/regs.c > +++ b/drivers/cxl/core/regs.c > @@ -200,6 +200,7 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, > > return ret_val; > } > +EXPORT_SYMBOL_FOR_MODULES(devm_cxl_iomap_block, "cxl_core"); > > int cxl_map_component_regs(const struct cxl_register_map *map, > struct cxl_component_regs *regs, > @@ -285,6 +286,8 @@ static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_hi, > } > > map->reg_type = reg_type; > + map->bar = bar; > + map->bar_offset = offset; > map->resource = pci_resource_start(pdev, bar) + offset; > map->max_size = pci_resource_len(pdev, bar) - offset; > return true; > @@ -309,6 +312,7 @@ static int __cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_ty > *map = (struct cxl_register_map) { > .host = &pdev->dev, > .resource = CXL_RESOURCE_NONE, > + .bar = -1, > }; > > regloc = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, > @@ -339,6 +343,8 @@ static int __cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_ty > } > > map->resource = CXL_RESOURCE_NONE; > + map->bar = -1; > + map->bar_offset = 0; > if (index == CXL_INSTANCES_COUNT) > return instance; > > @@ -518,6 +524,7 @@ u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb) > > return offset; > } > +EXPORT_SYMBOL_NS_GPL(cxl_rcrb_to_aer, "CXL"); > > static resource_size_t cxl_rcrb_to_linkcap(struct device *dev, struct cxl_dport *dport) > { > @@ -634,6 +641,7 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri > > return component_reg_phys; > } > +EXPORT_SYMBOL_NS_GPL(__rcrb_to_component, "CXL"); > > resource_size_t cxl_rcd_component_reg_phys(struct device *dev, > struct cxl_dport *dport) > @@ -642,3 +650,4 @@ resource_size_t cxl_rcd_component_reg_phys(struct device *dev, > return CXL_RESOURCE_NONE; > return __rcrb_to_component(dev, &dport->rcrb, CXL_RCRB_UPSTREAM); > } > +EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, "CXL"); > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index 688350c7c5fb..ad4e80be2bd7 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -239,9 +239,6 @@ enum cxl_regloc_type; > int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); > int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, > struct cxl_register_map *map, unsigned int index); > -int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, > - struct cxl_register_map *map); > -int cxl_setup_regs(struct cxl_register_map *map); > struct cxl_dport; > int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); > > diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h > index 341a7c52894a..206acf5845e1 100644 > --- a/include/cxl/cxl.h > +++ b/include/cxl/cxl.h > @@ -27,6 +27,7 @@ enum cxl_devtype { > > struct cxl_region; > struct cxl_hdm_info; > +struct pci_dev; > > enum cxl_decoder_type { > CXL_DECODER_DEVMEM = 2, > @@ -150,6 +151,8 @@ struct cxl_pmu_reg_map { > * @base: virtual base of the register-block-BAR + @block_offset > * @resource: physical resource base of the register block > * @max_size: maximum mapping size to perform register search > + * @bar: PCI BAR containing the register block > + * @bar_offset: register block offset relative to @bar > * @reg_type: see enum cxl_regloc_type > * @component_map: cxl_reg_map for component registers > * @device_map: cxl_reg_maps for device registers > @@ -160,6 +163,8 @@ struct cxl_register_map { > void __iomem *base; > resource_size_t resource; > resource_size_t max_size; > + int bar; > + resource_size_t bar_offset; > u8 reg_type; > union { > struct cxl_component_reg_map component_map; > @@ -168,6 +173,7 @@ struct cxl_register_map { > }; > }; > > + > /** > * struct cxl_dpa_perf - DPA performance property entry > * @dpa_range: range for DPA address > diff --git a/include/cxl/pci.h b/include/cxl/pci.h > index 3e0000015871..b15d7e415e27 100644 > --- a/include/cxl/pci.h > +++ b/include/cxl/pci.h > @@ -4,6 +4,8 @@ > #ifndef __CXL_CXL_PCI_H__ > #define __CXL_CXL_PCI_H__ > > +#include > + > /* Register Block Identifier (RBI) */ > enum cxl_regloc_type { > CXL_REGLOC_RBI_EMPTY = 0, > @@ -19,4 +21,15 @@ struct pci_dev; > > int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > struct cxl_register_map *map); > +int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, > + struct cxl_register_map *map); > +int cxl_setup_regs(struct cxl_register_map *map); > +/* > + * CXL r4.0 sec 8.1.3.1: a CXL.mem capable device reports one or two HDM > + * ranges. 00b is illegal when Mem_Capable is set and 11b is reserved. > + */ > +static inline bool cxl_dvsec_hdm_count_valid(unsigned int hdm_count) > +{ > + return hdm_count == 1 || hdm_count == 2; > +} > #endif > diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild > index 2be1df80fcc9..e80500f457a9 100644 > --- a/tools/testing/cxl/Kbuild > +++ b/tools/testing/cxl/Kbuild > @@ -55,7 +55,6 @@ obj-m += cxl_core.o > > cxl_core-y := $(CXL_CORE_SRC)/port.o > cxl_core-y += $(CXL_CORE_SRC)/pmem.o > -cxl_core-y += $(CXL_CORE_SRC)/regs.o > cxl_core-y += $(CXL_CORE_SRC)/memdev.o > cxl_core-y += $(CXL_CORE_SRC)/mbox.o > cxl_core-y += $(CXL_CORE_SRC)/pci.o > -- > 2.43.0 >