[PATCH v7 00/13] Fixes to pcie-tegra194 driver

[PATCH v7 00/13] Fixes to pcie-tegra194 driver

[Manikanta Maddireddy]

This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).

I added below four new patches to fix bugs, commit message of each
patch has the details on the bug and fix.
 - PCI: tegra194: Use HW version number
 - PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on
 - PCI: tegra194: Disable PERST IRQ only in Endpoint mode

Rest of the patches are same as the original V3 series, rebased them on
6.19.0-rc6-next and addressed minor review comments.

I reordered the patches with regard to fixes tag.

Verification details.
 - I verified both Root Port and Endpoint mode controllers on Tegra234 SoC.
 - Basic sanity Link up, configuration space access and BAR access are verified.
 - I verified that ASPM L1.2 capability is disabled for Endpoint mode.
 - I verified suspend to RAM tests with Endpoint mode.

[1] https://patchwork.kernel.org/project/linux-pci/patch/20221013183854.21087-1-vidyas@nvidia.com/

Manikanta Maddireddy (3):
  PCI: tegra194: Disable PERST IRQ only in Endpoint mode
  PCI: tegra194: Use HW version number
  PCI: tegra194: Fix CBB timeout caused by DBI access before core
    power-on

Vidya Sagar (10):
  PCI: tegra194: Fix polling delay for L2 state
  PCI: tegra194: Refactor LTSSM state polling on surprise down
  PCI: tegra194: Don't force the device into the D0 state before L2
  PCI: tegra194: Use devm_gpiod_get_optional() to parse
    "nvidia,refclk-select"
  PCI: tegra194: Disable direct speed change for EP
  PCI: tegra194: Set LTR message request before PCIe link up
  PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP
  PCI: tegra194: Allow system suspend when the Endpoint link is not up
  PCI: tegra194: Free up EP resources during remove()
  PCI: tegra194: Free resources during controller deinitialization

 drivers/pci/controller/dwc/pcie-designware.c |   2 +-
 drivers/pci/controller/dwc/pcie-designware.h |   2 +
 drivers/pci/controller/dwc/pcie-tegra194.c   | 194 +++++++++----------
 3 files changed, 97 insertions(+), 101 deletions(-)

-- 
2.34.1

[PATCH v7 01/13] PCI: tegra194: Fix polling delay for L2 state

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

As per PCIe spec r7.0, sec 5.3.3.2.1, after sending PME_Turn_Off message,
Root Port should wait for 1~10 msec for PME_TO_Ack message. Currently,
driver is polling for 10 msec with 1 usec delay which is aggressive.
Use existing macro PCIE_PME_TO_L2_TIMEOUT_US to poll for 10 msec with
1 msec delay. Since this function is used in non-atomic context only,
use non-atomic poll function.

Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V6 -> V7: Use PCIE_PME_TO_L2_TIMEOUT_US instead PME_ACK_TIMEOUT
Changes V1 -> V6: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 0ddeef70726d..d6c6bd512b51 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -198,8 +198,6 @@
 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK	GENMASK(11, 8)
 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT	8
 
-#define PME_ACK_TIMEOUT 10000
-
 #define LTSSM_TIMEOUT 50000	/* 50ms */
 
 #define GEN3_GEN4_EQ_PRESET_INIT	5
@@ -1553,9 +1551,10 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
 	val |= APPL_PM_XMT_TURNOFF_STATE;
 	appl_writel(pcie, val, APPL_RADM_STATUS);
 
-	return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
-				 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
-				 1, PME_ACK_TIMEOUT);
+	return readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
+				  val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
+				  PCIE_PME_TO_L2_TIMEOUT_US/10,
+				  PCIE_PME_TO_L2_TIMEOUT_US);
 }
 
 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
-- 
2.34.1

[PATCH v7 02/13] PCI: tegra194: Refactor LTSSM state polling on surprise down

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

On surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock ->
Recovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock
and Recovery.RcvrSpeed transit times are 24 msec and 48 msec respectively.
So, the total time taken to transit from L0 to detect state is ~96 msec.
Hence, increase the poll time to 120 msec.

Disable the LTSSM state after it transits to detect to avoid LTSSM
toggling between polling and detect states.

tegra_pcie_dw_pme_turnoff() function is called in non-atomic context
only, so use the non-atomic poll function.

Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V6 -> V7: Append _US to LTSSM macros
Changes V5 -> V6: Retain only one fixes tag
Changes V1 -> V5: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 55 +++++++++++++---------
 1 file changed, 32 insertions(+), 23 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index d6c6bd512b51..afbc0bdd8a93 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -137,7 +137,11 @@
 #define APPL_DEBUG_PM_LINKST_IN_L0		0x11
 #define APPL_DEBUG_LTSSM_STATE_MASK		GENMASK(8, 3)
 #define APPL_DEBUG_LTSSM_STATE_SHIFT		3
-#define LTSSM_STATE_PRE_DETECT			5
+#define LTSSM_STATE_DETECT_QUIET		0x00
+#define LTSSM_STATE_DETECT_ACT			0x08
+#define LTSSM_STATE_PRE_DETECT_QUIET		0x28
+#define LTSSM_STATE_DETECT_WAIT			0x30
+#define LTSSM_STATE_L2_IDLE			0xa8
 
 #define APPL_RADM_STATUS			0xE4
 #define APPL_PM_XMT_TURNOFF_STATE		BIT(0)
@@ -198,7 +202,8 @@
 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK	GENMASK(11, 8)
 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT	8
 
-#define LTSSM_TIMEOUT 50000	/* 50ms */
+#define LTSSM_DELAY_US		10000	/* 10 ms */
+#define LTSSM_TIMEOUT_US	120000	/* 120 ms */
 
 #define GEN3_GEN4_EQ_PRESET_INIT	5
 
@@ -1589,23 +1594,22 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
 		data &= ~APPL_PINMUX_PEX_RST;
 		appl_writel(pcie, data, APPL_PINMUX);
 
+		err = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data,
+			((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
+			((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
+			((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||
+			((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT),
+			LTSSM_DELAY_US, LTSSM_TIMEOUT_US);
+		if (err)
+			dev_info(pcie->dev, "Link didn't go to detect state\n");
+
 		/*
-		 * Some cards do not go to detect state even after de-asserting
-		 * PERST#. So, de-assert LTSSM to bring link to detect state.
+		 * Deassert LTSSM state to stop the state toggling between
+		 * polling and detect.
 		 */
 		data = readl(pcie->appl_base + APPL_CTRL);
 		data &= ~APPL_CTRL_LTSSM_EN;
 		writel(data, pcie->appl_base + APPL_CTRL);
-
-		err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
-						data,
-						((data &
-						APPL_DEBUG_LTSSM_STATE_MASK) >>
-						APPL_DEBUG_LTSSM_STATE_SHIFT) ==
-						LTSSM_STATE_PRE_DETECT,
-						1, LTSSM_TIMEOUT);
-		if (err)
-			dev_info(pcie->dev, "Link didn't go to detect state\n");
 	}
 	/*
 	 * DBI registers may not be accessible after this as PLL-E would be
@@ -1679,19 +1683,24 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
 	if (pcie->ep_state == EP_STATE_DISABLED)
 		return;
 
-	/* Disable LTSSM */
+	ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
+		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
+		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
+		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||
+		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT) ||
+		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_L2_IDLE),
+		LTSSM_DELAY_US, LTSSM_TIMEOUT_US);
+	if (ret)
+		dev_err(pcie->dev, "LTSSM state: 0x%x timeout: %d\n", val, ret);
+
+	/*
+	 * Deassert LTSSM state to stop the state toggling between
+	 * polling and detect.
+	 */
 	val = appl_readl(pcie, APPL_CTRL);
 	val &= ~APPL_CTRL_LTSSM_EN;
 	appl_writel(pcie, val, APPL_CTRL);
 
-	ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
-				 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>
-				 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
-				 LTSSM_STATE_PRE_DETECT,
-				 1, LTSSM_TIMEOUT);
-	if (ret)
-		dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
-
 	reset_control_assert(pcie->core_rst);
 
 	tegra_pcie_disable_phy(pcie);
-- 
2.34.1

Re: [PATCH v7 02/13] PCI: tegra194: Refactor LTSSM state polling on surprise down

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:24:37PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> On surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock ->
> Recovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock
> and Recovery.RcvrSpeed transit times are 24 msec and 48 msec respectively.
> So, the total time taken to transit from L0 to detect state is ~96 msec.
> Hence, increase the poll time to 120 msec.
> 
> Disable the LTSSM state after it transits to detect to avoid LTSSM
> toggling between polling and detect states.
> 

These are two separate changes (increasing poll time and disabling LTSSM).
Please split this into two patches. A patch should only fix one issue, not more.

- Mani

> tegra_pcie_dw_pme_turnoff() function is called in non-atomic context
> only, so use the non-atomic poll function.
> 
> Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V6 -> V7: Append _US to LTSSM macros
> Changes V5 -> V6: Retain only one fixes tag
> Changes V1 -> V5: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 55 +++++++++++++---------
>  1 file changed, 32 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index d6c6bd512b51..afbc0bdd8a93 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -137,7 +137,11 @@
>  #define APPL_DEBUG_PM_LINKST_IN_L0		0x11
>  #define APPL_DEBUG_LTSSM_STATE_MASK		GENMASK(8, 3)
>  #define APPL_DEBUG_LTSSM_STATE_SHIFT		3
> -#define LTSSM_STATE_PRE_DETECT			5
> +#define LTSSM_STATE_DETECT_QUIET		0x00
> +#define LTSSM_STATE_DETECT_ACT			0x08
> +#define LTSSM_STATE_PRE_DETECT_QUIET		0x28
> +#define LTSSM_STATE_DETECT_WAIT			0x30
> +#define LTSSM_STATE_L2_IDLE			0xa8
>  
>  #define APPL_RADM_STATUS			0xE4
>  #define APPL_PM_XMT_TURNOFF_STATE		BIT(0)
> @@ -198,7 +202,8 @@
>  #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK	GENMASK(11, 8)
>  #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT	8
>  
> -#define LTSSM_TIMEOUT 50000	/* 50ms */
> +#define LTSSM_DELAY_US		10000	/* 10 ms */
> +#define LTSSM_TIMEOUT_US	120000	/* 120 ms */
>  
>  #define GEN3_GEN4_EQ_PRESET_INIT	5
>  
> @@ -1589,23 +1594,22 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>  		data &= ~APPL_PINMUX_PEX_RST;
>  		appl_writel(pcie, data, APPL_PINMUX);
>  
> +		err = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data,
> +			((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
> +			((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
> +			((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||
> +			((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT),
> +			LTSSM_DELAY_US, LTSSM_TIMEOUT_US);
> +		if (err)
> +			dev_info(pcie->dev, "Link didn't go to detect state\n");
> +
>  		/*
> -		 * Some cards do not go to detect state even after de-asserting
> -		 * PERST#. So, de-assert LTSSM to bring link to detect state.
> +		 * Deassert LTSSM state to stop the state toggling between
> +		 * polling and detect.
>  		 */
>  		data = readl(pcie->appl_base + APPL_CTRL);
>  		data &= ~APPL_CTRL_LTSSM_EN;
>  		writel(data, pcie->appl_base + APPL_CTRL);
> -
> -		err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
> -						data,
> -						((data &
> -						APPL_DEBUG_LTSSM_STATE_MASK) >>
> -						APPL_DEBUG_LTSSM_STATE_SHIFT) ==
> -						LTSSM_STATE_PRE_DETECT,
> -						1, LTSSM_TIMEOUT);
> -		if (err)
> -			dev_info(pcie->dev, "Link didn't go to detect state\n");
>  	}
>  	/*
>  	 * DBI registers may not be accessible after this as PLL-E would be
> @@ -1679,19 +1683,24 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
>  	if (pcie->ep_state == EP_STATE_DISABLED)
>  		return;
>  
> -	/* Disable LTSSM */
> +	ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
> +		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
> +		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
> +		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||
> +		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT) ||
> +		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_L2_IDLE),
> +		LTSSM_DELAY_US, LTSSM_TIMEOUT_US);
> +	if (ret)
> +		dev_err(pcie->dev, "LTSSM state: 0x%x timeout: %d\n", val, ret);
> +
> +	/*
> +	 * Deassert LTSSM state to stop the state toggling between
> +	 * polling and detect.
> +	 */
>  	val = appl_readl(pcie, APPL_CTRL);
>  	val &= ~APPL_CTRL_LTSSM_EN;
>  	appl_writel(pcie, val, APPL_CTRL);
>  
> -	ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
> -				 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>
> -				 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
> -				 LTSSM_STATE_PRE_DETECT,
> -				 1, LTSSM_TIMEOUT);
> -	if (ret)
> -		dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
> -
>  	reset_control_assert(pcie->core_rst);
>  
>  	tegra_pcie_disable_phy(pcie);
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 03/13] PCI: tegra194: Don't force the device into the D0 state before L2

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe Endpoint device
should be in D3 state to assert wake# pin. This takes precedence over PCI
Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management
which states that the device can be put into D0 state before taking the
link to L2 state. To enable the wake functionality for Endpoint devices,
do not force the devices to D0 state before taking the link to L2 state.
There is no functional issue with the Endpoint devices where the link
doesn't go into L2 state (the reason why the earlier change was made in
the first place) as the Root Port proceeds with the usual flow post PME
timeout.

Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V6 -> V7: Fix commit message
Changes V1 -> V6: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 41 ----------------------
 1 file changed, 41 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index afbc0bdd8a93..831986de584e 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1258,44 +1258,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
 	return 0;
 }
 
-static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
-{
-	struct dw_pcie_rp *pp = &pcie->pci.pp;
-	struct pci_bus *child, *root_port_bus = NULL;
-	struct pci_dev *pdev;
-
-	/*
-	 * link doesn't go into L2 state with some of the endpoints with Tegra
-	 * if they are not in D0 state. So, need to make sure that immediate
-	 * downstream devices are in D0 state before sending PME_TurnOff to put
-	 * link into L2 state.
-	 * This is as per PCI Express Base r4.0 v1.0 September 27-2017,
-	 * 5.2 Link State Power Management (Page #428).
-	 */
-
-	list_for_each_entry(child, &pp->bridge->bus->children, node) {
-		if (child->parent == pp->bridge->bus) {
-			root_port_bus = child;
-			break;
-		}
-	}
-
-	if (!root_port_bus) {
-		dev_err(pcie->dev, "Failed to find downstream bus of Root Port\n");
-		return;
-	}
-
-	/* Bring downstream devices to D0 if they are not already in */
-	list_for_each_entry(pdev, &root_port_bus->devices, bus_list) {
-		if (PCI_SLOT(pdev->devfn) == 0) {
-			if (pci_set_power_state(pdev, PCI_D0))
-				dev_err(pcie->dev,
-					"Failed to transition %s to D0 state\n",
-					dev_name(&pdev->dev));
-		}
-	}
-}
-
 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
 {
 	pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
@@ -1625,7 +1587,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
 
 static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
 {
-	tegra_pcie_downstream_dev_to_D0(pcie);
 	dw_pcie_host_deinit(&pcie->pci.pp);
 	tegra_pcie_dw_pme_turnoff(pcie);
 	tegra_pcie_unconfig_controller(pcie);
@@ -2335,7 +2296,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
 	if (!pcie->link_state)
 		return 0;
 
-	tegra_pcie_downstream_dev_to_D0(pcie);
 	tegra_pcie_dw_pme_turnoff(pcie);
 	tegra_pcie_unconfig_controller(pcie);
 
@@ -2409,7 +2369,6 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
 			return;
 
 		debugfs_remove_recursive(pcie->debugfs);
-		tegra_pcie_downstream_dev_to_D0(pcie);
 
 		disable_irq(pcie->pci.pp.irq);
 		if (IS_ENABLED(CONFIG_PCI_MSI))
-- 
2.34.1

Re: [PATCH v7 03/13] PCI: tegra194: Don't force the device into the D0 state before L2

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:24:38PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe Endpoint device
> should be in D3 state to assert wake# pin. This takes precedence over PCI

WAKE#

> Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management
> which states that the device can be put into D0 state before taking the
> link to L2 state. To enable the wake functionality for Endpoint devices,
> do not force the devices to D0 state before taking the link to L2 state.
> There is no functional issue with the Endpoint devices where the link
> doesn't go into L2 state (the reason why the earlier change was made in
> the first place) as the Root Port proceeds with the usual flow post PME
> timeout.
> 

So the previous claim in the comments is not true?

I agree with this patch in principle, but just want to know why the comment
claimed there is an issue if the devices are not in D0 state.

- Mani

> Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V6 -> V7: Fix commit message
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 41 ----------------------
>  1 file changed, 41 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index afbc0bdd8a93..831986de584e 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1258,44 +1258,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
>  	return 0;
>  }
>  
> -static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
> -{
> -	struct dw_pcie_rp *pp = &pcie->pci.pp;
> -	struct pci_bus *child, *root_port_bus = NULL;
> -	struct pci_dev *pdev;
> -
> -	/*
> -	 * link doesn't go into L2 state with some of the endpoints with Tegra
> -	 * if they are not in D0 state. So, need to make sure that immediate
> -	 * downstream devices are in D0 state before sending PME_TurnOff to put
> -	 * link into L2 state.
> -	 * This is as per PCI Express Base r4.0 v1.0 September 27-2017,
> -	 * 5.2 Link State Power Management (Page #428).
> -	 */
> -
> -	list_for_each_entry(child, &pp->bridge->bus->children, node) {
> -		if (child->parent == pp->bridge->bus) {
> -			root_port_bus = child;
> -			break;
> -		}
> -	}
> -
> -	if (!root_port_bus) {
> -		dev_err(pcie->dev, "Failed to find downstream bus of Root Port\n");
> -		return;
> -	}
> -
> -	/* Bring downstream devices to D0 if they are not already in */
> -	list_for_each_entry(pdev, &root_port_bus->devices, bus_list) {
> -		if (PCI_SLOT(pdev->devfn) == 0) {
> -			if (pci_set_power_state(pdev, PCI_D0))
> -				dev_err(pcie->dev,
> -					"Failed to transition %s to D0 state\n",
> -					dev_name(&pdev->dev));
> -		}
> -	}
> -}
> -
>  static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
>  {
>  	pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
> @@ -1625,7 +1587,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>  
>  static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
>  {
> -	tegra_pcie_downstream_dev_to_D0(pcie);
>  	dw_pcie_host_deinit(&pcie->pci.pp);
>  	tegra_pcie_dw_pme_turnoff(pcie);
>  	tegra_pcie_unconfig_controller(pcie);
> @@ -2335,7 +2296,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>  	if (!pcie->link_state)
>  		return 0;
>  
> -	tegra_pcie_downstream_dev_to_D0(pcie);
>  	tegra_pcie_dw_pme_turnoff(pcie);
>  	tegra_pcie_unconfig_controller(pcie);
>  
> @@ -2409,7 +2369,6 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
>  			return;
>  
>  		debugfs_remove_recursive(pcie->debugfs);
> -		tegra_pcie_downstream_dev_to_D0(pcie);
>  
>  		disable_irq(pcie->pci.pp.irq);
>  		if (IS_ENABLED(CONFIG_PCI_MSI))
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 03/13] PCI: tegra194: Don't force the device into the D0 state before L2

[Manikanta Maddireddy]

On 05/03/26 3:10 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:24:38PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe Endpoint device
>> should be in D3 state to assert wake# pin. This takes precedence over PCI
> 
> WAKE#
> 
>> Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management
>> which states that the device can be put into D0 state before taking the
>> link to L2 state. To enable the wake functionality for Endpoint devices,
>> do not force the devices to D0 state before taking the link to L2 state.
>> There is no functional issue with the Endpoint devices where the link
>> doesn't go into L2 state (the reason why the earlier change was made in
>> the first place) as the Root Port proceeds with the usual flow post PME
>> timeout.
>>
> 
> So the previous claim in the comments is not true?
> 
> I agree with this patch in principle, but just want to know why the comment
> claimed there is an issue if the devices are not in D0 state.
> 
> - Mani
No, previous claim is true. D0 fix is done to fix L2 timeout with a 
specific Endpoint. However, later realized that it is breaking wake 
functionality with other Endpoints. As I mentioned in the commit message 
reverting D0 fix still causes L2 timeout with that specific Endpoint, 
but it doesn't cause any functional issue.

- Manikanta
> 
>> Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V6 -> V7: Fix commit message
>> Changes V1 -> V6: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 41 ----------------------
>>   1 file changed, 41 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index afbc0bdd8a93..831986de584e 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1258,44 +1258,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
>>   	return 0;
>>   }
>>   
>> -static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
>> -{
>> -	struct dw_pcie_rp *pp = &pcie->pci.pp;
>> -	struct pci_bus *child, *root_port_bus = NULL;
>> -	struct pci_dev *pdev;
>> -
>> -	/*
>> -	 * link doesn't go into L2 state with some of the endpoints with Tegra
>> -	 * if they are not in D0 state. So, need to make sure that immediate
>> -	 * downstream devices are in D0 state before sending PME_TurnOff to put
>> -	 * link into L2 state.
>> -	 * This is as per PCI Express Base r4.0 v1.0 September 27-2017,
>> -	 * 5.2 Link State Power Management (Page #428).
>> -	 */
>> -
>> -	list_for_each_entry(child, &pp->bridge->bus->children, node) {
>> -		if (child->parent == pp->bridge->bus) {
>> -			root_port_bus = child;
>> -			break;
>> -		}
>> -	}
>> -
>> -	if (!root_port_bus) {
>> -		dev_err(pcie->dev, "Failed to find downstream bus of Root Port\n");
>> -		return;
>> -	}
>> -
>> -	/* Bring downstream devices to D0 if they are not already in */
>> -	list_for_each_entry(pdev, &root_port_bus->devices, bus_list) {
>> -		if (PCI_SLOT(pdev->devfn) == 0) {
>> -			if (pci_set_power_state(pdev, PCI_D0))
>> -				dev_err(pcie->dev,
>> -					"Failed to transition %s to D0 state\n",
>> -					dev_name(&pdev->dev));
>> -		}
>> -	}
>> -}
>> -
>>   static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
>>   {
>>   	pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
>> @@ -1625,7 +1587,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>>   
>>   static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
>>   {
>> -	tegra_pcie_downstream_dev_to_D0(pcie);
>>   	dw_pcie_host_deinit(&pcie->pci.pp);
>>   	tegra_pcie_dw_pme_turnoff(pcie);
>>   	tegra_pcie_unconfig_controller(pcie);
>> @@ -2335,7 +2296,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>>   	if (!pcie->link_state)
>>   		return 0;
>>   
>> -	tegra_pcie_downstream_dev_to_D0(pcie);
>>   	tegra_pcie_dw_pme_turnoff(pcie);
>>   	tegra_pcie_unconfig_controller(pcie);
>>   
>> @@ -2409,7 +2369,6 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
>>   			return;
>>   
>>   		debugfs_remove_recursive(pcie->debugfs);
>> -		tegra_pcie_downstream_dev_to_D0(pcie);
>>   
>>   		disable_irq(pcie->pci.pp.irq);
>>   		if (IS_ENABLED(CONFIG_PCI_MSI))
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic

Re: [PATCH v7 03/13] PCI: tegra194: Don't force the device into the D0 state before L2

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 06:51:23PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 3:10 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:24:38PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe Endpoint device
> > > should be in D3 state to assert wake# pin. This takes precedence over PCI
> > 
> > WAKE#
> > 
> > > Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management
> > > which states that the device can be put into D0 state before taking the
> > > link to L2 state. To enable the wake functionality for Endpoint devices,
> > > do not force the devices to D0 state before taking the link to L2 state.
> > > There is no functional issue with the Endpoint devices where the link
> > > doesn't go into L2 state (the reason why the earlier change was made in
> > > the first place) as the Root Port proceeds with the usual flow post PME
> > > timeout.
> > > 
> > 
> > So the previous claim in the comments is not true?
> > 
> > I agree with this patch in principle, but just want to know why the comment
> > claimed there is an issue if the devices are not in D0 state.
> > 
> > - Mani
> No, previous claim is true. D0 fix is done to fix L2 timeout with a specific
> Endpoint. However, later realized that it is breaking wake functionality
> with other Endpoints. As I mentioned in the commit message reverting D0 fix
> still causes L2 timeout with that specific Endpoint, but it doesn't cause
> any functional issue.
> 

Okay, I just looked up the mentioned section in r4.0. The spec suggests that it
is possible to initiate power removal without transitioning the device into
D3Hot. It didn't explicitly say that "put device into D0", which is quite
misleading.

Anyway, the previous comment as well as the workaround is not correct. So ammend
the commit message as per above in next version.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 04/13] PCI: tegra194: Disable PERST IRQ only in Endpoint mode

[Manikanta Maddireddy]

The PERST (PERST#) GPIO interrupt is only registered when the controller
is operating in Endpoint mode. In Root Port mode, the PERST GPIO is
configured as an output to control downstream devices, and no interrupt
is registered for it.

Currently, tegra_pcie_dw_stop_link() unconditionally calls disable_irq()
on pex_rst_irq, which causes issues in Root Port mode where this IRQ is
not registered.

Fix this by only disabling the PERST IRQ when operating in Endpoint mode,
where the interrupt is actually registered and used to detect PERST
assertion/deassertion from the host.

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe Endpoint mode in Tegra194")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 831986de584e..dd8b92fbd393 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1025,7 +1025,8 @@ static void tegra_pcie_dw_stop_link(struct dw_pcie *pci)
 {
 	struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
 
-	disable_irq(pcie->pex_rst_irq);
+	if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+		disable_irq(pcie->pex_rst_irq);
 }
 
 static const struct dw_pcie_ops tegra_dw_pcie_ops = {
-- 
2.34.1

[PATCH v7 05/13] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select"

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

The GPIO DT property "nvidia,refclk-select" to select the PCIe reference
clock is optional. Use devm_gpiod_get_optional() to get it.

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V5 -> V7: None
Changes V4 -> V5: Added Fixes tag
Changes V1 -> V4: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index dd8b92fbd393..7dcf3e3596dd 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1167,9 +1167,9 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
 		return err;
 	}
 
-	pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev,
-						    "nvidia,refclk-select",
-						    GPIOD_OUT_HIGH);
+	pcie->pex_refclk_sel_gpiod = devm_gpiod_get_optional(pcie->dev,
+							     "nvidia,refclk-select",
+							     GPIOD_OUT_HIGH);
 	if (IS_ERR(pcie->pex_refclk_sel_gpiod)) {
 		int err = PTR_ERR(pcie->pex_refclk_sel_gpiod);
 		const char *level = KERN_ERR;
-- 
2.34.1

[PATCH v7 06/13] PCI: tegra194: Disable direct speed change for EP

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Disable direct speed change for the Endpoint to prevent it from initiating
the speed change post physical layer link up at gen1. This leaves the speed
change ownership with the host.

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 7dcf3e3596dd..2da3478f0b5f 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1805,6 +1805,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 
 	reset_control_deassert(pcie->core_rst);
 
+	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+	val &= ~PORT_LOGIC_SPEED_CHANGE;
+	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
 	if (pcie->update_fc_fixup) {
 		val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
 		val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
-- 
2.34.1

Re: [PATCH v7 06/13] PCI: tegra194: Disable direct speed change for EP

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:24:41PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Disable direct speed change for the Endpoint to prevent it from initiating
> the speed change post physical layer link up at gen1. This leaves the speed
> change ownership with the host.
> 

Why?

- Mani

> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V7: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 7dcf3e3596dd..2da3478f0b5f 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1805,6 +1805,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  
>  	reset_control_deassert(pcie->core_rst);
>  
> +	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> +	val &= ~PORT_LOGIC_SPEED_CHANGE;
> +	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> +
>  	if (pcie->update_fc_fixup) {
>  		val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
>  		val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 06/13] PCI: tegra194: Disable direct speed change for EP

[Manikanta Maddireddy]

On 05/03/26 3:13 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:24:41PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> Disable direct speed change for the Endpoint to prevent it from initiating
>> the speed change post physical layer link up at gen1. This leaves the speed
>> change ownership with the host.
>>
> 
> Why?
> 
> - Mani
In pre silicon sim tests our HW team identified that Endpoint is trying 
to initiate speed change after secondary bus reset. So, our HW team 
recommended to disable direct speed change feature in Endpoint to keep 
the speed change control with host.

- Manikanta

> 
>> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V1 -> V7: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 7dcf3e3596dd..2da3478f0b5f 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1805,6 +1805,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>>   
>>   	reset_control_deassert(pcie->core_rst);
>>   
>> +	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
>> +	val &= ~PORT_LOGIC_SPEED_CHANGE;
>> +	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
>> +
>>   	if (pcie->update_fc_fixup) {
>>   		val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
>>   		val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic

Re: [PATCH v7 06/13] PCI: tegra194: Disable direct speed change for EP

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 07:14:14PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 3:13 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:24:41PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > Disable direct speed change for the Endpoint to prevent it from initiating
> > > the speed change post physical layer link up at gen1. This leaves the speed
> > > change ownership with the host.
> > > 
> > 
> > Why?
> > 
> > - Mani
> In pre silicon sim tests our HW team identified that Endpoint is trying to
> initiate speed change after secondary bus reset. So, our HW team recommended
> to disable direct speed change feature in Endpoint to keep the speed change
> control with host.
> 

Please add the above into to the commit message.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 07/13] PCI: tegra194: Set LTR message request before PCIe link up

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

LTR message should be sent as soon as the Root Port enables LTR in the
Endpoint. Set snoop & no snoop LTR timing and LTR message request before
PCIe links up. This ensures that LTR message is sent upstream as soon as
LTR is enabled.

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V6 -> V7: Retain FIELD_PREP() usage
Changes V1 -> V6: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 2da3478f0b5f..b50229df890e 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -485,15 +485,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
 	if (val & PCI_COMMAND_MASTER) {
 		ktime_t timeout;
 
-		/* 110us for both snoop and no-snoop */
-		val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
-		      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
-		      LTR_MSG_REQ |
-		      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
-		      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
-		      LTR_NOSNOOP_MSG_REQ;
-		appl_writel(pcie, val, APPL_LTR_MSG_1);
-
 		/* Send LTR upstream */
 		val = appl_readl(pcie, APPL_LTR_MSG_2);
 		val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
@@ -1803,6 +1794,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
 	appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
 
+	/* 110us for both snoop and no-snoop */
+	val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
+	      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
+	      LTR_MSG_REQ |
+	      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
+	      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
+	      LTR_NOSNOOP_MSG_REQ;
+	appl_writel(pcie, val, APPL_LTR_MSG_1);
+
 	reset_control_deassert(pcie->core_rst);
 
 	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-- 
2.34.1

Re: [PATCH v7 07/13] PCI: tegra194: Set LTR message request before PCIe link up

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:24:42PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> LTR message should be sent as soon as the Root Port enables LTR in the
> Endpoint. Set snoop & no snoop LTR timing and LTR message request before
> PCIe links up. This ensures that LTR message is sent upstream as soon as
> LTR is enabled.
> 



> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V6 -> V7: Retain FIELD_PREP() usage
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 2da3478f0b5f..b50229df890e 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -485,15 +485,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
>  	if (val & PCI_COMMAND_MASTER) {
>  		ktime_t timeout;
>  
> -		/* 110us for both snoop and no-snoop */
> -		val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
> -		      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
> -		      LTR_MSG_REQ |
> -		      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
> -		      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
> -		      LTR_NOSNOOP_MSG_REQ;
> -		appl_writel(pcie, val, APPL_LTR_MSG_1);
> -
>  		/* Send LTR upstream */
>  		val = appl_readl(pcie, APPL_LTR_MSG_2);
>  		val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
> @@ -1803,6 +1794,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  	val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
>  	appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
>  
> +	/* 110us for both snoop and no-snoop */
> +	val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
> +	      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
> +	      LTR_MSG_REQ |
> +	      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
> +	      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
> +	      LTR_NOSNOOP_MSG_REQ;

As per the spec, the device is not permitted to request Snoop/No-Snoop latencies
greater that the Max Snoop/No-Snoop latencies set by the host depending on the
platform requirement.

But here the driver is just using a hardcoded value without reading Max values.
It may be assuming that the host is always going to be another NVidia platform,
so it sends out fixed LTR latencies, but that's not going to be true always.

Also, the host can update the Max latencies at any point of time during runtime.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 07/13] PCI: tegra194: Set LTR message request before PCIe link up

[Manikanta Maddireddy]

On 05/03/26 3:48 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:24:42PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> LTR message should be sent as soon as the Root Port enables LTR in the
>> Endpoint. Set snoop & no snoop LTR timing and LTR message request before
>> PCIe links up. This ensures that LTR message is sent upstream as soon as
>> LTR is enabled.
>>
> 
> 
> 
>> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V6 -> V7: Retain FIELD_PREP() usage
>> Changes V1 -> V6: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 18 +++++++++---------
>>   1 file changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 2da3478f0b5f..b50229df890e 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -485,15 +485,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
>>   	if (val & PCI_COMMAND_MASTER) {
>>   		ktime_t timeout;
>>   
>> -		/* 110us for both snoop and no-snoop */
>> -		val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
>> -		      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
>> -		      LTR_MSG_REQ |
>> -		      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
>> -		      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
>> -		      LTR_NOSNOOP_MSG_REQ;
>> -		appl_writel(pcie, val, APPL_LTR_MSG_1);
>> -
>>   		/* Send LTR upstream */
>>   		val = appl_readl(pcie, APPL_LTR_MSG_2);
>>   		val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
>> @@ -1803,6 +1794,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>>   	val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
>>   	appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
>>   
>> +	/* 110us for both snoop and no-snoop */
>> +	val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
>> +	      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
>> +	      LTR_MSG_REQ |
>> +	      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
>> +	      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
>> +	      LTR_NOSNOOP_MSG_REQ;
> 
> As per the spec, the device is not permitted to request Snoop/No-Snoop latencies
> greater that the Max Snoop/No-Snoop latencies set by the host depending on the
> platform requirement.
> 
> But here the driver is just using a hardcoded value without reading Max values.
> It may be assuming that the host is always going to be another NVidia platform,
> so it sends out fixed LTR latencies, but that's not going to be true always.
> 
> Also, the host can update the Max latencies at any point of time during runtime.
> 
> - Mani
> 
Agree, but this patch is only addressing case where max latencies are 
not yet programmed by the host.  Without this programming Endpoint sends 
0 latencies to the host. Once host sets max latencies in the config 
space, HW compares the above latencies and the max latencies configured 
by host and sends appropriate values to the host.

- Manikanta

-- 
nvpublic

Re: [PATCH v7 07/13] PCI: tegra194: Set LTR message request before PCIe link up

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 07:19:47PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 3:48 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:24:42PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > LTR message should be sent as soon as the Root Port enables LTR in the
> > > Endpoint. Set snoop & no snoop LTR timing and LTR message request before
> > > PCIe links up. This ensures that LTR message is sent upstream as soon as
> > > LTR is enabled.
> > > 
> > 
> > 
> > 
> > > Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> > > Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> > > Tested-by: Jon Hunter <jonathanh@nvidia.com>
> > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> > > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> > > ---
> > > Changes V6 -> V7: Retain FIELD_PREP() usage
> > > Changes V1 -> V6: None
> > > 
> > >   drivers/pci/controller/dwc/pcie-tegra194.c | 18 +++++++++---------
> > >   1 file changed, 9 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > index 2da3478f0b5f..b50229df890e 100644
> > > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > @@ -485,15 +485,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
> > >   	if (val & PCI_COMMAND_MASTER) {
> > >   		ktime_t timeout;
> > > -		/* 110us for both snoop and no-snoop */
> > > -		val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
> > > -		      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
> > > -		      LTR_MSG_REQ |
> > > -		      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
> > > -		      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
> > > -		      LTR_NOSNOOP_MSG_REQ;
> > > -		appl_writel(pcie, val, APPL_LTR_MSG_1);
> > > -
> > >   		/* Send LTR upstream */
> > >   		val = appl_readl(pcie, APPL_LTR_MSG_2);
> > >   		val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
> > > @@ -1803,6 +1794,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
> > >   	val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
> > >   	appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
> > > +	/* 110us for both snoop and no-snoop */
> > > +	val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
> > > +	      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
> > > +	      LTR_MSG_REQ |
> > > +	      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
> > > +	      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
> > > +	      LTR_NOSNOOP_MSG_REQ;
> > 
> > As per the spec, the device is not permitted to request Snoop/No-Snoop latencies
> > greater that the Max Snoop/No-Snoop latencies set by the host depending on the
> > platform requirement.
> > 
> > But here the driver is just using a hardcoded value without reading Max values.
> > It may be assuming that the host is always going to be another NVidia platform,
> > so it sends out fixed LTR latencies, but that's not going to be true always.
> > 
> > Also, the host can update the Max latencies at any point of time during runtime.
> > 
> > - Mani
> > 
> Agree, but this patch is only addressing case where max latencies are not
> yet programmed by the host.  Without this programming Endpoint sends 0
> latencies to the host. Once host sets max latencies in the config space, HW
> compares the above latencies and the max latencies configured by host and
> sends appropriate values to the host.
> 

Okay, this should also be clarified in commit message.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

PERST# and CLKREQ# pinctrl settings should be applied for both Root Port
and Endpoint mode. Move pinctrl_pm_select_default_state() function call
from Root Port specific configuration function to probe().

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V5 -> V7: None
Changes V4 -> V5: Use dev_err_probe() function
Changes V1 -> V4: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index b50229df890e..5b79d3c28ba6 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1598,12 +1598,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
 		goto fail_pm_get_sync;
 	}
 
-	ret = pinctrl_pm_select_default_state(dev);
-	if (ret < 0) {
-		dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
-		goto fail_pm_get_sync;
-	}
-
 	ret = tegra_pcie_init_controller(pcie);
 	if (ret < 0) {
 		dev_err(dev, "Failed to initialize controller: %d\n", ret);
@@ -2077,6 +2071,10 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
 	pp = &pci->pp;
 	pp->num_vectors = MAX_MSI_IRQS;
 
+	ret = pinctrl_pm_select_default_state(dev);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Failed to configure sideband pins: %d\n", ret);
+
 	ret = tegra_pcie_dw_parse_dt(pcie);
 	if (ret < 0) {
 		const char *level = KERN_ERR;
-- 
2.34.1

Re: [PATCH v7 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:24:43PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> PERST# and CLKREQ# pinctrl settings should be applied for both Root Port
> and Endpoint mode. Move pinctrl_pm_select_default_state() function call
> from Root Port specific configuration function to probe().
> 

Why should this driver care about setting default pinctrl state? Why can't it
rely on the pinctrl framework as like other drivers?

- Mani

> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V5 -> V7: None
> Changes V4 -> V5: Use dev_err_probe() function
> Changes V1 -> V4: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index b50229df890e..5b79d3c28ba6 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1598,12 +1598,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>  		goto fail_pm_get_sync;
>  	}
>  
> -	ret = pinctrl_pm_select_default_state(dev);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
> -		goto fail_pm_get_sync;
> -	}
> -
>  	ret = tegra_pcie_init_controller(pcie);
>  	if (ret < 0) {
>  		dev_err(dev, "Failed to initialize controller: %d\n", ret);
> @@ -2077,6 +2071,10 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>  	pp = &pci->pp;
>  	pp->num_vectors = MAX_MSI_IRQS;
>  
> +	ret = pinctrl_pm_select_default_state(dev);
> +	if (ret < 0)
> +		return dev_err_probe(dev, ret, "Failed to configure sideband pins: %d\n", ret);
> +
>  	ret = tegra_pcie_dw_parse_dt(pcie);
>  	if (ret < 0) {
>  		const char *level = KERN_ERR;
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

[Manikanta Maddireddy]

On 05/03/26 3:49 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:24:43PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> PERST# and CLKREQ# pinctrl settings should be applied for both Root Port
>> and Endpoint mode. Move pinctrl_pm_select_default_state() function call
>> from Root Port specific configuration function to probe().
>>
> 
> Why should this driver care about setting default pinctrl state? Why can't it
> rely on the pinctrl framework as like other drivers?
> 
> - Mani

pinctrl framework doesn't know if PCIe controller is going to be 
configured in Endpoint or Root port mode. In Root port mode PERST# 
signal should be configured as special function IO pin(SFIO) and in 
Endpoint mode it should be configured as general purpose IO pin(GPIO). 
So, PCIe driver should request appropriate pinctl values.

- Manikanta

> 
>> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V5 -> V7: None
>> Changes V4 -> V5: Use dev_err_probe() function
>> Changes V1 -> V4: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++------
>>   1 file changed, 4 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index b50229df890e..5b79d3c28ba6 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1598,12 +1598,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>>   		goto fail_pm_get_sync;
>>   	}
>>   
>> -	ret = pinctrl_pm_select_default_state(dev);
>> -	if (ret < 0) {
>> -		dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
>> -		goto fail_pm_get_sync;
>> -	}
>> -
>>   	ret = tegra_pcie_init_controller(pcie);
>>   	if (ret < 0) {
>>   		dev_err(dev, "Failed to initialize controller: %d\n", ret);
>> @@ -2077,6 +2071,10 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>>   	pp = &pci->pp;
>>   	pp->num_vectors = MAX_MSI_IRQS;
>>   
>> +	ret = pinctrl_pm_select_default_state(dev);
>> +	if (ret < 0)
>> +		return dev_err_probe(dev, ret, "Failed to configure sideband pins: %d\n", ret);
>> +
>>   	ret = tegra_pcie_dw_parse_dt(pcie);
>>   	if (ret < 0) {
>>   		const char *level = KERN_ERR;
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic

Re: [PATCH v7 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 07:24:48PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 3:49 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:24:43PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > PERST# and CLKREQ# pinctrl settings should be applied for both Root Port
> > > and Endpoint mode. Move pinctrl_pm_select_default_state() function call
> > > from Root Port specific configuration function to probe().
> > > 
> > 
> > Why should this driver care about setting default pinctrl state? Why can't it
> > rely on the pinctrl framework as like other drivers?
> > 
> > - Mani
> 
> pinctrl framework doesn't know if PCIe controller is going to be configured
> in Endpoint or Root port mode. In Root port mode PERST# signal should be
> configured as special function IO pin(SFIO) and in Endpoint mode it should
> be configured as general purpose IO pin(GPIO). So, PCIe driver should
> request appropriate pinctl values.
> 

So you are saying that irrespective of board design, you can configure the
controller in host/endpoint mode? Is it possible? Dual mode controllers are
quite common in other SoCs, but they rely on devicetree to either configure the
controller in host or endpoint mode.

If the devicetree enables the endpoint node, why can't it also define the
pinctrl config?

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

[Manikanta Maddireddy]

On 16/03/26 7:01 am, Manivannan Sadhasivam wrote:
> On Sun, Mar 15, 2026 at 07:24:48PM +0530, Manikanta Maddireddy wrote:
>>
>>
>> On 05/03/26 3:49 pm, Manivannan Sadhasivam wrote:
>>> On Tue, Mar 03, 2026 at 12:24:43PM +0530, Manikanta Maddireddy wrote:
>>>> From: Vidya Sagar <vidyas@nvidia.com>
>>>>
>>>> PERST# and CLKREQ# pinctrl settings should be applied for both Root Port
>>>> and Endpoint mode. Move pinctrl_pm_select_default_state() function call
>>>> from Root Port specific configuration function to probe().
>>>>
>>>
>>> Why should this driver care about setting default pinctrl state? Why can't it
>>> rely on the pinctrl framework as like other drivers?
>>>
>>> - Mani
>>
>> pinctrl framework doesn't know if PCIe controller is going to be configured
>> in Endpoint or Root port mode. In Root port mode PERST# signal should be
>> configured as special function IO pin(SFIO) and in Endpoint mode it should
>> be configured as general purpose IO pin(GPIO). So, PCIe driver should
>> request appropriate pinctl values.
>>
> 
> So you are saying that irrespective of board design, you can configure the
> controller in host/endpoint mode? Is it possible? Dual mode controllers are
> quite common in other SoCs, but they rely on devicetree to either configure the
> controller in host or endpoint mode.
> 
> If the devicetree enables the endpoint node, why can't it also define the
> pinctrl config?
> 
> - Mani
> 

Root Port and Endpoint role switch is through device tree only.
pinctrl settings are defined in Root Port/Endpoint device tree node, but 
to apply the pinctrl settings respective driver need to call 
pinctrl_pm_select_default_state().

arch/arm64/boot/dts/nvidia/tegra234.dtsi

                 pcie-ep@140e0000 {
                         compatible = "nvidia,tegra234-pcie-ep";
                         ...

                         pinctrl-names = "default";
                         pinctrl-0 = <&pex_rst_c10_in_state>;
                         ...
                 }

arch/arm64/boot/dts/nvidia/tegra194.dtsi
                 pcie@141a0000 {
                         compatible = "nvidia,tegra194-pcie";
                         ...

                         pinctrl-names = "default";
                         pinctrl-0 = <&pex_rst_c5_out_state>, 
<&pex_clkreq_c5_bi_dir_state>;
                         ...
                 }
- Manikanta

-- 
nvpublic

Re: [PATCH v7 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

[Manivannan Sadhasivam]

On Mon, Mar 16, 2026 at 09:11:53AM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 16/03/26 7:01 am, Manivannan Sadhasivam wrote:
> > On Sun, Mar 15, 2026 at 07:24:48PM +0530, Manikanta Maddireddy wrote:
> > > 
> > > 
> > > On 05/03/26 3:49 pm, Manivannan Sadhasivam wrote:
> > > > On Tue, Mar 03, 2026 at 12:24:43PM +0530, Manikanta Maddireddy wrote:
> > > > > From: Vidya Sagar <vidyas@nvidia.com>
> > > > > 
> > > > > PERST# and CLKREQ# pinctrl settings should be applied for both Root Port
> > > > > and Endpoint mode. Move pinctrl_pm_select_default_state() function call
> > > > > from Root Port specific configuration function to probe().
> > > > > 
> > > > 
> > > > Why should this driver care about setting default pinctrl state? Why can't it
> > > > rely on the pinctrl framework as like other drivers?
> > > > 
> > > > - Mani
> > > 
> > > pinctrl framework doesn't know if PCIe controller is going to be configured
> > > in Endpoint or Root port mode. In Root port mode PERST# signal should be
> > > configured as special function IO pin(SFIO) and in Endpoint mode it should
> > > be configured as general purpose IO pin(GPIO). So, PCIe driver should
> > > request appropriate pinctl values.
> > > 
> > 
> > So you are saying that irrespective of board design, you can configure the
> > controller in host/endpoint mode? Is it possible? Dual mode controllers are
> > quite common in other SoCs, but they rely on devicetree to either configure the
> > controller in host or endpoint mode.
> > 
> > If the devicetree enables the endpoint node, why can't it also define the
> > pinctrl config?
> > 
> > - Mani
> > 
> 
> Root Port and Endpoint role switch is through device tree only.
> pinctrl settings are defined in Root Port/Endpoint device tree node, but to
> apply the pinctrl settings respective driver need to call
> pinctrl_pm_select_default_state().
> 

First of all calling pinctrl_pm_select_default_state() from probe() is not
correct. pinctrl_pm_* APIs are supposed to be called from PM callbacks.

Also, the pinctrl default state *should* be selected by the pinctrl core. So
what this driver is doing here looks redundant.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 09/13] PCI: tegra194: Allow system suspend when the Endpoint link is not up

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Only a Root Port initiates the L2 sequence. PCIe link is kept in L2 state
during suspend. If Endpoint mode is enabled and the link is up, the
software cannot proceed with suspend. However, when the PCIe Endpoint
driver is probed, but the PCIe link is not up, Tegra can go into suspend
state. So, allow system to suspend in this case.

Fixes: de2bbf2b71bb ("PCI: tegra194: Don't allow suspend when Tegra PCIe is in EP mode")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 31 +++++++++++++++++-----
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 5b79d3c28ba6..b2794be35cfe 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2267,16 +2267,28 @@ static void tegra_pcie_dw_remove(struct platform_device *pdev)
 		gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
 }
 
-static int tegra_pcie_dw_suspend_late(struct device *dev)
+static int tegra_pcie_dw_suspend(struct device *dev)
 {
 	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
-	u32 val;
 
 	if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
-		dev_err(dev, "Failed to Suspend as Tegra PCIe is in EP mode\n");
-		return -EPERM;
+		if (pcie->ep_state == EP_STATE_ENABLED) {
+			dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed\n");
+			return -EPERM;
+		}
+
+		disable_irq(pcie->pex_rst_irq);
+		return 0;
 	}
 
+	return 0;
+}
+
+static int tegra_pcie_dw_suspend_late(struct device *dev)
+{
+	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
+	u32 val;
+
 	if (!pcie->link_state)
 		return 0;
 
@@ -2296,6 +2308,9 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
 {
 	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
 
+	if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+		return 0;
+
 	if (!pcie->link_state)
 		return 0;
 
@@ -2310,6 +2325,9 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
 	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
 	int ret;
 
+	if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+		return 0;
+
 	if (!pcie->link_state)
 		return 0;
 
@@ -2342,8 +2360,8 @@ static int tegra_pcie_dw_resume_early(struct device *dev)
 	u32 val;
 
 	if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
-		dev_err(dev, "Suspend is not supported in EP mode");
-		return -ENOTSUPP;
+		enable_irq(pcie->pex_rst_irq);
+		return 0;
 	}
 
 	if (!pcie->link_state)
@@ -2448,6 +2466,7 @@ static const struct of_device_id tegra_pcie_dw_of_match[] = {
 };
 
 static const struct dev_pm_ops tegra_pcie_dw_pm_ops = {
+	.suspend = tegra_pcie_dw_suspend,
 	.suspend_late = tegra_pcie_dw_suspend_late,
 	.suspend_noirq = tegra_pcie_dw_suspend_noirq,
 	.resume_noirq = tegra_pcie_dw_resume_noirq,
-- 
2.34.1

Re: [PATCH v7 09/13] PCI: tegra194: Allow system suspend when the Endpoint link is not up

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:24:44PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Only a Root Port initiates the L2 sequence. PCIe link is kept in L2 state

It is not Root Port, it is the host software which initiates the L2 entry
sequence.

And L2 is only guaranteed if the Vaux is available.

> during suspend. If Endpoint mode is enabled and the link is up, the
> software cannot proceed with suspend. However, when the PCIe Endpoint
> driver is probed, but the PCIe link is not up, Tegra can go into suspend
> state. So, allow system to suspend in this case.
> 
> Fixes: de2bbf2b71bb ("PCI: tegra194: Don't allow suspend when Tegra PCIe is in EP mode")
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V7: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 31 +++++++++++++++++-----
>  1 file changed, 25 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 5b79d3c28ba6..b2794be35cfe 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2267,16 +2267,28 @@ static void tegra_pcie_dw_remove(struct platform_device *pdev)
>  		gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
>  }
>  
> -static int tegra_pcie_dw_suspend_late(struct device *dev)
> +static int tegra_pcie_dw_suspend(struct device *dev)
>  {
>  	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
> -	u32 val;
>  
>  	if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
> -		dev_err(dev, "Failed to Suspend as Tegra PCIe is in EP mode\n");
> -		return -EPERM;
> +		if (pcie->ep_state == EP_STATE_ENABLED) {
> +			dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed\n");
> +			return -EPERM;
> +		}
> +
> +		disable_irq(pcie->pex_rst_irq);

So you just disable PERST# IRQ during suspend? And even if the host deasserts
PERST#, EP is not going to wakeup?

Technically it is possible that whenever the EP wakes up, it will see PERST# IRQ
since PERST# is level triggered, but it just sounds dumb to let the endpoint
sleep after host deasserting PERST#.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 09/13] PCI: tegra194: Allow system suspend when the Endpoint link is not up

[Manikanta Maddireddy]

On 05/03/26 3:59 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:24:44PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> Only a Root Port initiates the L2 sequence. PCIe link is kept in L2 state
> 
> It is not Root Port, it is the host software which initiates the L2 entry
> sequence.
> 
> And L2 is only guaranteed if the Vaux is available.
> 
I will fix the commit message.

>> during suspend. If Endpoint mode is enabled and the link is up, the
>> software cannot proceed with suspend. However, when the PCIe Endpoint
>> driver is probed, but the PCIe link is not up, Tegra can go into suspend
>> state. So, allow system to suspend in this case.
>>
>> Fixes: de2bbf2b71bb ("PCI: tegra194: Don't allow suspend when Tegra PCIe is in EP mode")
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V1 -> V7: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 31 +++++++++++++++++-----
>>   1 file changed, 25 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 5b79d3c28ba6..b2794be35cfe 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -2267,16 +2267,28 @@ static void tegra_pcie_dw_remove(struct platform_device *pdev)
>>   		gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
>>   }
>>   
>> -static int tegra_pcie_dw_suspend_late(struct device *dev)
>> +static int tegra_pcie_dw_suspend(struct device *dev)
>>   {
>>   	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> -	u32 val;
>>   
>>   	if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
>> -		dev_err(dev, "Failed to Suspend as Tegra PCIe is in EP mode\n");
>> -		return -EPERM;
>> +		if (pcie->ep_state == EP_STATE_ENABLED) {
>> +			dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed\n");
>> +			return -EPERM;
>> +		}
>> +
>> +		disable_irq(pcie->pex_rst_irq);
> 
> So you just disable PERST# IRQ during suspend? And even if the host deasserts
> PERST#, EP is not going to wakeup?
> 
> Technically it is possible that whenever the EP wakes up, it will see PERST# IRQ
> since PERST# is level triggered, but it just sounds dumb to let the endpoint
> sleep after host deasserting PERST#.
> 
> - Mani
> 
I need to check if PERST# line in Tegra has wake feature and 
corresponding PMC changes are available. Anyway adding wake feature will 
be separate patch. In this current patch, I am trying to reduce the 
impact of Endpoint on suspend. If Endpoint is never initialized I don't 
see a reason to block suspend. Are you OK with this current patch to 
reduce the impact on suspend? Or do you have any suggestions?

- Manikanta

-- 
nvpublic

Re: [PATCH v7 09/13] PCI: tegra194: Allow system suspend when the Endpoint link is not up

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 07:40:04PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 3:59 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:24:44PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > Only a Root Port initiates the L2 sequence. PCIe link is kept in L2 state
> > 
> > It is not Root Port, it is the host software which initiates the L2 entry
> > sequence.
> > 
> > And L2 is only guaranteed if the Vaux is available.
> > 
> I will fix the commit message.
> 
> > > during suspend. If Endpoint mode is enabled and the link is up, the
> > > software cannot proceed with suspend. However, when the PCIe Endpoint
> > > driver is probed, but the PCIe link is not up, Tegra can go into suspend
> > > state. So, allow system to suspend in this case.
> > > 
> > > Fixes: de2bbf2b71bb ("PCI: tegra194: Don't allow suspend when Tegra PCIe is in EP mode")
> > > Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> > > Tested-by: Jon Hunter <jonathanh@nvidia.com>
> > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> > > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> > > ---
> > > Changes V1 -> V7: None
> > > 
> > >   drivers/pci/controller/dwc/pcie-tegra194.c | 31 +++++++++++++++++-----
> > >   1 file changed, 25 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > index 5b79d3c28ba6..b2794be35cfe 100644
> > > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > @@ -2267,16 +2267,28 @@ static void tegra_pcie_dw_remove(struct platform_device *pdev)
> > >   		gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
> > >   }
> > > -static int tegra_pcie_dw_suspend_late(struct device *dev)
> > > +static int tegra_pcie_dw_suspend(struct device *dev)
> > >   {
> > >   	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
> > > -	u32 val;
> > >   	if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
> > > -		dev_err(dev, "Failed to Suspend as Tegra PCIe is in EP mode\n");
> > > -		return -EPERM;
> > > +		if (pcie->ep_state == EP_STATE_ENABLED) {
> > > +			dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed\n");
> > > +			return -EPERM;
> > > +		}
> > > +
> > > +		disable_irq(pcie->pex_rst_irq);
> > 
> > So you just disable PERST# IRQ during suspend? And even if the host deasserts
> > PERST#, EP is not going to wakeup?
> > 
> > Technically it is possible that whenever the EP wakes up, it will see PERST# IRQ
> > since PERST# is level triggered, but it just sounds dumb to let the endpoint
> > sleep after host deasserting PERST#.
> > 
> > - Mani
> > 
> I need to check if PERST# line in Tegra has wake feature and corresponding
> PMC changes are available. Anyway adding wake feature will be separate
> patch. In this current patch, I am trying to reduce the impact of Endpoint
> on suspend. If Endpoint is never initialized I don't see a reason to block
> suspend. Are you OK with this current patch to reduce the impact on suspend?
> Or do you have any suggestions?
> 

Fine with me. I was just checking the possibility of waking the endpoint during
PERST# deassert.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 10/13] PCI: tegra194: Free up EP resources during remove()

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Free up the resources during remove() that were acquired by the DesignWare
driver for the Endpoint mode during probe().

Fixes: bb617cbd8151 ("PCI: tegra194: Clean up the exit path for Endpoint mode")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index b2794be35cfe..1963165967b9 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2248,6 +2248,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
 static void tegra_pcie_dw_remove(struct platform_device *pdev)
 {
 	struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
+	struct dw_pcie_ep *ep = &pcie->pci.ep;
 
 	if (pcie->of_data->mode == DW_PCIE_RC_TYPE) {
 		if (!pcie->link_state)
@@ -2259,6 +2260,7 @@ static void tegra_pcie_dw_remove(struct platform_device *pdev)
 	} else {
 		disable_irq(pcie->pex_rst_irq);
 		pex_ep_event_pex_rst_assert(pcie);
+		dw_pcie_ep_deinit(ep);
 	}
 
 	pm_runtime_disable(pcie->dev);
-- 
2.34.1

[PATCH v7 11/13] PCI: tegra194: Use HW version number

[Manikanta Maddireddy]

Tegra194 PCIe driver uses custom version number to detect Tegra194 and
Tegra234 IPs. With version detect logic added, version check results
in mismatch warnings.

Use HW version numbers in Tegra194 driver to avoid this kernel warnings.

Fixed version check to enable ecrc for Tegra194.
Existing 490A check is left intact in case any HW relying on existing check.

Fixes: a54e19073718 ("PCI: tegra194: Add Tegra234 PCIe support")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-designware.c | 2 +-
 drivers/pci/controller/dwc/pcie-designware.h | 2 ++
 drivers/pci/controller/dwc/pcie-tegra194.c   | 4 ++--
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 345365ea97c7..0dac5d2f5a83 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 	if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&
 	    dw_pcie_ver_is_ge(pci, 460A))
 		val |= PCIE_ATU_INCREASE_REGION_SIZE;
-	if (dw_pcie_ver_is(pci, 490A))
+	if (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))
 		val = dw_pcie_enable_ecrc(val);
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
 
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index f4cf1602cc99..5bceadbd2c9f 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -34,8 +34,10 @@
 #define DW_PCIE_VER_470A		0x3437302a
 #define DW_PCIE_VER_480A		0x3438302a
 #define DW_PCIE_VER_490A		0x3439302a
+#define DW_PCIE_VER_500A		0x3530302a
 #define DW_PCIE_VER_520A		0x3532302a
 #define DW_PCIE_VER_540A		0x3534302a
+#define DW_PCIE_VER_562A		0x3536322a
 
 #define __dw_pcie_ver_cmp(_pci, _ver, _op) \
 	((_pci)->version _op DW_PCIE_VER_ ## _ver)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 1963165967b9..1c6543341fb9 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -35,8 +35,8 @@
 #include <soc/tegra/bpmp-abi.h>
 #include "../../pci.h"
 
-#define TEGRA194_DWC_IP_VER			0x490A
-#define TEGRA234_DWC_IP_VER			0x562A
+#define TEGRA194_DWC_IP_VER			DW_PCIE_VER_500A
+#define TEGRA234_DWC_IP_VER			DW_PCIE_VER_562A
 
 #define APPL_PINMUX				0x0
 #define APPL_PINMUX_PEX_RST			BIT(0)
-- 
2.34.1

Re: [PATCH v7 11/13] PCI: tegra194: Use HW version number

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:24:46PM +0530, Manikanta Maddireddy wrote:
> Tegra194 PCIe driver uses custom version number to detect Tegra194 and
> Tegra234 IPs. With version detect logic added, version check results
> in mismatch warnings.
> 

What warnings? This sounds like a separate fix.

> Use HW version numbers in Tegra194 driver to avoid this kernel warnings.
> 
> Fixed version check to enable ecrc for Tegra194.

This is a separate fix, so separate patch. Do not combine two unreleated fixes
in a single patch.

- Mani

> Existing 490A check is left intact in case any HW relying on existing check.
> 
> Fixes: a54e19073718 ("PCI: tegra194: Add Tegra234 PCIe support")
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V7: None
> 
>  drivers/pci/controller/dwc/pcie-designware.c | 2 +-
>  drivers/pci/controller/dwc/pcie-designware.h | 2 ++
>  drivers/pci/controller/dwc/pcie-tegra194.c   | 4 ++--
>  3 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 345365ea97c7..0dac5d2f5a83 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
>  	if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&
>  	    dw_pcie_ver_is_ge(pci, 460A))
>  		val |= PCIE_ATU_INCREASE_REGION_SIZE;
> -	if (dw_pcie_ver_is(pci, 490A))
> +	if (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))
>  		val = dw_pcie_enable_ecrc(val);
>  	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
>  
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index f4cf1602cc99..5bceadbd2c9f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -34,8 +34,10 @@
>  #define DW_PCIE_VER_470A		0x3437302a
>  #define DW_PCIE_VER_480A		0x3438302a
>  #define DW_PCIE_VER_490A		0x3439302a
> +#define DW_PCIE_VER_500A		0x3530302a
>  #define DW_PCIE_VER_520A		0x3532302a
>  #define DW_PCIE_VER_540A		0x3534302a
> +#define DW_PCIE_VER_562A		0x3536322a
>  
>  #define __dw_pcie_ver_cmp(_pci, _ver, _op) \
>  	((_pci)->version _op DW_PCIE_VER_ ## _ver)
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 1963165967b9..1c6543341fb9 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -35,8 +35,8 @@
>  #include <soc/tegra/bpmp-abi.h>
>  #include "../../pci.h"
>  
> -#define TEGRA194_DWC_IP_VER			0x490A
> -#define TEGRA234_DWC_IP_VER			0x562A
> +#define TEGRA194_DWC_IP_VER			DW_PCIE_VER_500A
> +#define TEGRA234_DWC_IP_VER			DW_PCIE_VER_562A
>  
>  #define APPL_PINMUX				0x0
>  #define APPL_PINMUX_PEX_RST			BIT(0)
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 12/13] PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on

[Manikanta Maddireddy]

When PERST# is deasserted twice (assert -> deassert -> assert -> deassert),
a CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc
(PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify()
and dw_pcie_ep_cleanup() are called before reset_control_deassert() powers
on the controller core.

The call chain that causes the timeout:
  pex_ep_event_pex_rst_deassert()
    pci_epc_deinit_notify()
      pci_epf_test_epc_deinit()
        pci_epf_test_clear_bar()
          pci_epc_clear_bar()
            dw_pcie_ep_clear_bar()
              __dw_pcie_ep_reset_bar()
                dw_pcie_dbi_ro_wr_en()  <- Accesses 0x8bc DBI register
    reset_control_deassert(pcie->core_rst)  <- Core powered on HERE

The DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only
accessible after the controller core is powered on via
reset_control_deassert(pcie->core_rst). Accessing them before this point
results in a CBB timeout because the hardware is not yet operational.

Fix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to
after reset_control_deassert(pcie->core_rst), ensuring the controller is
fully powered on before any DBI register accesses occur.

Fixes: 40e2125381dc ("PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 1c6543341fb9..a311c31109e3 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1726,10 +1726,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 		goto fail_phy;
 	}
 
-	/* Perform cleanup that requires refclk */
-	pci_epc_deinit_notify(pcie->pci.ep.epc);
-	dw_pcie_ep_cleanup(&pcie->pci.ep);
-
 	/* Clear any stale interrupt statuses */
 	appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
 	appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
@@ -1799,6 +1795,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 
 	reset_control_deassert(pcie->core_rst);
 
+	/* Perform cleanup that requires refclk and core reset deasserted */
+	pci_epc_deinit_notify(pcie->pci.ep.epc);
+	dw_pcie_ep_cleanup(&pcie->pci.ep);
+
 	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 	val &= ~PORT_LOGIC_SPEED_CHANGE;
 	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
-- 
2.34.1

[PATCH v7 13/13] PCI: tegra194: Free resources during controller deinitialization

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Call pci_epc_deinit_notify() during controller deinitialization to free the
resources allocated by Endpoint function driver. This is safe to call
during PCIe assert sequence because we don't expect Endpoint function
driver to touch hardware in deinit function.

Fixes: 40e2125381dc ("PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V5 -> V7: None
Changes V4 -> V5: Remove pci_epc_deinit_notify() call from pex_ep_event_pex_rst_deassert()
Changes V1 -> V4: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index a311c31109e3..b1ae46761915 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1624,12 +1624,16 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
 
 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
 {
+	struct dw_pcie *pci = &pcie->pci;
+	struct dw_pcie_ep *ep = &pci->ep;
 	u32 val;
 	int ret;
 
 	if (pcie->ep_state == EP_STATE_DISABLED)
 		return;
 
+	pci_epc_deinit_notify(ep->epc);
+
 	ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
 		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
 		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
@@ -1796,7 +1800,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	reset_control_deassert(pcie->core_rst);
 
 	/* Perform cleanup that requires refclk and core reset deasserted */
-	pci_epc_deinit_notify(pcie->pci.ep.epc);
 	dw_pcie_ep_cleanup(&pcie->pci.ep);
 
 	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-- 
2.34.1

Re: [PATCH v7 13/13] PCI: tegra194: Free resources during controller deinitialization

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:24:48PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Call pci_epc_deinit_notify() during controller deinitialization to free the
> resources allocated by Endpoint function driver. This is safe to call
> during PCIe assert sequence because we don't expect Endpoint function
> driver to touch hardware in deinit function.
> 

Are you sure? The epf-test driver itself touches DBI space during deinit.

- Mani

> Fixes: 40e2125381dc ("PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()")
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V5 -> V7: None
> Changes V4 -> V5: Remove pci_epc_deinit_notify() call from pex_ep_event_pex_rst_deassert()
> Changes V1 -> V4: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index a311c31109e3..b1ae46761915 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1624,12 +1624,16 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>  
>  static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
>  {
> +	struct dw_pcie *pci = &pcie->pci;
> +	struct dw_pcie_ep *ep = &pci->ep;
>  	u32 val;
>  	int ret;
>  
>  	if (pcie->ep_state == EP_STATE_DISABLED)
>  		return;
>  
> +	pci_epc_deinit_notify(ep->epc);
> +
>  	ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
>  		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
>  		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
> @@ -1796,7 +1800,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  	reset_control_deassert(pcie->core_rst);
>  
>  	/* Perform cleanup that requires refclk and core reset deasserted */
> -	pci_epc_deinit_notify(pcie->pci.ep.epc);
>  	dw_pcie_ep_cleanup(&pcie->pci.ep);
>  
>  	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 13/13] PCI: tegra194: Free resources during controller deinitialization

[Manikanta Maddireddy]

On 05/03/26 4:13 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:24:48PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> Call pci_epc_deinit_notify() during controller deinitialization to free the
>> resources allocated by Endpoint function driver. This is safe to call
>> during PCIe assert sequence because we don't expect Endpoint function
>> driver to touch hardware in deinit function.
>>
> 
> Are you sure? The epf-test driver itself touches DBI space during deinit.
> 
> - Mani
Ok, I see epf-test is doing clear_bar which access DBI space.
But, I think we should give give a chance to EPF drivers to clean up 
resources and stop using them in PERST# assert. Let me know your inputs 
on this.

- Manikanta

> 
>> Fixes: 40e2125381dc ("PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()")
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V5 -> V7: None
>> Changes V4 -> V5: Remove pci_epc_deinit_notify() call from pex_ep_event_pex_rst_deassert()
>> Changes V1 -> V4: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 5 ++++-
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index a311c31109e3..b1ae46761915 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1624,12 +1624,16 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>>   
>>   static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
>>   {
>> +	struct dw_pcie *pci = &pcie->pci;
>> +	struct dw_pcie_ep *ep = &pci->ep;
>>   	u32 val;
>>   	int ret;
>>   
>>   	if (pcie->ep_state == EP_STATE_DISABLED)
>>   		return;
>>   
>> +	pci_epc_deinit_notify(ep->epc);
>> +
>>   	ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
>>   		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
>>   		((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
>> @@ -1796,7 +1800,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>>   	reset_control_deassert(pcie->core_rst);
>>   
>>   	/* Perform cleanup that requires refclk and core reset deasserted */
>> -	pci_epc_deinit_notify(pcie->pci.ep.epc);
>>   	dw_pcie_ep_cleanup(&pcie->pci.ep);
>>   
>>   	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic

Re: [PATCH v7 13/13] PCI: tegra194: Free resources during controller deinitialization

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 07:46:49PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 4:13 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:24:48PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > Call pci_epc_deinit_notify() during controller deinitialization to free the
> > > resources allocated by Endpoint function driver. This is safe to call
> > > during PCIe assert sequence because we don't expect Endpoint function
> > > driver to touch hardware in deinit function.
> > > 
> > 
> > Are you sure? The epf-test driver itself touches DBI space during deinit.
> > 
> > - Mani
> Ok, I see epf-test is doing clear_bar which access DBI space.
> But, I think we should give give a chance to EPF drivers to clean up
> resources and stop using them in PERST# assert. Let me know your inputs on
> this.
> 

You cannot control the EPF behavior from the controller driver. So I'd prefer
not changing the flow.

- Mani

-- 
மணிவண்ணன் சதாசிவம்