Linux Tegra architecture development
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From: Robin Murphy <robin.murphy@arm.com>
To: Ashish Mhetre <amhetre@nvidia.com>,
	Jon Hunter <jonathanh@nvidia.com>,
	will@kernel.org, joro@8bytes.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, nicolinc@nvidia.com
Cc: thierry.reding@gmail.com, vdumpa@nvidia.com, jgg@ziepe.ca,
	linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH V2 3/3] arm64: dts: nvidia: Add nodes for CMDQV
Date: Mon, 1 Dec 2025 14:13:00 +0000	[thread overview]
Message-ID: <b66e1993-fe07-4826-9bf4-728e640ccacd@arm.com> (raw)
In-Reply-To: <acae92d8-3394-436c-be8e-8bed7a923e85@nvidia.com>

On 2025-12-01 9:36 am, Ashish Mhetre wrote:
> 
> On 11/25/2025 3:52 PM, Jon Hunter wrote:
>>
>>
>> On 25/11/2025 07:16, Ashish Mhetre wrote:
>>> The Command Queue Virtualization (CMDQV) hardware is part of the
>>> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
>>> virtualizing the command queue for the SMMU.
>>>
>>> Update SMMU compatible strings to use nvidia,tegra264-smmu to enable
>>> CMDQV support. Add device tree nodes for the CMDQV hardware and enable
>>> them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU
>>> instance is paired with its corresponding CMDQV instance via the
>>> nvidia,cmdqv property.
>>>
>>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>>> ---
>>>   .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi |  8 +++
>>>   arch/arm64/boot/dts/nvidia/tegra264.dtsi      | 55 +++++++++++++++++--
>>>   2 files changed, 58 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/ 
>>> arm64/boot/dts/nvidia/tegra264-p3834.dtsi
>>> index 06795c82427a..375d122b92fa 100644
>>> --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
>>> +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
>>> @@ -26,5 +26,13 @@ iommu@5000000 {
>>>           iommu@6000000 {
>>>               status = "okay";
>>>           };
>>> +
>>> +        cmdqv@5200000 {
>>> +            status = "okay";
>>> +        };
>>
>> This needs to be ordered in the file according to its address.
> 
> Hi Jon, Thanks for the review.
> cmdqv nodes follow same ordering as its corresponding iommu nodes.
> I have added them immediately after corresponding iommu nodes.
> Can you please check and see if it's fine? Same applies to your
> similar comments below as well.

It's fairly standard practice to order DT nodes by unit address where 
applicable (and alphabetically by node name otherwise). The platform 
maintainers aren't necessarily familiar with the intended usage of every 
individual node when they have to resolve merge conflicts etc., so 
maintaining a straightforward consistent pattern is generally easier for 
everyone.

Thanks,
Robin.

      parent reply	other threads:[~2025-12-01 14:13 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-25  7:16 [PATCH V2 0/3] Add device tree support for NVIDIA Tegra CMDQV Ashish Mhetre
2025-11-25  7:16 ` [PATCH V2 1/3] iommu/arm-smmu-v3: Add device-tree support for CMDQV driver Ashish Mhetre
2025-11-25 17:25   ` Robin Murphy
2025-12-01 15:55     ` Ashish Mhetre
2025-11-25  7:16 ` [PATCH V2 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support Ashish Mhetre
2025-11-25  7:16 ` [PATCH V2 3/3] arm64: dts: nvidia: Add nodes for CMDQV Ashish Mhetre
2025-11-25 10:22   ` Jon Hunter
2025-12-01  9:36     ` Ashish Mhetre
2025-12-01 14:11       ` Thierry Reding
2025-12-01 15:54         ` Ashish Mhetre
2025-12-01 14:13       ` Robin Murphy [this message]

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