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From: Jon Hunter <jonathanh@nvidia.com>
To: Kartik Rajput <kkartik@nvidia.com>,
	thierry.reding@gmail.com, jirislaby@kernel.org,
	pshete@nvidia.com, chleroy@kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] soc/tegra: pmc: Add PMC support for Tegra410
Date: Wed, 25 Mar 2026 15:45:34 +0000	[thread overview]
Message-ID: <b6bae185-52cd-48bf-8638-53f68004f987@nvidia.com> (raw)
In-Reply-To: <20260324082847.550771-1-kkartik@nvidia.com>


On 24/03/2026 08:28, Kartik Rajput wrote:
> Tegra410 uses PMC driver only to retrieve system reset reason using PMC
> sysfs. Tegra410 uses ACPI to probe PMC, unlike device-tree boot it does
> not use the early initialisation sequence.
> 
> Add PMC support for Tegra410, which uses the PMC driver to retrieve
> the system reset reason via PMC sysfs.
> 
> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> ---
> Changes in v2:
> 	* Updated commit message.
> ---
>   drivers/soc/tegra/pmc.c | 128 ++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 128 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index a1a2966512d1..f17dcfd0aeae 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -11,6 +11,7 @@
>   
>   #define pr_fmt(fmt) "tegra-pmc: " fmt
>   
> +#include <linux/acpi.h>
>   #include <linux/arm-smccc.h>
>   #include <linux/clk.h>
>   #include <linux/clk-provider.h>
> @@ -3095,12 +3096,30 @@ static void tegra_pmc_reset_suspend_mode(void *data)
>   	pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
>   }
>   
> +static int tegra_pmc_acpi_probe(struct platform_device *pdev)
> +{
> +	pmc->soc = device_get_match_data(&pdev->dev);
> +	pmc->dev = &pdev->dev;
> +
> +	pmc->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(pmc->base))
> +		return PTR_ERR(pmc->base);
> +
> +	tegra_pmc_reset_sysfs_init(pmc);
> +	platform_set_drvdata(pdev, pmc);
> +
> +	return 0;
> +}
> +
>   static int tegra_pmc_probe(struct platform_device *pdev)
>   {
>   	void __iomem *base;
>   	struct resource *res;
>   	int err;
>   
> +	if (is_acpi_node(dev_fwnode(&pdev->dev)))
> +		return tegra_pmc_acpi_probe(pdev);
> +
>   	/*
>   	 * Early initialisation should have configured an initial
>   	 * register mapping and setup the soc data pointer. If these
> @@ -4615,6 +4634,108 @@ static const struct tegra_pmc_soc tegra264_pmc_soc = {
>   	.max_wake_vectors = 4,
>   };
>   
> +static const char * const tegra410_reset_sources[] = {
> +	"SYS_RESET_N",		/* 0x0 */
> +	"CSDC_RTC_XTAL",
> +	"VREFRO_POWER_BAD",
> +	"FMON_32K",
> +	"FMON_OSC",
> +	"POD_RTC",
> +	"POD_IO",
> +	"POD_PLUS_IO_SPLL",
> +	"POD_PLUS_IO_VMON",	/* 0x8 */
> +	"POD_PLUS_SOC",
> +	"VMON_PLUS_UV",
> +	"VMON_PLUS_OV",
> +	"FUSECRC_FAULT",
> +	"OSC_FAULT",
> +	"BPMP_BOOT_FAULT",
> +	"SCPM_BPMP_CORE_CLK",
> +	"SCPM_PSC_SE_CLK",	/* 0x10 */
> +	"VMON_SOC_MIN",
> +	"VMON_SOC_MAX",
> +	"NVJTAG_SEL_MONITOR",
> +	"L0_RST_REQ_N",
> +	"NV_THERM_FAULT",
> +	"PSC_SW",
> +	"POD_C2C_LPI_0",
> +	"POD_C2C_LPI_1",	/* 0x18 */
> +	"BPMP_FMON",
> +	"FMON_SPLL_OUT",
> +	"L1_RST_REQ_N",
> +	"OCP_RECOVERY",
> +	"AO_WDT_POR",
> +	"BPMP_WDT_POR",
> +	"RAS_WDT_POR",
> +	"TOP_0_WDT_POR",	/* 0x20 */
> +	"TOP_1_WDT_POR",
> +	"TOP_2_WDT_POR",
> +	"PSC_WDT_POR",
> +	"OOBHUB_WDT_POR",
> +	"MSS_SEQ_WDT_POR",
> +	"SW_MAIN",
> +	"L0L1_RST_OUT_N",
> +	"HSM",			/* 0x28 */
> +	"CSITE_SW",
> +	"AO_WDT_DBG",
> +	"BPMP_WDT_DBG",
> +	"RAS_WDT_DBG",
> +	"TOP_0_WDT_DBG",
> +	"TOP_1_WDT_DBG",
> +	"TOP_2_WDT_DBG",
> +	"PSC_WDT_DBG",		/* 0x30 */
> +	"TSC_0_WDT_DBG",
> +	"TSC_1_WDT_DBG",
> +	"OOBHUB_WDT_DBG",
> +	"MSS_SEQ_WDT_DBG",
> +	"L2_RST_REQ_N",
> +	"L2_RST_OUT_N",
> +	"SC7"
> +};
> +
> +static const struct tegra_pmc_regs tegra410_pmc_regs = {
> +	.rst_status = 0x8,
> +	.rst_source_shift = 0x2,
> +	.rst_source_mask = 0xfc,
> +	.rst_level_shift = 0x0,
> +	.rst_level_mask = 0x3,
> +};
> +
> +static const struct tegra_pmc_soc tegra410_pmc_soc = {
> +	.supports_core_domain = false,

Not needed since there are no powergates

> +	.num_powergates = 0,
> +	.powergates = NULL,
> +	.num_cpu_powergates = 0,
> +	.cpu_powergates = NULL,
> +	.has_tsense_reset = false,

Not needed as you have a different probe function.

> +	.has_gpu_clamps = false,

It should not be necessary to explicitly set this because this is only 
used if there are powergates.

> +	.needs_mbist_war = false,

Same with this.

> +	.has_impl_33v_pwr = false,

This is only needed for if you have IO pads.

> +	.maybe_tz_only = false,

Only used in early init and so also not needed.

> +	.num_io_pads = 0,
> +	.io_pads = NULL,
> +	.num_pin_descs = 0,
> +	.pin_descs = NULL,
> +	.regs = &tegra410_pmc_regs,
> +	.init = NULL,
> +	.setup_irq_polarity = NULL,
> +	.set_wake_filters = NULL,
> +	.irq_set_wake = NULL,
> +	.irq_set_type = NULL,
> +	.reset_sources = tegra410_reset_sources,
> +	.num_reset_sources = ARRAY_SIZE(tegra410_reset_sources),
> +	.reset_levels = tegra186_reset_levels,
> +	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
> +	.num_wake_events = 0,
> +	.wake_events = NULL,
> +	.max_wake_events = 0,
> +	.max_wake_vectors = 0,
> +	.pmc_clks_data = NULL,
> +	.num_pmc_clks = 0,
> +	.has_blink_output = false,

Not needed as there are no clocks.

> +	.has_single_mmio_aperture = false,

Not needed as you have a ACPI specific probe function.

In general, I think that we should only init things here and need to be 
explicitly initialised.

Jon

-- 
nvpublic


      reply	other threads:[~2026-03-25 15:45 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-24  8:28 [PATCH v2] soc/tegra: pmc: Add PMC support for Tegra410 Kartik Rajput
2026-03-25 15:45 ` Jon Hunter [this message]

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