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a="3247782" X-IronPort-AV: E=Sophos;i="6.27,210,1787036400"; d="scan'208";a="3247782" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2026 15:49:32 -0800 X-CSE-ConnectionGUID: u6GHNGKtRReKeINebfksyg== X-CSE-MsgGUID: yItJD5dmQG6m6BtvGQiJ8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,210,1787036400"; d="scan'208";a="8613663" Received: from jjgreens-desk24.amr.corp.intel.com (HELO [10.125.111.216]) ([10.125.111.216]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2026 15:49:30 -0800 Message-ID: Date: Thu, 12 Nov 2026 16:49:28 -0700 X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v17 08/19] cxl: Move cxl_rwsem into built-in code To: Srirangan Madhavan , Alison Schofield , Bjorn Helgaas , Davidlohr Bueso , Ira Weiny , Jonathan Cameron , Vishal Verma , linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Li Ming , Joshua Machauer , Alex Williamson , vsethi@nvidia.com, alwilliamson@nvidia.com, Sai Yashwanth Reddy Kancherla , Vishal Aslot , Manish Honap , Jiandi An , Richard Cheng , linux-tegra@vger.kernel.org References: <20261105185917.2667656-1-smadhavan@nvidia.com> <20261105185917.2667656-9-smadhavan@nvidia.com> From: Dave Jiang Content-Language: en-US In-Reply-To: <20261105185917.2667656-9-smadhavan@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/5/26 11:59 AM, Srirangan Madhavan wrote: > Keep the region and DPA locks available to built-in CXL state management > when cxl_core is modular. > > Signed-off-by: Srirangan Madhavan > Reviewed-by: Richard Cheng Reviewed-by: Dave Jiang > --- > drivers/cxl/core/Makefile | 2 +- > drivers/cxl/core/hdm.c | 5 ----- > drivers/cxl/core/hdm_state.c | 15 +++++++++++++++ > 3 files changed, 16 insertions(+), 6 deletions(-) > create mode 100644 drivers/cxl/core/hdm_state.c > > diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile > index 6703c1729396..9971efb237fb 100644 > --- a/drivers/cxl/core/Makefile > +++ b/drivers/cxl/core/Makefile > @@ -1,6 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > obj-$(CONFIG_CXL_BUS) += cxl_core.o > -obj-$(subst m,y,$(CONFIG_CXL_BUS)) += hdm_regs.o > +obj-$(subst m,y,$(CONFIG_CXL_BUS)) += hdm_regs.o hdm_state.o > obj-$(CONFIG_CXL_SUSPEND) += suspend.o > > ccflags-y += -I$(srctree)/drivers/cxl > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 5b5f5f22ea32..85f9abf58a42 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -17,11 +17,6 @@ > * for enumerating these registers and capabilities. > */ > > -struct cxl_rwsem cxl_rwsem = { > - .region = __RWSEM_INITIALIZER(cxl_rwsem.region), > - .dpa = __RWSEM_INITIALIZER(cxl_rwsem.dpa), > -}; > - > static int add_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld) > { > int rc; > diff --git a/drivers/cxl/core/hdm_state.c b/drivers/cxl/core/hdm_state.c > new file mode 100644 > index 000000000000..c9cc019902ef > --- /dev/null > +++ b/drivers/cxl/core/hdm_state.c > @@ -0,0 +1,15 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* Copyright (c) 2026 NVIDIA Corporation & Affiliates */ > +#include > +#include > + > +#include > + > +#include "cxl.h" > +#include "core.h" > + > +struct cxl_rwsem cxl_rwsem = { > + .region = __RWSEM_INITIALIZER(cxl_rwsem.region), > + .dpa = __RWSEM_INITIALIZER(cxl_rwsem.dpa), > +}; > +EXPORT_SYMBOL_FOR_MODULES(cxl_rwsem, "cxl_core");