From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [PATCH v6 3/8] usb: chipidea: Add support for Tegra20/30/114/124 Date: Wed, 6 Sep 2017 14:21:59 +0100 Message-ID: References: <2b091105e45234dca93051862e76e711acf482cc.1502879078.git.digetx@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <2b091105e45234dca93051862e76e711acf482cc.1502879078.git.digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Content-Language: en-US Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Dmitry Osipenko , Thierry Reding , Felipe Balbi , Greg Kroah-Hartman , Peter Chen , Stephen Warren Cc: Marc Dietrich , Nicolas Chauvet , =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 16/08/17 11:32, Dmitry Osipenko wrote: > From: Thierry Reding > > All of these Tegra SoC generations have a ChipIdea UDC IP block that can > be used for device mode communication with a host. Implement rudimentary > support that doesn't allow switching between host and device modes. > > Tested-by: Michał Mirosław > Signed-off-by: Thierry Reding > [digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: rebased patches and added DMA alignment quirk for Tegra20] > Signed-off-by: Dmitry Osipenko > Acked-by: Peter Chen Currently, I am seeing that system suspend on Tegra30/114/124 is broken on -next (looks like it broke starting with next-20170823). Bisect shows that is broke with this series and reverting this patch of top of tree does workaround the problem. Looking a bit deeper, it appears that the boards are hanging when the set_phcd() function is called in the tegra phy driver to disable the phy clock. This function is called by usb_phy_set_suspend() in the chipidea driver. Thierry, any thoughts? Cheers Jon -- nvpublic