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Miller" , Eric Dumazet , Jakub Kicinski , linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Marcin Wojtas , Maxime Coquelin , netdev@vger.kernel.org, Paolo Abeni , UNGLinuxDriver@microchip.com, "linux-tegra@vger.kernel.org" References: <05987b45-94b9-4744-a90d-9812cf3566d9@nvidia.com> <86fae995-1700-420b-8d84-33ab1e1f6353@nvidia.com> <203871c2-c673-4a98-a0a3-299d1cf71cf0@nvidia.com> <31731125-ab8f-48d9-bd6f-431d49431957@nvidia.com> From: Jon Hunter Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: LO2P265CA0503.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:13b::10) To SJ2PR12MB8784.namprd12.prod.outlook.com (2603:10b6:a03:4d0::11) Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB8784:EE_|SN7PR12MB6837:EE_ X-MS-Office365-Filtering-Correlation-Id: e0780930-e3f7-4ac7-eade-08dd564e04bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|10070799003|1800799024|7416014|366016; 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>>> mutex_lock(&priv->lock); >>> + phy_eee_rx_clock_stop(priv->dev->phydev, false); >>> + >>> stmmac_reset_queues_param(priv); >>> stmmac_free_tx_skbufs(priv); >>> @@ -7937,6 +7939,9 @@ int stmmac_resume(struct device *dev) >>> stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); >>> + phy_eee_rx_clock_stop(priv->dev->phydev, >>> + priv->phylink_config.eee_rx_clk_stop_enable); >>> + >>> stmmac_enable_all_queues(priv); >>> stmmac_enable_all_dma_irq(priv); >> >> >> Sorry for the delay, I have been testing various issues recently and needed >> a bit more time to test this. >> >> It turns out that what I had proposed last week does not work. I believe >> that with all the various debug/instrumentation I had added, I was again >> getting lucky. So when I tested again this week on top of vanilla v6.14-rc2, >> it did not work :-( >> >> However, what you are suggesting above, all by itself, is working. I have >> tested this on top of vanilla v6.14-rc2 and v6.14-rc4 and it is working >> reliably. I have also tested on some other boards that use the same stmmac >> driver (but use the Aquantia PHY) and I have not seen any issues. So this >> does fix the issue I am seeing. >> >> I know we are getting quite late in the rc for v6.14, but not sure if we >> could add this as a fix? > > The patch above was something of a hack, bypassing the layering, so I > would like to consider how this should be done properly. > > I'm still wondering whether the early call to phylink_resume() is > symptomatic of this same issue, or whether there is a PHY that needs > phy_start() to be called to output its clock even with link down that > we don't know about. > > The phylink_resume() call is relevant to this because I'd like to put: > > phy_eee_rx_clock_stop(priv->dev->phydev, > priv->phylink_config.eee_rx_clk_stop_enable); > > in there to ensure that the PHY is correctly configured for clock-stop, > but given stmmac's placement that wouldn't work. > > I'm then thinking of phylink_pre_resume() to disable the EEE clock-stop > at the PHY. > > I think the only thing we could do is try solving this problem as per > above and see what the fall-out from it is. I don't get the impression > that stmmac users are particularly active at testing patches though, so > it may take months to get breakage reports. We can ask Furong to test as he seems to active and making changes, but otherwise I am not sure how well it is being tested across various devices. On the other hand, it feels like there are still lingering issues like this with the driver and so I would hope this is moving in the right direction. Let me know if you have a patch you want me to test and I will run in on our Tegra186, Tegra194 and Tegra234 devices that all use this. Thanks Jon -- nvpublic