From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bitan Biswas Subject: Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check Date: Fri, 14 Jun 2019 02:50:27 -0700 Message-ID: References: <1560250274-18499-1-git-send-email-bbiswas@nvidia.com> <1560250274-18499-6-git-send-email-bbiswas@nvidia.com> <42ce2523-dab9-0cdf-e8ff-42631dd161b7@gmail.com> <78140337-dca0-e340-a501-9e37eca6cc87@nvidia.com> <9cb7123a-1ebd-3a93-60dc-c8f57f60270b@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <9cb7123a-1ebd-3a93-60dc-c8f57f60270b@gmail.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Dmitry Osipenko , Laxman Dewangan , Thierry Reding , Jonathan Hunter , linux-i2c@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Rosin , Wolfram Sang Cc: Shardar Mohammed , Sowjanya Komatineni , Mantravadi Karthik List-Id: linux-tegra@vger.kernel.org On 6/13/19 5:28 AM, Dmitry Osipenko wrote: > 13.06.2019 14:30, Bitan Biswas =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >> >> >> On 6/12/19 7:30 AM, Dmitry Osipenko wrote: >>> 11.06.2019 13:51, Bitan Biswas =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>> Fix expression for residual bytes(less than word) transfer >>>> in I2C PIO mode RX/TX. >>>> >>>> Signed-off-by: Bitan Biswas >>>> --- >>> >>> [snip] >>> >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Update state befor= e writing to FIFO.=C2=A0 If this casues us >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Update state befor= e writing to FIFO.=C2=A0 If this causes us >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * to fin= ish writing all bytes (AKA buf_remaining goes to >>>> 0) we >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * have a= potential for an interrupt (PACKET_XFER_COMPLETE is >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * not maskable).=C2= =A0 We need to make sure that the isr sees >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * buf_remaining as 0= and doesn't call us back re-entrantly. >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * not maskable). >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 buf_remaining = -=3D words_to_transfer * BYTES_PER_FIFO_WORD; >>> >>> Looks like the comment could be removed altogether because it doesn't >>> make sense since interrupt handler is under xfer_lock which is kept >>> locked during of tegra_i2c_xfer_msg(). >> I would push a separate patch to remove this comment because of >> xfer_lock in ISR now. >> >>> >>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable", >>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does? >>> >> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips >> newer than Tegra30 allows one to not see interrupt after Packet transfer >> complete. With the xfer_lock in ISR the scenario discussed in comment >> can be ignored. >=20 > Also note that xfer_lock could be removed and replaced with a just > irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care > about IRQ not firing during of the preparation process. This should need sufficient testing hence let us do it in a different=20 series. >=20 > It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all > IRQ's could be simply unmasked during the driver's probe, in that case > it may worth to add a kind of "in-progress" flag to catch erroneous > interrupts. >=20 TX interrupt needs special handling if this change is done. Hence I=20 think it should be taken up after sufficient testing in a separate patch. -regards, Bitan