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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?rw6sOeejxWubQlYyZceNDsK+FNCbUkhFgaWk5TvIYmGrC54d14md6F8pg98J?= =?us-ascii?Q?/LWzidGSb1SPZWjY4r8PURiG8+4EN7+Kzudm7NkLvWj+wYFwS9bGL2ZW9e8K?= =?us-ascii?Q?ANG26XjdmlCDwfWebJlUteDvhrBCXJ4XK9o7tESwJXPc7L3GjdD+GQYsGefn?= =?us-ascii?Q?LWiApS66LWSQO78C38co2MkGbYn1GU0se2k8O9dEJzEOUDN/rmE+ZzwMfklW?= =?us-ascii?Q?hZCXHYwZ+oBxBJwpwBTVsgMfCoBMkdh9XbPOQNkmFDRdLLpMP9sRCttUsBLP?= =?us-ascii?Q?1x8/tH8rYs/FQxiYzIHg/MHy8jn+sSxTxhR/6j8Iv9UXLqdXXmPpzaMn6Yn5?= =?us-ascii?Q?kQR+20HfLdcqmUv8xCoMK//G6FFOSfKDzyCowWcCrTL/wZAIfoqSFa9kUmyW?= =?us-ascii?Q?4IRPwOFmLezWe75G8lwv83Eg+pxgwQv9vkEB0u2aOtx5yeSFaDH9vVyWxjyp?= =?us-ascii?Q?C3xUSanErtRFH3+6jqrpT5Fd7ZlWYur8NNuK0I1kLex1SYbSOZ58sYshnazt?= =?us-ascii?Q?/rkFtIPqczIQuobgbM7hB2eLv0BpK1hTLCTMGFi0cdKFsUNjWL8ws/zZpWBW?= =?us-ascii?Q?w9pPSwyo11vtqg7PK0qwmR3KQ2DlOqThmMsi1UHRiwo4qjEc/OP0lpj+1XRs?= =?us-ascii?Q?f6Cc6xwF8VwJuLGYywu7ejVvnOWlm/goCiPBA4yFQ0jUAwt5EFIJwYdXslbj?= =?us-ascii?Q?WXbZ3xhp6OJlLVxFb2hLkUaFX5l8tkcBPvG5VDPZrixWmUlrxgT+LYqg/CaB?= =?us-ascii?Q?00+sf/WedrnBM0T2cXs+hgxZJVdiwRnm+yEw1hQeWmJ+QtPH9M90phHMf1GE?= =?us-ascii?Q?ZQV3/CxGh8EhIj9ikPvDmo3CeQKyHBBFnFki7mCiKyWjNl3AsX3IDjPC3w5I?= =?us-ascii?Q?1SC+wHG76IfsCE0aHX1nop7GSmpy6wA33SDvLvs0gYLhNQehQUciwS6ru4Ik?= =?us-ascii?Q?5LAJhlr5Htx4iMU/qcSkourARH4GuySupqr5FuaG603s22X8MfAhFzf4Mmuy?= =?us-ascii?Q?bBS5xBUHIyNBHsy79x3U9mm08QvvgFTQGLU/mPSCRxIzxDzhgEnG9J/cpPov?= =?us-ascii?Q?SbukHbAz7fwoFr6GzcMB7TOwM9QtHxV/M5sB0VUuyXMwo0Zzlyxz11LCzyK7?= =?us-ascii?Q?eGdxnPzxvUi+OJMeBh7cU7Ahi5+6vWdw8w6Bdsb1X28Slc4b9nm7MwrY6JHp?= =?us-ascii?Q?vZ1U1GZ1baZbCtD+SKDNCRd9qp5+qlJ8AfXv7DxXLZhp5qy4qgFHpidLINru?= =?us-ascii?Q?FLnvu2QB8kps7fhuQYEaJRt3W1YbT4BQETR693v0mHbE1R5TSHn9elvtpuV2?= =?us-ascii?Q?QwsCqftHTxHs3nboAO/FeiK5a5IEaSMr7XWCd5pJsjgguhbKxcPVmdaFxwRx?= =?us-ascii?Q?XOPQQL3SJzScqYSxf5EBNQMipyn7H30Txz79rQAdb8CAqUipXB+GGX80uy9n?= =?us-ascii?Q?9VZyfu9Skqwu4wNfi9ABh0xIpyxuD/Jvf3NUCg3HRAb4u/J2qi7kVK/a3NsM?= =?us-ascii?Q?qzgnSfj1SeK0DUMJE7P6fFw1qkrblEq9eTP3beTLSdft64HO6wmFt/L+CXa2?= =?us-ascii?Q?7q6kIbMnzfDfc0dFYpfBOjL0zqIRsRDvibXfpKf5bNcbxccck35BtRkK/zll?= =?us-ascii?Q?oUDopPLBVCmk53We3nuVUW0=3D?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8080d6d4-5821-4cd7-ce84-08ddfba678fa X-MS-Exchange-CrossTenant-AuthSource: MW4PR01MB6228.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2025 20:10:57.0815 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xqd4iwoKbC5KA1HO3L9wxESHCarm0eziM9zNJWizwX9sYRmQQUkhFAFqqvNTP6wehMJliPPKXvT3n/L4jqIsQRNFSQd87auABT9kWxEOqT7l5Mj5GZIKYx/h3s+hTJBo X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR01MB8802 On Tue, 23 Sep 2025, Besar Wicaksono wrote: > Support NVIDIA PMU that utilizes the optional event filter2 register. > > Signed-off-by: Besar Wicaksono Reviewed-by: Ilkka Koskinen > --- > drivers/perf/arm_cspmu/nvidia_cspmu.c | 176 +++++++++++++++++++------- > 1 file changed, 133 insertions(+), 43 deletions(-) > > diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu/nvidia_cspmu.c > index ac91dc46501d..e06a06d3407b 100644 > --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c > +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c > @@ -40,10 +40,21 @@ > > struct nv_cspmu_ctx { > const char *name; > - u32 filter_mask; > - u32 filter_default_val; > + > struct attribute **event_attr; > struct attribute **format_attr; > + > + u32 filter_mask; > + u32 filter_default_val; > + u32 filter2_mask; > + u32 filter2_default_val; > + > + u32 (*get_filter)(const struct perf_event *event); > + u32 (*get_filter2)(const struct perf_event *event); > + > + void *data; > + > + int (*init_data)(struct arm_cspmu *cspmu); > }; > > static struct attribute *scf_pmu_event_attrs[] = { > @@ -144,6 +155,7 @@ static struct attribute *cnvlink_pmu_format_attrs[] = { > static struct attribute *generic_pmu_format_attrs[] = { > ARM_CSPMU_FORMAT_EVENT_ATTR, > ARM_CSPMU_FORMAT_FILTER_ATTR, > + ARM_CSPMU_FORMAT_FILTER2_ATTR, > NULL, > }; > > @@ -184,13 +196,36 @@ static u32 nv_cspmu_event_filter(const struct perf_event *event) > return filter_val; > } > > +static u32 nv_cspmu_event_filter2(const struct perf_event *event) > +{ > + const struct nv_cspmu_ctx *ctx = > + to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); > + > + const u32 filter_val = event->attr.config2 & ctx->filter2_mask; > + > + if (filter_val == 0) > + return ctx->filter2_default_val; > + > + return filter_val; > +} > + > static void nv_cspmu_set_ev_filter(struct arm_cspmu *cspmu, > const struct perf_event *event) > { > - u32 filter = nv_cspmu_event_filter(event); > - u32 offset = PMEVFILTR + (4 * event->hw.idx); > + u32 filter, offset; > + const struct nv_cspmu_ctx *ctx = > + to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); > + offset = 4 * event->hw.idx; > > - writel(filter, cspmu->base0 + offset); > + if (ctx->get_filter) { > + filter = ctx->get_filter(event); > + writel(filter, cspmu->base0 + PMEVFILTR + offset); > + } > + > + if (ctx->get_filter2) { > + filter = ctx->get_filter2(event); > + writel(filter, cspmu->base0 + PMEVFILT2R + offset); > + } > } > > static void nv_cspmu_set_cc_filter(struct arm_cspmu *cspmu, > @@ -210,74 +245,120 @@ enum nv_cspmu_name_fmt { > struct nv_cspmu_match { > u32 prodid; > u32 prodid_mask; > - u64 filter_mask; > - u32 filter_default_val; > const char *name_pattern; > enum nv_cspmu_name_fmt name_fmt; > - struct attribute **event_attr; > - struct attribute **format_attr; > + struct nv_cspmu_ctx template_ctx; > + struct arm_cspmu_impl_ops ops; > }; > > static const struct nv_cspmu_match nv_cspmu_match[] = { > { > .prodid = 0x10300000, > .prodid_mask = NV_PRODID_MASK, > - .filter_mask = NV_PCIE_FILTER_ID_MASK, > - .filter_default_val = NV_PCIE_FILTER_ID_MASK, > .name_pattern = "nvidia_pcie_pmu_%u", > .name_fmt = NAME_FMT_SOCKET, > - .event_attr = mcf_pmu_event_attrs, > - .format_attr = pcie_pmu_format_attrs > + .template_ctx = { > + .event_attr = mcf_pmu_event_attrs, > + .format_attr = pcie_pmu_format_attrs, > + .filter_mask = NV_PCIE_FILTER_ID_MASK, > + .filter_default_val = NV_PCIE_FILTER_ID_MASK, > + .filter2_mask = 0x0, > + .filter2_default_val = 0x0, > + .get_filter = nv_cspmu_event_filter, > + .get_filter2 = NULL, > + .data = NULL, > + .init_data = NULL > + }, > }, > { > .prodid = 0x10400000, > .prodid_mask = NV_PRODID_MASK, > - .filter_mask = NV_NVL_C2C_FILTER_ID_MASK, > - .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK, > .name_pattern = "nvidia_nvlink_c2c1_pmu_%u", > .name_fmt = NAME_FMT_SOCKET, > - .event_attr = mcf_pmu_event_attrs, > - .format_attr = nvlink_c2c_pmu_format_attrs > + .template_ctx = { > + .event_attr = mcf_pmu_event_attrs, > + .format_attr = nvlink_c2c_pmu_format_attrs, > + .filter_mask = NV_NVL_C2C_FILTER_ID_MASK, > + .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK, > + .filter2_mask = 0x0, > + .filter2_default_val = 0x0, > + .get_filter = nv_cspmu_event_filter, > + .get_filter2 = NULL, > + .data = NULL, > + .init_data = NULL > + }, > }, > { > .prodid = 0x10500000, > .prodid_mask = NV_PRODID_MASK, > - .filter_mask = NV_NVL_C2C_FILTER_ID_MASK, > - .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK, > .name_pattern = "nvidia_nvlink_c2c0_pmu_%u", > .name_fmt = NAME_FMT_SOCKET, > - .event_attr = mcf_pmu_event_attrs, > - .format_attr = nvlink_c2c_pmu_format_attrs > + .template_ctx = { > + .event_attr = mcf_pmu_event_attrs, > + .format_attr = nvlink_c2c_pmu_format_attrs, > + .filter_mask = NV_NVL_C2C_FILTER_ID_MASK, > + .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK, > + .filter2_mask = 0x0, > + .filter2_default_val = 0x0, > + .get_filter = nv_cspmu_event_filter, > + .get_filter2 = NULL, > + .data = NULL, > + .init_data = NULL > + }, > }, > { > .prodid = 0x10600000, > .prodid_mask = NV_PRODID_MASK, > - .filter_mask = NV_CNVL_FILTER_ID_MASK, > - .filter_default_val = NV_CNVL_FILTER_ID_MASK, > .name_pattern = "nvidia_cnvlink_pmu_%u", > .name_fmt = NAME_FMT_SOCKET, > - .event_attr = mcf_pmu_event_attrs, > - .format_attr = cnvlink_pmu_format_attrs > + .template_ctx = { > + .event_attr = mcf_pmu_event_attrs, > + .format_attr = cnvlink_pmu_format_attrs, > + .filter_mask = NV_CNVL_FILTER_ID_MASK, > + .filter_default_val = NV_CNVL_FILTER_ID_MASK, > + .filter2_mask = 0x0, > + .filter2_default_val = 0x0, > + .get_filter = nv_cspmu_event_filter, > + .get_filter2 = NULL, > + .data = NULL, > + .init_data = NULL > + }, > }, > { > .prodid = 0x2CF00000, > .prodid_mask = NV_PRODID_MASK, > - .filter_mask = 0x0, > - .filter_default_val = 0x0, > .name_pattern = "nvidia_scf_pmu_%u", > .name_fmt = NAME_FMT_SOCKET, > - .event_attr = scf_pmu_event_attrs, > - .format_attr = scf_pmu_format_attrs > + .template_ctx = { > + .event_attr = scf_pmu_event_attrs, > + .format_attr = scf_pmu_format_attrs, > + .filter_mask = 0x0, > + .filter_default_val = 0x0, > + .filter2_mask = 0x0, > + .filter2_default_val = 0x0, > + .get_filter = nv_cspmu_event_filter, > + .get_filter2 = NULL, > + .data = NULL, > + .init_data = NULL > + }, > }, > { > .prodid = 0, > .prodid_mask = 0, > - .filter_mask = NV_GENERIC_FILTER_ID_MASK, > - .filter_default_val = NV_GENERIC_FILTER_ID_MASK, > .name_pattern = "nvidia_uncore_pmu_%u", > .name_fmt = NAME_FMT_GENERIC, > - .event_attr = generic_pmu_event_attrs, > - .format_attr = generic_pmu_format_attrs > + .template_ctx = { > + .event_attr = generic_pmu_event_attrs, > + .format_attr = generic_pmu_format_attrs, > + .filter_mask = NV_GENERIC_FILTER_ID_MASK, > + .filter_default_val = NV_GENERIC_FILTER_ID_MASK, > + .filter2_mask = NV_GENERIC_FILTER_ID_MASK, > + .filter2_default_val = NV_GENERIC_FILTER_ID_MASK, > + .get_filter = nv_cspmu_event_filter, > + .get_filter2 = nv_cspmu_event_filter2, > + .data = NULL, > + .init_data = NULL > + }, > }, > }; > > @@ -310,6 +391,14 @@ static char *nv_cspmu_format_name(const struct arm_cspmu *cspmu, > return name; > } > > +#define SET_OP(name, impl, match, default_op) \ > + do { \ > + if (match->ops.name) \ > + impl->name = match->ops.name; \ > + else if (default_op != NULL) \ > + impl->name = default_op; \ > + } while (false) > + > static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) > { > struct nv_cspmu_ctx *ctx; > @@ -330,20 +419,21 @@ static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) > break; > } > > - ctx->name = nv_cspmu_format_name(cspmu, match); > - ctx->filter_mask = match->filter_mask; > - ctx->filter_default_val = match->filter_default_val; > - ctx->event_attr = match->event_attr; > - ctx->format_attr = match->format_attr; > + /* Initialize the context with the matched template. */ > + memcpy(ctx, &match->template_ctx, sizeof(struct nv_cspmu_ctx)); > + ctx->name = nv_cspmu_format_name(cspmu, match); > > cspmu->impl.ctx = ctx; > > /* NVIDIA specific callbacks. */ > - impl_ops->set_cc_filter = nv_cspmu_set_cc_filter; > - impl_ops->set_ev_filter = nv_cspmu_set_ev_filter; > - impl_ops->get_event_attrs = nv_cspmu_get_event_attrs; > - impl_ops->get_format_attrs = nv_cspmu_get_format_attrs; > - impl_ops->get_name = nv_cspmu_get_name; > + SET_OP(set_cc_filter, impl_ops, match, nv_cspmu_set_cc_filter); > + SET_OP(set_ev_filter, impl_ops, match, nv_cspmu_set_ev_filter); > + SET_OP(get_event_attrs, impl_ops, match, nv_cspmu_get_event_attrs); > + SET_OP(get_format_attrs, impl_ops, match, nv_cspmu_get_format_attrs); > + SET_OP(get_name, impl_ops, match, nv_cspmu_get_name); > + > + if (ctx->init_data) > + return ctx->init_data(cspmu); > > return 0; > } > -- > 2.50.1 > >