* Re: [PATCH 1/4] [ARM] tegra: Add support for Tegra USB PHYs
From: Matthieu CASTET @ 2011-02-09 8:44 UTC (permalink / raw)
To: Benoit Goby
Cc: David Brownell, Greg Kroah-Hartman,
linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Robert Morell,
Olof Johansson, Erik Gilling,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1297228927-23497-2-git-send-email-benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
Hello,
Benoit Goby a écrit :
> Interface used by Tegra's gadget driver and ehci driver
> to power on and configure the USB PHYs.
>
> + */
> +
> +#include <linux/resource.h>
> +#include <linux/delay.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/gpio.h>
> +#include <asm/mach-types.h>
> +#include <mach/usb_phy.h>
> +#include <mach/iomap.h>
> +
> +#define USB_USBSTS 0x144
> +#define USB_USBSTS_PCI (1 << 2)
> +
> +#define ULPI_VIEWPORT 0x170
It look like your core is a arc/chipidea/mips one that is already used
on other product (msm) for example.
Can't you merge with them ?
for example
> +static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
> +{
> + unsigned long timeout = 2000;
> + do {
> + if ((readl(reg) & mask) == result)
> + return 0;
> + udelay(1);
> + timeout--;
> + } while (timeout);
> + return -1;
> +}
> +static void ulpi_viewport_write(struct tegra_usb_phy *phy, u8 addr,
u8 data)
> +{
> + unsigned long val;
> + void __iomem *base = phy->regs;
> +
> + val = ULPI_RUN | ULPI_RD_RW_WRITE | ULPI_PORT(0);
> + val |= ULPI_ADDR(addr) | ULPI_DATA_WR(data);
> + writel(val, base + ULPI_VIEWPORT);
> +
> + if (utmi_wait_register(base + ULPI_VIEWPORT, ULPI_RUN, 0))
> + pr_err("%s: timeout accessing ulpi phy\n", __func__);
> +}
look very similar to what is in drivers/usb/otg/msm72k_otg.c
+static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+{
+ struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
+ int cnt = 0;
+
+ /* initiate write operation */
+ writel(ULPI_RUN | ULPI_WRITE |
+ ULPI_ADDR(reg) | ULPI_DATA(val),
+ USB_ULPI_VIEWPORT);
+
+ /* wait for completion */
+ while (cnt < ULPI_IO_TIMEOUT_USEC) {
+ if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
+ break;
+ udelay(1);
+ cnt++;
+ }
+
+ if (cnt >= ULPI_IO_TIMEOUT_USEC) {
+ dev_err(otg->dev, "ulpi_write: timeout\n");
+ return -ETIMEDOUT;
+ }
+ return 0;
+}
Matthieu
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* Re: [PATCH 1/4] [ARM] tegra: Add support for Tegra USB PHYs
From: rmorell-DDmLM1+adcrQT0dZR+AlfA @ 2011-02-09 7:05 UTC (permalink / raw)
To: Benoit Goby
Cc: David Brownell, Greg Kroah-Hartman,
linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Olof Johansson,
Erik Gilling, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1297228927-23497-2-git-send-email-benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
On Tue, Feb 08, 2011 at 09:22:04PM -0800, Benoit Goby wrote:
> Interface used by Tegra's gadget driver and ehci driver
> to power on and configure the USB PHYs.
>
> Signed-off-by: Benoit Goby <benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
> ---
For some reason this patch (along with patch 3) appears to contain
spaces as indentation (no hard tabs), although patches 2 and 4 in this
series have the correct tabs.
[...]
> +#define USB_USBSTS 0x144
> +#define USB_USBSTS_PCI (1 << 2)
This doesn't appear to be used?
[...]
> +static DEFINE_SPINLOCK(utmip_pad_lock);
> +static int utmip_pad_count;
> +
> +static const int udc_freq_table[] = {
> + 12000000,
> + 13000000,
> + 19200000,
> + 26000000,
> +};
> +
> +static const u8 udc_delay_table[][4] = {
> + /* ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
> + {0x02, 0x2F, 0x04, 0x76}, /* 12 MHz */
> + {0x02, 0x33, 0x05, 0x7F}, /* 13 MHz */
> + {0x03, 0x4B, 0x06, 0xBB}, /* 19.2 MHz */
> + {0x04, 0x66, 0x09, 0xFE}, /* 26 Mhz */
> +};
Use an array of structs here? Writing
"UTMIP_PLL_ACTIVE_DLY_COUNT(udc_delay_table[phy->freq_sel][2])" below is a
lot less clear and more prone to bugs than, say,
"UTMIP_PLL_ACTIVE_DLY_COUNT(udc_delay_table[phy->freq_sel].active_dly)".
It'd be even better to combine all three tables into one; something
like:
static const struct udc_... udc_table[] = {
{ .freq = 12000000,
.delay = {
.enable = 0x02,
.stable = 0x2f,
.active = 0x04
},
.xtal_freq_cnt = 0x76,
.debounce = 0x7530,
},
[... etc]
};
[...]
> +static int utmip_pad_open(struct tegra_usb_phy *phy)
> +{
> + phy->pad_clk = clk_get_sys("utmip-pad", NULL);
> + if (IS_ERR(phy->pad_clk)) {
> + pr_err("%s: can't get utmip pad clock\n", __func__);
> + return -1;
return PTR_ERR(phy->pad_clk);
> + }
> +
> + if (phy->instance == 0) {
> + phy->pad_regs = phy->regs;
> + } else {
> + phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
> + if (!phy->pad_regs) {
> + pr_err("%s: can't remap usb registers\n", __func__);
> + clk_put(phy->pad_clk);
> + return -ENOMEM;
> + }
> + }
> + return 0;
> +}
[...]
> +static int utmip_pad_power_off(struct tegra_usb_phy *phy)
> +{
> + unsigned long val, flags;
> + void __iomem *base = phy->pad_regs;
> +
> + if (!utmip_pad_count) {
> + pr_err("%s: utmip pad already powered off\n", __func__);
> + return -1;
return -EINVAL?
> + }
> +
> + clk_enable(phy->pad_clk);
> +
> + spin_lock_irqsave(&utmip_pad_lock, flags);
> +
> + if (--utmip_pad_count == 0) {
> + val = readl(base + UTMIP_BIAS_CFG0);
> + val |= UTMIP_OTGPD | UTMIP_BIASPD;
> + writel(val, base + UTMIP_BIAS_CFG0);
> + }
> +
> + spin_unlock_irqrestore(&utmip_pad_lock, flags);
> +
> + clk_disable(phy->pad_clk);
> +
> + return 0;
> +}
> +
[...]
> +static void ulpi_phy_power_on(struct tegra_usb_phy *phy)
> +{
> + unsigned long val;
> + void __iomem *base = phy->regs;
> + struct tegra_ulpi_config *config = phy->config;
> +
> + gpio_direction_output(config->reset_gpio, 0);
> + msleep(5);
> + gpio_direction_output(config->reset_gpio, 1);
> +
> + clk_enable(phy->clk);
> + msleep(1);
This msleep seems excessive. Does it take that long for the clock to
settle?
> +
> + val = readl(base + USB_SUSP_CTRL);
> + val |= UHSIC_RESET;
> + writel(val, base + USB_SUSP_CTRL);
> +
> + val = readl(base + ULPI_TIMING_CTRL_0);
> + val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
> + writel(val, base + ULPI_TIMING_CTRL_0);
> +
> + val = readl(base + USB_SUSP_CTRL);
> + val |= ULPI_PHY_ENABLE;
> + writel(val, base + USB_SUSP_CTRL);
> +
> + val = 0;
> + writel(val, base + ULPI_TIMING_CTRL_1);
> +
> + val |= ULPI_DATA_TRIMMER_SEL(4);
> + val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
> + val |= ULPI_DIR_TRIMMER_SEL(4);
> + writel(val, base + ULPI_TIMING_CTRL_1);
> + udelay(10);
> +
> + val |= ULPI_DATA_TRIMMER_LOAD;
> + val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
> + val |= ULPI_DIR_TRIMMER_LOAD;
> + writel(val, base + ULPI_TIMING_CTRL_1);
> +
> + val = ULPI_WAKEUP | ULPI_RD_RW_WRITE | ULPI_PORT(0);
> + writel(val, base + ULPI_VIEWPORT);
> +
> + if (utmi_wait_register(base + ULPI_VIEWPORT, ULPI_WAKEUP, 0)) {
> + pr_err("%s: timeout waiting for ulpi phy wakeup\n", __func__);
> + return;
Why does this function return void if it can fail?
tegra_usb_phy_power_on() can propagate the error.
> + }
> +
> + /* Fix VbusInvalid due to floating VBUS */
> + ulpi_viewport_write(phy, 0x08, 0x40);
> + ulpi_viewport_write(phy, 0x0B, 0x80);
> +
> + val = readl(base + USB_PORTSC1);
> + val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
> + writel(val, base + USB_PORTSC1);
> +
> + val = readl(base + USB_SUSP_CTRL);
> + val |= USB_SUSP_CLR;
> + writel(val, base + USB_SUSP_CTRL);
> + udelay(100);
> +
> + val = readl(base + USB_SUSP_CTRL);
> + val &= ~USB_SUSP_CLR;
> + writel(val, base + USB_SUSP_CTRL);
> +}
[...]
> +struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
> + void *config, enum tegra_usb_phy_mode phy_mode)
> +{
> + struct tegra_usb_phy *phy;
> + struct tegra_ulpi_config *ulpi_config;
> + unsigned long parent_rate;
> + int freq_sel;
> + int err;
> +
> + phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
> + if (!phy)
> + return ERR_PTR(-ENOMEM);
> +
> + phy->instance = instance;
> + phy->regs = regs;
> + phy->config = config;
> + phy->mode = phy_mode;
> +
> + if (!phy->config) {
> + if (instance == 1) {
Instead of all of the (instance == 1) checks here and below (I count
eleven separate places this is checked), it might be more readable to
have a macro or static inline function such as bool phy_is_ulpi(phy).
> + pr_err("%s: ulpi phy configuration missing", __func__);
> + err = -EINVAL;
> + goto err0;
> + } else {
> + phy->config = &utmip_default[instance];
> + }
> + }
> +
> + phy->pll_u = clk_get_sys(NULL, "pll_u");
> + if (IS_ERR(phy->pll_u)) {
> + pr_err("Can't get pll_u clock\n");
> + err = PTR_ERR(phy->pll_u);
> + goto err0;
> + }
> + clk_enable(phy->pll_u);
> +
> + parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
> + for (freq_sel = 0; freq_sel < ARRAY_SIZE(udc_freq_table); freq_sel++) {
> + if (udc_freq_table[freq_sel] == parent_rate)
> + break;
> + }
> + if (freq_sel == ARRAY_SIZE(udc_freq_table)) {
> + pr_err("invalid pll_u parent rate %ld\n", parent_rate);
> + err = -EINVAL;
> + goto err1;
> + }
> + phy->freq_sel = freq_sel;
> +
> + if (phy->instance == 1) {
> + ulpi_config = config;
> + phy->clk = clk_get_sys(NULL, ulpi_config->clk);
> + if (IS_ERR(phy->clk)) {
> + pr_err("%s: can't get ulpi clock\n", __func__);
> + err = -ENXIO;
> + goto err1;
> + }
> + tegra_gpio_enable(ulpi_config->reset_gpio);
> + gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
> + gpio_direction_output(ulpi_config->reset_gpio, 0);
> + } else {
> + err = utmip_pad_open(phy);
> + if (err < 0)
> + goto err1;
> + }
> +
> + return phy;
> +
> +err1:
> + clk_disable(phy->pll_u);
> + clk_put(phy->pll_u);
> +err0:
> + kfree(phy);
> + return ERR_PTR(err);
> +}
[...]
The rest seems okay.
> --
> 1.7.3.1
>
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^ permalink raw reply
* [PATCH 4/4] USB: ehci: tegra: Align DMA transfers to 32 bytes
From: Benoit Goby @ 2011-02-09 5:22 UTC (permalink / raw)
To: David Brownell, Greg Kroah-Hartman,
linux-usb-u79uwXL29TY76Z2rM5mHXA
Cc: Benoit Goby, Olof Johansson, Erik Gilling,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Robert Morell
In-Reply-To: <1297228927-23497-1-git-send-email-benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
From: Robert Morell <rmorell-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The Tegra2 USB controller doesn't properly deal with misaligned DMA
buffers, causing corruption. This is especially prevalent with USB
network adapters, where skbuff alignment is often in the middle of a
4-byte dword.
To avoid this, allocate a temporary buffer for the DMA if the provided
buffer isn't sufficiently aligned.
Signed-off-by: Robert Morell <rmorell-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Benoit Goby <benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
---
drivers/usb/host/ehci-tegra.c | 90 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 90 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 24783ca..6d2d247 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -32,6 +32,8 @@
#define TEGRA_USB_USBMODE_HOST (3 << 0)
#define TEGRA_USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
+#define TEGRA_USB_DMA_ALIGN 32
+
struct tegra_ehci_hcd {
struct ehci_hcd *ehci;
struct tegra_usb_phy *phy;
@@ -423,6 +425,92 @@ static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
}
#endif
+struct temp_buffer {
+ void *kmalloc_ptr;
+ void *old_xfer_buffer;
+ u8 data[0];
+};
+
+static void free_temp_buffer(struct urb *urb)
+{
+ enum dma_data_direction dir;
+ struct temp_buffer *temp;
+
+ if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
+ return;
+
+ dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+ temp = container_of(urb->transfer_buffer, struct temp_buffer,
+ data);
+
+ if (dir == DMA_FROM_DEVICE)
+ memcpy(temp->old_xfer_buffer, temp->data,
+ urb->transfer_buffer_length);
+ urb->transfer_buffer = temp->old_xfer_buffer;
+ kfree(temp->kmalloc_ptr);
+
+ urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
+}
+
+static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
+{
+ enum dma_data_direction dir;
+ struct temp_buffer *temp, *kmalloc_ptr;
+ size_t kmalloc_size;
+
+ if (urb->num_sgs || urb->sg ||
+ urb->transfer_buffer_length == 0 ||
+ !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
+ return 0;
+
+ dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+ /* Allocate a buffer with enough padding for alignment */
+ kmalloc_size = urb->transfer_buffer_length +
+ sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1;
+
+ kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
+ if (!kmalloc_ptr)
+ return -ENOMEM;
+
+ /* Position our struct temp_buffer such that data is aligned */
+ temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
+
+ temp->kmalloc_ptr = kmalloc_ptr;
+ temp->old_xfer_buffer = urb->transfer_buffer;
+ if (dir == DMA_TO_DEVICE)
+ memcpy(temp->data, urb->transfer_buffer,
+ urb->transfer_buffer_length);
+ urb->transfer_buffer = temp->data;
+
+ urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
+
+ return 0;
+}
+
+static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
+ gfp_t mem_flags)
+{
+ int ret;
+
+ ret = alloc_temp_buffer(urb, mem_flags);
+ if (ret)
+ return ret;
+
+ ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
+ if (ret)
+ free_temp_buffer(urb);
+
+ return ret;
+}
+
+static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
+{
+ usb_hcd_unmap_urb_for_dma(hcd, urb);
+ free_temp_buffer(urb);
+}
+
static const struct hc_driver tegra_ehci_hc_driver = {
.description = hcd_name,
.product_desc = "Tegra EHCI Host Controller",
@@ -438,6 +526,8 @@ static const struct hc_driver tegra_ehci_hc_driver = {
.shutdown = tegra_ehci_shutdown,
.urb_enqueue = ehci_urb_enqueue,
.urb_dequeue = ehci_urb_dequeue,
+ .map_urb_for_dma = tegra_ehci_map_urb_for_dma,
+ .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma,
.endpoint_disable = ehci_endpoint_disable,
.endpoint_reset = ehci_endpoint_reset,
.get_frame_number = ehci_get_frame,
--
1.7.3.1
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^ permalink raw reply related
* [PATCH 3/4] usb: host: Add EHCI driver for NVIDIA Tegra SoCs
From: Benoit Goby @ 2011-02-09 5:22 UTC (permalink / raw)
To: David Brownell, Greg Kroah-Hartman,
linux-usb-u79uwXL29TY76Z2rM5mHXA, Robert Morell
Cc: Benoit Goby, Olof Johansson, Erik Gilling,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1297228927-23497-1-git-send-email-benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Benoit Goby <benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
---
drivers/usb/Kconfig | 1 +
drivers/usb/host/Kconfig | 8 +
drivers/usb/host/ehci-hcd.c | 5 +
drivers/usb/host/ehci-tegra.c | 673 +++++++++++++++++++++++++++++++++++++++++
include/linux/tegra_usb.h | 35 +++
5 files changed, 722 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/ehci-tegra.c
create mode 100644 include/linux/tegra_usb.h
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index fceea5e..a2fa2a8 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -59,6 +59,7 @@ config USB_ARCH_HAS_EHCI
default y if PPC_MPC512x
default y if SOC_AU1200
default y if ARCH_IXP4XX
+ default y if ARCH_TEGRA
default y if ARCH_W90X900
default y if ARCH_AT91SAM9G45
default y if ARCH_MXC
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 24046c0..a769adc 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -459,6 +459,14 @@ config USB_HWA_HCD
To compile this driver a module, choose M here: the module
will be called "hwa-hc".
+config USB_TEGRA_HCD
+ boolean "NVIDIA Tegra HCD support"
+ depends on USB && ARCH_TEGRA && USB_EHCI_HCD
+ select USB_EHCI_ROOT_HUB_TT
+ help
+ This driver enables support for the internal USB Host Controller
+ found in NVIDIA Tegra SoCs. The Tegra controller is EHCI compliant.
+
config USB_IMX21_HCD
tristate "iMX21 HCD support"
depends on USB && ARM && MACH_MX21
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 7afa345..63e8b29 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1246,6 +1246,11 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ehci_msm_driver
#endif
+#ifdef CONFIG_ARCH_TEGRA
+#include "ehci-tegra.c"
+#define PLATFORM_DRIVER tegra_ehci_driver
+#endif
+
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
!defined(XILINX_OF_PLATFORM_DRIVER)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
new file mode 100644
index 0000000..24783ca
--- /dev/null
+++ b/drivers/usb/host/ehci-tegra.c
@@ -0,0 +1,673 @@
+/*
+ * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2009 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/tegra_usb.h>
+#include <linux/irq.h>
+#include <linux/usb/otg.h>
+#include <mach/usb_phy.h>
+
+#define TEGRA_USB_USBCMD_REG_OFFSET 0x140
+#define TEGRA_USB_USBCMD_RESET (1 << 1)
+#define TEGRA_USB_USBMODE_REG_OFFSET 0x1a8
+#define TEGRA_USB_USBMODE_HOST (3 << 0)
+#define TEGRA_USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
+
+struct tegra_ehci_hcd {
+ struct ehci_hcd *ehci;
+ struct tegra_usb_phy *phy;
+ struct clk *clk;
+ struct clk *emc_clk;
+ struct otg_transceiver *transceiver;
+ int host_resumed;
+ int bus_suspended;
+ int port_resuming;
+ int power_down_on_bus_suspend;
+ enum tegra_usb_phy_port_speed port_speed;
+};
+
+static void tegra_ehci_power_up(struct usb_hcd *hcd)
+{
+ struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
+
+ clk_enable(tegra->emc_clk);
+ clk_enable(tegra->clk);
+ tegra_usb_phy_power_on(tegra->phy);
+ tegra->host_resumed = 1;
+}
+
+static void tegra_ehci_power_down(struct usb_hcd *hcd)
+{
+ struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
+
+ tegra->host_resumed = 0;
+ tegra_usb_phy_power_off(tegra->phy);
+ clk_disable(tegra->clk);
+ clk_disable(tegra->emc_clk);
+}
+
+static int tegra_ehci_hub_control(
+ struct usb_hcd *hcd,
+ u16 typeReq,
+ u16 wValue,
+ u16 wIndex,
+ char *buf,
+ u16 wLength
+)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
+ u32 __iomem *status_reg;
+ u32 temp;
+ unsigned long flags;
+ int retval = 0;
+
+ status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
+
+ spin_lock_irqsave(&ehci->lock, flags);
+
+ /*
+ * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
+ * that are write on clear, by writing back the register read value, so
+ * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
+ */
+ if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
+ temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
+ ehci_writel(ehci, temp & ~PORT_PE, status_reg);
+ goto done;
+ }
+
+ else if (typeReq == GetPortStatus) {
+ temp = ehci_readl(ehci, status_reg);
+ if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
+ /* resume completed */
+ tegra->port_resuming = 0;
+ tegra_usb_phy_postresume(tegra->phy);
+ }
+ }
+
+ else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
+ temp = ehci_readl(ehci, status_reg);
+ if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
+ retval = -EPIPE;
+ goto done;
+ }
+
+ /* After above check the port must be connected.
+ * Set appropriate bit thus could put phy into low power
+ * mode if we have hostpc feature
+ */
+ temp &= ~PORT_WKCONN_E;
+ temp |= PORT_WKDISC_E | PORT_WKOC_E;
+ ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
+ if (handshake(ehci, status_reg, PORT_SUSPEND,
+ PORT_SUSPEND, 5000))
+ pr_err("%s: timeout waiting for SUSPEND\n", __func__);
+ set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
+ goto done;
+ }
+
+ /*
+ * Tegra host controller will time the resume operation to clear the bit
+ * when the port control state switches to HS or FS Idle. This behavior
+ * is different from EHCI where the host controller driver is required
+ * to set this bit to a zero after the resume duration is timed in the
+ * driver.
+ */
+ else if (typeReq == ClearPortFeature &&
+ wValue == USB_PORT_FEAT_SUSPEND) {
+ temp = ehci_readl(ehci, status_reg);
+ if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
+ retval = -EPIPE;
+ goto done;
+ }
+
+ if (!(temp & PORT_SUSPEND))
+ goto done;
+
+ tegra_usb_phy_preresume(tegra->phy);
+
+ ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
+
+ temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
+ /* start resume signalling */
+ ehci_writel(ehci, temp | PORT_RESUME, status_reg);
+
+ spin_unlock_irqrestore(&ehci->lock, flags);
+ msleep(20);
+ spin_lock_irqsave(&ehci->lock, flags);
+
+ /* polling PORT_RESUME until the controller clear this bit */
+ if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
+ pr_err("%s: timeout waiting for RESUME\n", __func__);
+
+ /* polling PORT_SUSPEND until the controller clear this bit */
+ if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
+ pr_err("%s: timeout waiting for SUSPEND\n", __func__);
+
+ ehci->reset_done[wIndex-1] = 0;
+
+ tegra->port_resuming = 1;
+ goto done;
+ }
+
+ spin_unlock_irqrestore(&ehci->lock, flags);
+
+ /* Handle the hub control events here */
+ return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
+done:
+ spin_unlock_irqrestore(&ehci->lock, flags);
+ return retval;
+}
+
+static int tegra_ehci_reset(struct usb_hcd *hcd)
+{
+ unsigned long temp;
+ int usec = 250*1000; /* see ehci_reset */
+
+ temp = readl(hcd->regs + TEGRA_USB_USBCMD_REG_OFFSET);
+ temp |= TEGRA_USB_USBCMD_RESET;
+ writel(temp, hcd->regs + TEGRA_USB_USBCMD_REG_OFFSET);
+
+ do {
+ temp = readl(hcd->regs + TEGRA_USB_USBCMD_REG_OFFSET);
+ if (!(temp & TEGRA_USB_USBCMD_RESET))
+ break;
+ udelay(1);
+ usec--;
+ } while (usec);
+
+ if (!usec)
+ return -ETIMEDOUT;
+
+ /* Set to Host mode by setting bit 0-1 of USB device mode register */
+ temp = readl(hcd->regs + TEGRA_USB_USBMODE_REG_OFFSET);
+ writel((temp | TEGRA_USB_USBMODE_HOST),
+ (hcd->regs + TEGRA_USB_USBMODE_REG_OFFSET));
+
+ return 0;
+}
+
+static void tegra_ehci_restart(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+ tegra_ehci_reset(hcd);
+
+ /* setup the frame list and Async q heads */
+ ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
+ ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
+ /* setup the command register and set the controller in RUN mode */
+ ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
+ ehci->command |= CMD_RUN;
+ ehci_writel(ehci, ehci->command, &ehci->regs->command);
+
+ down_write(&ehci_cf_port_reset_rwsem);
+ ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
+ /* flush posted writes */
+ ehci_readl(ehci, &ehci->regs->command);
+ up_write(&ehci_cf_port_reset_rwsem);
+}
+
+static int tegra_usb_suspend(struct usb_hcd *hcd)
+{
+ struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
+ struct ehci_regs __iomem *hw = tegra->ehci->regs;
+ unsigned long flags;
+
+ spin_lock_irqsave(&tegra->ehci->lock, flags);
+
+ tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
+ ehci_halt(tegra->ehci);
+ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+ spin_unlock_irqrestore(&tegra->ehci->lock, flags);
+
+ tegra_ehci_power_down(hcd);
+ return 0;
+}
+
+static int tegra_usb_resume(struct usb_hcd *hcd)
+{
+ struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ struct ehci_regs __iomem *hw = ehci->regs;
+ unsigned long val;
+
+ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+ tegra_ehci_power_up(hcd);
+
+ if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
+ /* Wait for the phy to detect new devices
+ * before we restart the controller */
+ msleep(10);
+ goto restart;
+ }
+
+ tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
+
+ writel(TEGRA_USB_USBMODE_HOST, &hw->reserved[19]);
+
+ /* Enable Port Power */
+ val = readl(&hw->port_status[0]);
+ val |= PORT_POWER;
+ writel(val, &hw->port_status[0]);
+ udelay(10);
+
+ /* Check if the phy resume from LP0. When the phy resume from LP0
+ * USB register will be reset. */
+ if (!readl(&hw->async_next)) {
+ /* Program the field PTC based on the saved speed mode */
+ val = readl(&hw->port_status[0]);
+ val &= ~(TEGRA_USB_PORTSC1_PTC(~0));
+ if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
+ val |= TEGRA_USB_PORTSC1_PTC(5);
+ else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
+ val |= TEGRA_USB_PORTSC1_PTC(6);
+ else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
+ val |= TEGRA_USB_PORTSC1_PTC(7);
+ writel(val, &hw->port_status[0]);
+ udelay(10);
+
+ /* Disable test mode by setting PTC field to NORMAL_OP */
+ val = readl(&hw->port_status[0]);
+ val &= ~(TEGRA_USB_PORTSC1_PTC(~0));
+ writel(val, &hw->port_status[0]);
+ udelay(10);
+ }
+
+ /* Poll until CCS is enabled */
+ if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
+ PORT_CONNECT, 2000)) {
+ pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
+ goto restart;
+ }
+
+ /* Poll until PE is enabled */
+ if (handshake(ehci, &hw->port_status[0], PORT_PE,
+ PORT_PE, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
+ goto restart;
+ }
+
+ /* Clear the PCI status, to avoid an interrupt taken upon resume */
+ val = readl(&hw->status);
+ val |= STS_PCD;
+ writel(val, &hw->status);
+
+ /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
+ val = readl(&hw->port_status[0]);
+ if ((val & PORT_POWER) && (val & PORT_PE)) {
+ val |= PORT_SUSPEND;
+ writel(val, &hw->port_status[0]);
+
+ /* Wait until port suspend completes */
+ if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
+ PORT_SUSPEND, 1000)) {
+ pr_err("%s: timeout waiting for PORT_SUSPEND\n",
+ __func__);
+ goto restart;
+ }
+ }
+
+ tegra_ehci_phy_restore_end(tegra->phy);
+ return 0;
+
+restart:
+ if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
+ tegra_ehci_phy_restore_end(tegra->phy);
+
+ tegra_ehci_restart(hcd);
+ return 0;
+}
+
+static void tegra_ehci_shutdown(struct usb_hcd *hcd)
+{
+ struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
+
+ /* ehci_shutdown touches the USB controller registers, make sure
+ * controller has clocks to it */
+ if (!tegra->host_resumed)
+ tegra_ehci_power_up(hcd);
+
+ ehci_shutdown(hcd);
+}
+
+static int tegra_ehci_setup(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ int retval;
+
+ /* EHCI registers start at offset 0x100 */
+ ehci->caps = hcd->regs + 0x100;
+ ehci->regs = hcd->regs + 0x100 +
+ HC_LENGTH(readl(&ehci->caps->hc_capbase));
+
+ dbg_hcs_params(ehci, "reset");
+ dbg_hcc_params(ehci, "reset");
+
+ /* cache this readonly data; minimize chip reads */
+ ehci->hcs_params = readl(&ehci->caps->hcs_params);
+
+ retval = ehci_halt(ehci);
+ if (retval)
+ return retval;
+
+ /* data structure init */
+ retval = ehci_init(hcd);
+ if (retval)
+ return retval;
+
+ hcd->has_tt = 1;
+ ehci->sbrn = 0x20;
+
+ ehci_reset(ehci);
+
+ /*
+ * Resetting the controller has the side effect of resetting the PHY.
+ * So, never reset the controller after the calling
+ * tegra_ehci_reinit API.
+ */
+ ehci->controller_resets_phy = 1;
+
+ ehci_port_power(ehci, 1);
+ return retval;
+}
+
+#ifdef CONFIG_PM
+static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
+{
+ struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
+ int error_status = 0;
+
+ error_status = ehci_bus_suspend(hcd);
+ if (!error_status && tegra->power_down_on_bus_suspend) {
+ tegra_usb_suspend(hcd);
+ tegra->bus_suspended = 1;
+ }
+
+ return error_status;
+}
+
+static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
+{
+ struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
+
+ if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
+ tegra_usb_resume(hcd);
+ tegra->bus_suspended = 0;
+ }
+
+ tegra_usb_phy_preresume(tegra->phy);
+ tegra->port_resuming = 1;
+ return ehci_bus_resume(hcd);
+}
+#endif
+
+static const struct hc_driver tegra_ehci_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "Tegra EHCI Host Controller",
+ .hcd_priv_size = sizeof(struct ehci_hcd),
+
+ .flags = HCD_USB2 | HCD_MEMORY,
+
+ .reset = tegra_ehci_setup,
+ .irq = ehci_irq,
+
+ .start = ehci_run,
+ .stop = ehci_stop,
+ .shutdown = tegra_ehci_shutdown,
+ .urb_enqueue = ehci_urb_enqueue,
+ .urb_dequeue = ehci_urb_dequeue,
+ .endpoint_disable = ehci_endpoint_disable,
+ .endpoint_reset = ehci_endpoint_reset,
+ .get_frame_number = ehci_get_frame,
+ .hub_status_data = ehci_hub_status_data,
+ .hub_control = tegra_ehci_hub_control,
+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+#ifdef CONFIG_PM
+ .bus_suspend = tegra_ehci_bus_suspend,
+ .bus_resume = tegra_ehci_bus_resume,
+#endif
+ .relinquish_port = ehci_relinquish_port,
+ .port_handed_over = ehci_port_handed_over,
+};
+
+static int tegra_ehci_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct usb_hcd *hcd;
+ struct ehci_hcd *ehci;
+ struct tegra_ehci_hcd *tegra;
+ struct tegra_ehci_platform_data *pdata;
+ struct tegra_utmip_config *config;
+ int err = 0;
+ int irq;
+ int instance = pdev->id;
+
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
+ dev_err(&pdev->dev, "Platform data missing\n");
+ return -EINVAL;
+ }
+
+ tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
+ if (!tegra)
+ return -ENOMEM;
+
+ hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
+ dev_name(&pdev->dev));
+ if (!hcd) {
+ dev_err(&pdev->dev, "Unable to create HCD\n");
+ err = -ENOMEM;
+ goto fail_hcd;
+ }
+
+ platform_set_drvdata(pdev, tegra);
+
+ tegra->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(tegra->clk)) {
+ dev_err(&pdev->dev, "Can't get ehci clock\n");
+ err = PTR_ERR(tegra->clk);
+ goto fail_clk;
+ }
+
+ err = clk_enable(tegra->clk);
+ if (err)
+ goto fail_clken;
+
+ tegra->emc_clk = clk_get(&pdev->dev, "emc");
+ if (IS_ERR(tegra->emc_clk)) {
+ dev_err(&pdev->dev, "Can't get emc clock\n");
+ err = PTR_ERR(tegra->emc_clk);
+ goto fail_emc_clk;
+ }
+
+ clk_enable(tegra->emc_clk);
+ clk_set_rate(tegra->emc_clk, 400000000);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Failed to get I/O memory\n");
+ err = -ENXIO;
+ goto fail_io;
+ }
+ hcd->rsrc_start = res->start;
+ hcd->rsrc_len = resource_size(res);
+ hcd->regs = ioremap(res->start, resource_size(res));
+ if (!hcd->regs) {
+ dev_err(&pdev->dev, "Failed to remap I/O memory\n");
+ err = -ENOMEM;
+ goto fail_io;
+ }
+
+ config = pdata->phy_config;
+
+ tegra->phy = tegra_usb_phy_open(instance, hcd->regs, config,
+ TEGRA_USB_PHY_MODE_HOST);
+ if (IS_ERR(tegra->phy)) {
+ dev_err(&pdev->dev, "Failed to open USB phy\n");
+ err = -ENXIO;
+ goto fail_phy;
+ }
+
+ err = tegra_ehci_reset(hcd);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to reset controller\n");
+ goto fail;
+ }
+
+ tegra_usb_phy_power_on(tegra->phy);
+ tegra->host_resumed = 1;
+ tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
+
+ irq = platform_get_irq(pdev, 0);
+ if (!irq) {
+ dev_err(&pdev->dev, "Failed to get IRQ\n");
+ err = -ENODEV;
+ goto fail;
+ }
+
+ set_irq_flags(irq, IRQF_VALID);
+
+ ehci = hcd_to_ehci(hcd);
+ tegra->ehci = ehci;
+
+#ifdef CONFIG_USB_OTG_UTILS
+ if (pdata->operating_mode == TEGRA_USB_OTG) {
+ tegra->transceiver = otg_get_transceiver();
+ if (tegra->transceiver)
+ otg_set_host(tegra->transceiver, &hcd->self);
+ }
+#endif
+
+ err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+ if (err != 0) {
+ dev_err(&pdev->dev, "Failed to add USB HCD\n");
+ goto fail;
+ }
+
+ return err;
+
+fail:
+#ifdef CONFIG_USB_OTG_UTILS
+ if (tegra->transceiver) {
+ otg_set_host(tegra->transceiver, NULL);
+ otg_put_transceiver(tegra->transceiver);
+ }
+#endif
+ tegra_usb_phy_close(tegra->phy);
+fail_phy:
+ iounmap(hcd->regs);
+fail_io:
+ clk_disable(tegra->emc_clk);
+ clk_put(tegra->emc_clk);
+fail_emc_clk:
+ clk_disable(tegra->clk);
+fail_clken:
+ clk_put(tegra->clk);
+fail_clk:
+ usb_put_hcd(hcd);
+fail_hcd:
+ kfree(tegra);
+ return err;
+}
+
+#ifdef CONFIG_PM
+static int tegra_ehci_resume(struct platform_device *pdev)
+{
+ struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
+ struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
+
+ if (tegra->bus_suspended)
+ return 0;
+
+ return tegra_usb_resume(hcd);
+}
+
+static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
+ struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
+
+ if (tegra->bus_suspended)
+ return 0;
+
+ if (time_before(jiffies, tegra->ehci->next_statechange))
+ msleep(10);
+
+ return tegra_usb_suspend(hcd);
+}
+#endif
+
+static int tegra_ehci_remove(struct platform_device *pdev)
+{
+ struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
+ struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
+
+ if (tegra == NULL || hcd == NULL)
+ return -EINVAL;
+
+#ifdef CONFIG_USB_OTG_UTILS
+ if (tegra->transceiver) {
+ otg_set_host(tegra->transceiver, NULL);
+ otg_put_transceiver(tegra->transceiver);
+ }
+#endif
+
+ usb_remove_hcd(hcd);
+ usb_put_hcd(hcd);
+
+ tegra_usb_phy_close(tegra->phy);
+ iounmap(hcd->regs);
+
+ clk_disable(tegra->clk);
+ clk_put(tegra->clk);
+
+ clk_disable(tegra->emc_clk);
+ clk_put(tegra->emc_clk);
+
+ kfree(tegra);
+ return 0;
+}
+
+static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
+{
+ struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
+ struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
+
+ if (hcd->driver->shutdown)
+ hcd->driver->shutdown(hcd);
+}
+
+static struct platform_driver tegra_ehci_driver = {
+ .probe = tegra_ehci_probe,
+ .remove = tegra_ehci_remove,
+#ifdef CONFIG_PM
+ .suspend = tegra_ehci_suspend,
+ .resume = tegra_ehci_resume,
+#endif
+ .shutdown = tegra_ehci_hcd_shutdown,
+ .driver = {
+ .name = "tegra-ehci",
+ }
+};
diff --git a/include/linux/tegra_usb.h b/include/linux/tegra_usb.h
new file mode 100644
index 0000000..2947ed2
--- /dev/null
+++ b/include/linux/tegra_usb.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#ifndef _TEGRA_USB_H_
+#define _TEGRA_USB_H_
+
+enum tegra_usb_operating_modes {
+ TEGRA_USB_DEVICE,
+ TEGRA_USB_HOST,
+ TEGRA_USB_OTG,
+};
+
+struct tegra_ehci_platform_data {
+ enum tegra_usb_operating_modes operating_mode;
+ /* power down the phy on bus suspend */
+ int power_down_on_bus_suspend;
+ void *phy_config;
+};
+
+#endif /* _TEGRA_USB_H_ */
--
1.7.3.1
--
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^ permalink raw reply related
* [PATCH 2/4] usb: host: ehci-hcd: Add controller_resets_phy quirk
From: Benoit Goby @ 2011-02-09 5:22 UTC (permalink / raw)
To: David Brownell, Greg Kroah-Hartman,
linux-usb-u79uwXL29TY76Z2rM5mHXA, Robert Morell
Cc: Benoit Goby, Olof Johansson, Erik Gilling,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Gary King
In-Reply-To: <1297228927-23497-1-git-send-email-benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
From: Gary King <gking-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Tegra quirk: Resetting the controller has the side effect of resetting
the PHY. Only reset the controller when doing so won't also reset the
phy.
Signed-off-by: Gary King <gking-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Benoit Goby <benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
---
drivers/usb/host/ehci-hcd.c | 3 ++-
drivers/usb/host/ehci.h | 1 +
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 30515d3..7afa345 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -275,7 +275,8 @@ static int ehci_reset (struct ehci_hcd *ehci)
command |= CMD_RESET;
dbg_cmd (ehci, "reset", command);
- ehci_writel(ehci, command, &ehci->regs->command);
+ if (!ehci->controller_resets_phy)
+ ehci_writel(ehci, command, &ehci->regs->command);
ehci_to_hcd(ehci)->state = HC_STATE_HALT;
ehci->next_statechange = jiffies;
retval = handshake (ehci, &ehci->regs->command,
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index f86d3fa..8854491 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -134,6 +134,7 @@ struct ehci_hcd { /* one per controller */
unsigned amd_pll_fix:1;
unsigned fs_i_thresh:1; /* Intel iso scheduling */
unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
+ unsigned controller_resets_phy:1; /* Tegra quirk */
/* required for usb32 quirk */
#define OHCI_CTRL_HCFS (3 << 6)
--
1.7.3.1
--
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^ permalink raw reply related
* [PATCH 1/4] [ARM] tegra: Add support for Tegra USB PHYs
From: Benoit Goby @ 2011-02-09 5:22 UTC (permalink / raw)
To: David Brownell, Greg Kroah-Hartman,
linux-usb-u79uwXL29TY76Z2rM5mHXA, Robert Morell
Cc: Benoit Goby, Olof Johansson, Erik Gilling,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1297228927-23497-1-git-send-email-benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
Interface used by Tegra's gadget driver and ehci driver
to power on and configure the USB PHYs.
Signed-off-by: Benoit Goby <benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/include/mach/usb_phy.h | 83 +++
arch/arm/mach-tegra/usb_phy.c | 794 ++++++++++++++++++++++++++++
3 files changed, 878 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-tegra/include/mach/usb_phy.h
create mode 100644 arch/arm/mach-tegra/usb_phy.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index cdbc68e..38b66a8 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o
obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
obj-$(CONFIG_TEGRA_PCI) += pcie.o
+obj-$(CONFIG_USB_SUPPORT) += usb_phy.o
obj-${CONFIG_MACH_HARMONY} += board-harmony.o
obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
new file mode 100644
index 0000000..bf97667
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/usb_phy.h
@@ -0,0 +1,83 @@
+/*
+ * arch/arm/mach-tegra/include/mach/usb_phy.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_USB_PHY_H
+#define __MACH_USB_PHY_H
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+struct tegra_utmip_config {
+ u8 hssync_start_delay;
+ u8 elastic_limit;
+ u8 idle_wait_delay;
+ u8 term_range_adj;
+ u8 xcvr_setup;
+ u8 xcvr_lsfslew;
+ u8 xcvr_lsrslew;
+};
+
+struct tegra_ulpi_config {
+ int reset_gpio;
+ const char *clk;
+};
+
+enum tegra_usb_phy_port_speed {
+ TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
+ TEGRA_USB_PHY_PORT_SPEED_LOW,
+ TEGRA_USB_PHY_PORT_SPEED_HIGH,
+};
+
+enum tegra_usb_phy_mode {
+ TEGRA_USB_PHY_MODE_DEVICE,
+ TEGRA_USB_PHY_MODE_HOST,
+};
+
+struct tegra_usb_phy {
+ int instance;
+ int freq_sel;
+ void __iomem *regs;
+ void __iomem *pad_regs;
+ struct clk *clk;
+ struct clk *pll_u;
+ struct clk *pad_clk;
+ enum tegra_usb_phy_mode mode;
+ void *config;
+};
+
+struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
+ void *config, enum tegra_usb_phy_mode phy_mode);
+
+int tegra_usb_phy_power_on(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_power_off(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_preresume(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_postresume(struct tegra_usb_phy *phy);
+
+int tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
+ enum tegra_usb_phy_port_speed port_speed);
+
+int tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_close(struct tegra_usb_phy *phy);
+
+#endif /* __MACH_USB_PHY_H */
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
new file mode 100644
index 0000000..7242dda
--- /dev/null
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -0,0 +1,794 @@
+/*
+ * arch/arm/mach-tegra/usb_phy.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ * Erik Gilling <konkers-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
+ * Benoit Goby <benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <mach/usb_phy.h>
+#include <mach/iomap.h>
+
+#define USB_USBSTS 0x144
+#define USB_USBSTS_PCI (1 << 2)
+
+#define ULPI_VIEWPORT 0x170
+#define ULPI_WAKEUP (1 << 31)
+#define ULPI_RUN (1 << 30)
+#define ULPI_RD_RW_WRITE (1 << 29)
+#define ULPI_RD_RW_READ (0 << 29)
+#define ULPI_PORT(x) (((x) & 0x7) << 24)
+#define ULPI_ADDR(x) (((x) & 0xff) << 16)
+#define ULPI_DATA_RD(x) (((x) & 0xff) << 8)
+#define ULPI_DATA_WR(x) (((x) & 0xff) << 0)
+
+#define USB_PORTSC1 0x184
+#define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
+#define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26)
+#define USB_PORTSC1_PHCD (1 << 23)
+#define USB_PORTSC1_WKOC (1 << 22)
+#define USB_PORTSC1_WKDS (1 << 21)
+#define USB_PORTSC1_WKCN (1 << 20)
+#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
+#define USB_PORTSC1_PP (1 << 12)
+#define USB_PORTSC1_SUSP (1 << 7)
+#define USB_PORTSC1_PE (1 << 2)
+#define USB_PORTSC1_CCS (1 << 0)
+
+#define USB_SUSP_CTRL 0x400
+#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
+#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
+#define USB_SUSP_CLR (1 << 5)
+#define USB_PHY_CLK_VALID (1 << 7)
+#define UTMIP_RESET (1 << 11)
+#define UHSIC_RESET (1 << 11)
+#define UTMIP_PHY_ENABLE (1 << 12)
+#define ULPI_PHY_ENABLE (1 << 13)
+#define USB_SUSP_SET (1 << 14)
+#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
+
+#define USB1_LEGACY_CTRL 0x410
+#define USB1_NO_LEGACY_MODE (1 << 0)
+#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
+#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
+#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
+ (1 << 1)
+#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
+#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
+
+#define ULPI_TIMING_CTRL_0 0x424
+#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
+
+#define ULPI_TIMING_CTRL_1 0x428
+#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
+
+#define UTMIP_PLL_CFG1 0x804
+#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
+
+#define UTMIP_XCVR_CFG0 0x808
+#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
+#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
+#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
+#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
+#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
+
+#define UTMIP_BIAS_CFG0 0x80c
+#define UTMIP_OTGPD (1 << 11)
+#define UTMIP_BIASPD (1 << 10)
+
+#define UTMIP_HSRX_CFG0 0x810
+#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
+#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
+
+#define UTMIP_HSRX_CFG1 0x814
+#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
+
+#define UTMIP_TX_CFG0 0x820
+#define UTMIP_FS_PREABMLE_J (1 << 19)
+#define UTMIP_HS_DISCON_DISABLE (1 << 8)
+
+#define UTMIP_MISC_CFG0 0x824
+#define UTMIP_DPDM_OBSERVE (1 << 26)
+#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
+#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
+
+#define UTMIP_MISC_CFG1 0x828
+#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
+#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
+
+#define UTMIP_DEBOUNCE_CFG0 0x82c
+#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
+
+#define UTMIP_BAT_CHRG_CFG0 0x830
+#define UTMIP_PD_CHRG (1 << 0)
+
+#define UTMIP_SPARE_CFG0 0x834
+#define FUSE_SETUP_SEL (1 << 3)
+
+#define UTMIP_XCVR_CFG1 0x838
+#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
+#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
+
+#define UTMIP_BIAS_CFG1 0x83c
+#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
+
+static DEFINE_SPINLOCK(utmip_pad_lock);
+static int utmip_pad_count;
+
+static const int udc_freq_table[] = {
+ 12000000,
+ 13000000,
+ 19200000,
+ 26000000,
+};
+
+static const u8 udc_delay_table[][4] = {
+ /* ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
+ {0x02, 0x2F, 0x04, 0x76}, /* 12 MHz */
+ {0x02, 0x33, 0x05, 0x7F}, /* 13 MHz */
+ {0x03, 0x4B, 0x06, 0xBB}, /* 19.2 MHz */
+ {0x04, 0x66, 0x09, 0xFE}, /* 26 Mhz */
+};
+
+static const u16 udc_debounce_table[] = {
+ 0x7530, /* 12 MHz */
+ 0x7EF4, /* 13 MHz */
+ 0xBB80, /* 19.2 MHz */
+ 0xFDE8, /* 26 MHz */
+};
+
+static struct tegra_utmip_config utmip_default[] = {
+ [0] = {
+ .hssync_start_delay = 9,
+ .idle_wait_delay = 17,
+ .elastic_limit = 16,
+ .term_range_adj = 6,
+ .xcvr_setup = 9,
+ .xcvr_lsfslew = 1,
+ .xcvr_lsrslew = 1,
+ },
+ [2] = {
+ .hssync_start_delay = 9,
+ .idle_wait_delay = 17,
+ .elastic_limit = 16,
+ .term_range_adj = 6,
+ .xcvr_setup = 9,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ },
+};
+
+static int utmip_pad_open(struct tegra_usb_phy *phy)
+{
+ phy->pad_clk = clk_get_sys("utmip-pad", NULL);
+ if (IS_ERR(phy->pad_clk)) {
+ pr_err("%s: can't get utmip pad clock\n", __func__);
+ return -1;
+ }
+
+ if (phy->instance == 0) {
+ phy->pad_regs = phy->regs;
+ } else {
+ phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
+ if (!phy->pad_regs) {
+ pr_err("%s: can't remap usb registers\n", __func__);
+ clk_put(phy->pad_clk);
+ return -ENOMEM;
+ }
+ }
+ return 0;
+}
+
+static void utmip_pad_close(struct tegra_usb_phy *phy)
+{
+ if (phy->instance != 0)
+ iounmap(phy->pad_regs);
+ clk_put(phy->pad_clk);
+}
+
+static void utmip_pad_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val, flags;
+ void __iomem *base = phy->pad_regs;
+
+ clk_enable(phy->pad_clk);
+
+ spin_lock_irqsave(&utmip_pad_lock, flags);
+
+ if (utmip_pad_count++ == 0) {
+ val = readl(base + UTMIP_BIAS_CFG0);
+ val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
+ writel(val, base + UTMIP_BIAS_CFG0);
+ }
+
+ spin_unlock_irqrestore(&utmip_pad_lock, flags);
+
+ clk_disable(phy->pad_clk);
+}
+
+static int utmip_pad_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val, flags;
+ void __iomem *base = phy->pad_regs;
+
+ if (!utmip_pad_count) {
+ pr_err("%s: utmip pad already powered off\n", __func__);
+ return -1;
+ }
+
+ clk_enable(phy->pad_clk);
+
+ spin_lock_irqsave(&utmip_pad_lock, flags);
+
+ if (--utmip_pad_count == 0) {
+ val = readl(base + UTMIP_BIAS_CFG0);
+ val |= UTMIP_OTGPD | UTMIP_BIASPD;
+ writel(val, base + UTMIP_BIAS_CFG0);
+ }
+
+ spin_unlock_irqrestore(&utmip_pad_lock, flags);
+
+ clk_disable(phy->pad_clk);
+
+ return 0;
+}
+
+static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
+{
+ unsigned long timeout = 2000;
+ do {
+ if ((readl(reg) & mask) == result)
+ return 0;
+ udelay(1);
+ timeout--;
+ } while (timeout);
+ return -1;
+}
+
+static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ if (phy->instance == 0) {
+ val = readl(base + USB_SUSP_CTRL);
+ val |= USB_SUSP_SET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ udelay(10);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_SUSP_SET;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ if (phy->instance == 2) {
+ val = readl(base + USB_PORTSC1);
+ val |= USB_PORTSC1_PHCD;
+ writel(val, base + USB_PORTSC1);
+ }
+
+ if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
+ pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
+}
+
+static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ if (phy->instance == 0) {
+ val = readl(base + USB_SUSP_CTRL);
+ val |= USB_SUSP_CLR;
+ writel(val, base + USB_SUSP_CTRL);
+
+ udelay(10);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_SUSP_CLR;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ if (phy->instance == 2) {
+ val = readl(base + USB_PORTSC1);
+ val &= ~USB_PORTSC1_PHCD;
+ writel(val, base + USB_PORTSC1);
+ }
+
+ if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
+ USB_PHY_CLK_VALID))
+ pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
+}
+
+static void utmi_phy_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ struct tegra_utmip_config *config = phy->config;
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ if (phy->instance == 0) {
+ val = readl(base + USB1_LEGACY_CTRL);
+ val |= USB1_NO_LEGACY_MODE;
+ writel(val, base + USB1_LEGACY_CTRL);
+ }
+
+ val = readl(base + UTMIP_TX_CFG0);
+ val &= ~UTMIP_FS_PREABMLE_J;
+ writel(val, base + UTMIP_TX_CFG0);
+
+ val = readl(base + UTMIP_HSRX_CFG0);
+ val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
+ val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
+ val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
+ writel(val, base + UTMIP_HSRX_CFG0);
+
+ val = readl(base + UTMIP_HSRX_CFG1);
+ val &= ~UTMIP_HS_SYNC_START_DLY(~0);
+ val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
+ writel(val, base + UTMIP_HSRX_CFG1);
+
+ val = readl(base + UTMIP_DEBOUNCE_CFG0);
+ val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
+ val |= UTMIP_BIAS_DEBOUNCE_A(udc_debounce_table[phy->freq_sel]);
+ writel(val, base + UTMIP_DEBOUNCE_CFG0);
+
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
+ writel(val, base + UTMIP_MISC_CFG0);
+
+ val = readl(base + UTMIP_MISC_CFG1);
+ val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
+ val |= UTMIP_PLL_ACTIVE_DLY_COUNT(udc_delay_table[phy->freq_sel][2]) |
+ UTMIP_PLLU_STABLE_COUNT(udc_delay_table[phy->freq_sel][1]);
+ writel(val, base + UTMIP_MISC_CFG1);
+
+ val = readl(base + UTMIP_PLL_CFG1);
+ val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
+ val |= UTMIP_XTAL_FREQ_COUNT(udc_delay_table[phy->freq_sel][3]) |
+ UTMIP_PLLU_ENABLE_DLY_COUNT(udc_delay_table[phy->freq_sel][0]);
+ writel(val, base + UTMIP_PLL_CFG1);
+
+ if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ utmip_pad_power_on(phy);
+
+ val = readl(base + UTMIP_XCVR_CFG0);
+ val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
+ UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
+ UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
+ UTMIP_XCVR_HSSLEW_MSB(~0));
+ val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
+ val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
+ val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
+ writel(val, base + UTMIP_XCVR_CFG0);
+
+ val = readl(base + UTMIP_XCVR_CFG1);
+ val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
+ UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
+ val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
+ writel(val, base + UTMIP_XCVR_CFG1);
+
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val &= ~UTMIP_PD_CHRG;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+
+ val = readl(base + UTMIP_BIAS_CFG1);
+ val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
+ val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
+ writel(val, base + UTMIP_BIAS_CFG1);
+
+ if (phy->instance == 0) {
+ val = readl(base + UTMIP_SPARE_CFG0);
+ if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
+ val &= ~FUSE_SETUP_SEL;
+ else
+ val |= FUSE_SETUP_SEL;
+ writel(val, base + UTMIP_SPARE_CFG0);
+ }
+
+ if (phy->instance == 2) {
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ if (phy->instance == 0) {
+ val = readl(base + USB1_LEGACY_CTRL);
+ val &= ~USB1_VBUS_SENSE_CTL_MASK;
+ val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
+ writel(val, base + USB1_LEGACY_CTRL);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_SUSP_SET;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ utmi_phy_clk_enable(phy);
+
+ if (phy->instance == 2) {
+ val = readl(base + USB_PORTSC1);
+ val &= ~USB_PORTSC1_PTS(~0);
+ writel(val, base + USB_PORTSC1);
+ }
+}
+
+static void utmi_phy_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ utmi_phy_clk_disable(phy);
+
+ if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
+ val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val |= UTMIP_PD_CHRG;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+
+ val = readl(base + UTMIP_XCVR_CFG0);
+ val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
+ UTMIP_FORCE_PDZI_POWERDOWN;
+ writel(val, base + UTMIP_XCVR_CFG0);
+
+ val = readl(base + UTMIP_XCVR_CFG1);
+ val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
+ UTMIP_FORCE_PDDR_POWERDOWN;
+ writel(val, base + UTMIP_XCVR_CFG1);
+
+ utmip_pad_power_off(phy);
+}
+
+static void utmi_phy_preresume(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ val = readl(base + UTMIP_TX_CFG0);
+ val |= UTMIP_HS_DISCON_DISABLE;
+ writel(val, base + UTMIP_TX_CFG0);
+}
+
+static void utmi_phy_postresume(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ val = readl(base + UTMIP_TX_CFG0);
+ val &= ~UTMIP_HS_DISCON_DISABLE;
+ writel(val, base + UTMIP_TX_CFG0);
+}
+
+static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
+ enum tegra_usb_phy_port_speed port_speed)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
+ if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
+ val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
+ else
+ val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
+ writel(val, base + UTMIP_MISC_CFG0);
+ udelay(1);
+
+ val = readl(base + UTMIP_MISC_CFG0);
+ val |= UTMIP_DPDM_OBSERVE;
+ writel(val, base + UTMIP_MISC_CFG0);
+ udelay(10);
+}
+
+static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_DPDM_OBSERVE;
+ writel(val, base + UTMIP_MISC_CFG0);
+ udelay(10);
+}
+
+static void ulpi_viewport_write(struct tegra_usb_phy *phy, u8 addr, u8 data)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ val = ULPI_RUN | ULPI_RD_RW_WRITE | ULPI_PORT(0);
+ val |= ULPI_ADDR(addr) | ULPI_DATA_WR(data);
+ writel(val, base + ULPI_VIEWPORT);
+
+ if (utmi_wait_register(base + ULPI_VIEWPORT, ULPI_RUN, 0))
+ pr_err("%s: timeout accessing ulpi phy\n", __func__);
+}
+
+static void ulpi_phy_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ struct tegra_ulpi_config *config = phy->config;
+
+ gpio_direction_output(config->reset_gpio, 0);
+ msleep(5);
+ gpio_direction_output(config->reset_gpio, 1);
+
+ clk_enable(phy->clk);
+ msleep(1);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= ULPI_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = 0;
+ writel(val, base + ULPI_TIMING_CTRL_1);
+
+ val |= ULPI_DATA_TRIMMER_SEL(4);
+ val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
+ val |= ULPI_DIR_TRIMMER_SEL(4);
+ writel(val, base + ULPI_TIMING_CTRL_1);
+ udelay(10);
+
+ val |= ULPI_DATA_TRIMMER_LOAD;
+ val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
+ val |= ULPI_DIR_TRIMMER_LOAD;
+ writel(val, base + ULPI_TIMING_CTRL_1);
+
+ val = ULPI_WAKEUP | ULPI_RD_RW_WRITE | ULPI_PORT(0);
+ writel(val, base + ULPI_VIEWPORT);
+
+ if (utmi_wait_register(base + ULPI_VIEWPORT, ULPI_WAKEUP, 0)) {
+ pr_err("%s: timeout waiting for ulpi phy wakeup\n", __func__);
+ return;
+ }
+
+ /* Fix VbusInvalid due to floating VBUS */
+ ulpi_viewport_write(phy, 0x08, 0x40);
+ ulpi_viewport_write(phy, 0x0B, 0x80);
+
+ val = readl(base + USB_PORTSC1);
+ val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
+ writel(val, base + USB_PORTSC1);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= USB_SUSP_CLR;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(100);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_SUSP_CLR;
+ writel(val, base + USB_SUSP_CTRL);
+}
+
+static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ struct tegra_ulpi_config *config = phy->config;
+
+ /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
+ * Controller to immediately bring the ULPI PHY out of low power
+ */
+ val = readl(base + USB_PORTSC1);
+ val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
+ writel(val, base + USB_PORTSC1);
+
+ gpio_direction_output(config->reset_gpio, 0);
+ clk_disable(phy->clk);
+}
+
+struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
+ void *config, enum tegra_usb_phy_mode phy_mode)
+{
+ struct tegra_usb_phy *phy;
+ struct tegra_ulpi_config *ulpi_config;
+ unsigned long parent_rate;
+ int freq_sel;
+ int err;
+
+ phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
+ if (!phy)
+ return ERR_PTR(-ENOMEM);
+
+ phy->instance = instance;
+ phy->regs = regs;
+ phy->config = config;
+ phy->mode = phy_mode;
+
+ if (!phy->config) {
+ if (instance == 1) {
+ pr_err("%s: ulpi phy configuration missing", __func__);
+ err = -EINVAL;
+ goto err0;
+ } else {
+ phy->config = &utmip_default[instance];
+ }
+ }
+
+ phy->pll_u = clk_get_sys(NULL, "pll_u");
+ if (IS_ERR(phy->pll_u)) {
+ pr_err("Can't get pll_u clock\n");
+ err = PTR_ERR(phy->pll_u);
+ goto err0;
+ }
+ clk_enable(phy->pll_u);
+
+ parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
+ for (freq_sel = 0; freq_sel < ARRAY_SIZE(udc_freq_table); freq_sel++) {
+ if (udc_freq_table[freq_sel] == parent_rate)
+ break;
+ }
+ if (freq_sel == ARRAY_SIZE(udc_freq_table)) {
+ pr_err("invalid pll_u parent rate %ld\n", parent_rate);
+ err = -EINVAL;
+ goto err1;
+ }
+ phy->freq_sel = freq_sel;
+
+ if (phy->instance == 1) {
+ ulpi_config = config;
+ phy->clk = clk_get_sys(NULL, ulpi_config->clk);
+ if (IS_ERR(phy->clk)) {
+ pr_err("%s: can't get ulpi clock\n", __func__);
+ err = -ENXIO;
+ goto err1;
+ }
+ tegra_gpio_enable(ulpi_config->reset_gpio);
+ gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
+ gpio_direction_output(ulpi_config->reset_gpio, 0);
+ } else {
+ err = utmip_pad_open(phy);
+ if (err < 0)
+ goto err1;
+ }
+
+ return phy;
+
+err1:
+ clk_disable(phy->pll_u);
+ clk_put(phy->pll_u);
+err0:
+ kfree(phy);
+ return ERR_PTR(err);
+}
+
+int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
+{
+ if (phy->instance == 1)
+ ulpi_phy_power_on(phy);
+ else
+ utmi_phy_power_on(phy);
+
+ return 0;
+}
+
+int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
+{
+ if (phy->instance == 1)
+ ulpi_phy_power_off(phy);
+ else
+ utmi_phy_power_off(phy);
+
+ return 0;
+}
+
+int tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
+{
+ if (phy->instance != 1)
+ utmi_phy_preresume(phy);
+ return 0;
+}
+
+int tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
+{
+ if (phy->instance != 1)
+ utmi_phy_postresume(phy);
+ return 0;
+}
+
+int tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
+ enum tegra_usb_phy_port_speed port_speed)
+{
+ if (phy->instance != 1)
+ utmi_phy_restore_start(phy, port_speed);
+ return 0;
+}
+
+int tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
+{
+ if (phy->instance != 1)
+ utmi_phy_restore_end(phy);
+ return 0;
+}
+
+int tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
+{
+ if (phy->instance != 1)
+ utmi_phy_clk_disable(phy);
+
+ return 0;
+}
+
+int tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
+{
+ if (phy->instance != 1)
+ utmi_phy_clk_enable(phy);
+
+ return 0;
+}
+
+int tegra_usb_phy_close(struct tegra_usb_phy *phy)
+{
+ if (phy->instance == 1)
+ clk_put(phy->clk);
+ else
+ utmip_pad_close(phy);
+ clk_disable(phy->pll_u);
+ clk_put(phy->pll_u);
+ kfree(phy);
+ return 0;
+}
--
1.7.3.1
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^ permalink raw reply related
* [PATCH 0/4] Tegra EHCI driver
From: Benoit Goby @ 2011-02-09 5:22 UTC (permalink / raw)
To: David Brownell, Greg Kroah-Hartman,
linux-usb-u79uwXL29TY76Z2rM5mHXA, Robert Morell
Cc: Benoit Goby, Olof Johansson, Erik Gilling,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
This patch series adds support for EHCI compliant USB host
controllers found in Tegra SoCs. The EHCI driver depends on
the Tegra PHY configuration interface that is used by both
the ehci driver and the gadget driver. Tested on 2.6.38rc4.
Benoit Goby (2):
[ARM] tegra: Add support for Tegra USB PHYs
usb: host: Add EHCI driver for NVIDIA Tegra SoCs
Gary King (1):
usb: host: ehci-hcd: Add controller_resets_phy quirk
Robert Morell (1):
USB: ehci: tegra: Align DMA transfers to 32 bytes
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/include/mach/usb_phy.h | 83 +++
arch/arm/mach-tegra/usb_phy.c | 794 ++++++++++++++++++++++++++++
drivers/usb/Kconfig | 1 +
drivers/usb/host/Kconfig | 8 +
drivers/usb/host/ehci-hcd.c | 8 +-
drivers/usb/host/ehci-tegra.c | 763 ++++++++++++++++++++++++++
drivers/usb/host/ehci.h | 1 +
include/linux/tegra_usb.h | 35 ++
9 files changed, 1693 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-tegra/include/mach/usb_phy.h
create mode 100644 arch/arm/mach-tegra/usb_phy.c
create mode 100644 drivers/usb/host/ehci-tegra.c
create mode 100644 include/linux/tegra_usb.h
--
1.7.3.1
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^ permalink raw reply
* RE: [alsa-devel] [PATCH 6/6] ASoC: Tegra: Harmony: Support both int and ext mics
From: Stephen Warren @ 2011-02-08 23:32 UTC (permalink / raw)
To: Mark Brown
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
lrg-kDsPt+C1G03kYMGBc/C6ZA@public.gmane.org
In-Reply-To: <20110208205848.GA23844-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
Mark Brown wrote at Tuesday, February 08, 2011 1:59 PM:
> On Tue, Feb 08, 2011 at 12:34:09PM -0800, Stephen Warren wrote:
>
> > Maybe I should just not implement mic detection for Harmony due to these
> > issues? In which case, I'd just let mic bias be enabled whenever capture
> > was active, just like the speaker enable GPIO.
>
> It certainly seems way more trouble than it's worth: as soon as the
> on board mic is used the jack detection will get confused as it'll see
> it. Of course, the internal mic is actually plugged in to a header on
> the main board so it may be absent too (I believe a lot of units were
> shipped without a case...) which means detecting the internal mic might
> actually be useful :)
Well, one other option is to completely ignore (and disable) the internal
mic, and just support the external mic (jack). Then, mic detection could
be implemented. The advantage here is similarity to other boards without
the mic bias sharing issue. Plus, the jack is probably far more useful
than the internal mic on this board:
I honestly don't know how many boards (if any) actually have anything
plugged into the internal mic header on the board. Mine certainly
didn't originally; I used a PC speaker I stole from somewhere else as
the internal mic;-)
--
nvpublic
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^ permalink raw reply
* Re: [alsa-devel] [PATCH 1/6] ASoC: Tegra: Harmony: Add headphone jack detection
From: Liam Girdwood @ 2011-02-08 21:56 UTC (permalink / raw)
To: Mark Brown
Cc: Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
In-Reply-To: <20110208205917.GB23844-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
On Tue, 2011-02-08 at 20:59 +0000, Mark Brown wrote:
> On Tue, Feb 08, 2011 at 12:28:48PM -0800, Stephen Warren wrote:
>
> > Mark, I'm happy to go either way on this; the SW engineer in me doesn't like
> > non-const globals and inconsistency with the rest of the state data, but
> > equally fixing this seems like it would bloat the code and might make it
> > less readable.
>
> > Let me know which way you'd prefer it to go.
>
> I think your current patch is fine. Liam?
Yeah, lets go with this.
Acked-by: Liam Girdwood <lrg-kDsPt+C1G03kYMGBc/C6ZA@public.gmane.org>
--
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk
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^ permalink raw reply
* Re: [alsa-devel] [PATCH 1/6] ASoC: Tegra: Harmony: Add headphone jack detection
From: Mark Brown @ 2011-02-08 20:59 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
lrg-kDsPt+C1G03kYMGBc/C6ZA@public.gmane.org
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF0310F5FFA5-C7FfzLzN0UxDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
On Tue, Feb 08, 2011 at 12:28:48PM -0800, Stephen Warren wrote:
> Mark, I'm happy to go either way on this; the SW engineer in me doesn't like
> non-const globals and inconsistency with the rest of the state data, but
> equally fixing this seems like it would bloat the code and might make it
> less readable.
> Let me know which way you'd prefer it to go.
I think your current patch is fine. Liam?
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^ permalink raw reply
* Re: [alsa-devel] [PATCH 6/6] ASoC: Tegra: Harmony: Support both int and ext mics
From: Mark Brown @ 2011-02-08 20:58 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
lrg-kDsPt+C1G03kYMGBc/C6ZA@public.gmane.org
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF0310F5FFAC-C7FfzLzN0UxDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
On Tue, Feb 08, 2011 at 12:34:09PM -0800, Stephen Warren wrote:
> Maybe I should just not implement mic detection for Harmony due to these
> issues? In which case, I'd just let mic bias be enabled whenever capture
> was active, just like the speaker enable GPIO.
It certainly seems way more trouble than it's worth: as soon as the
on board mic is used the jack detection will get confused as it'll see
it. Of course, the internal mic is actually plugged in to a header on
the main board so it may be absent too (I believe a lot of units were
shipped without a case...) which means detecting the internal mic might
actually be useful :)
> Either way, I suppose I should add two explicit mic widgets, each directly
> driving the appropriate GPIO, so that the user can select which mic(s)
> actually get used for capture.
> Does that sound reasonable?
I think that's the best approach. If someone wants to do mic detection
they can always add it later.
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^ permalink raw reply
* RE: [alsa-devel] [PATCH 6/6] ASoC: Tegra: Harmony: Support both int and ext mics
From: Stephen Warren @ 2011-02-08 20:34 UTC (permalink / raw)
To: Mark Brown
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
lrg-kDsPt+C1G03kYMGBc/C6ZA@public.gmane.org
In-Reply-To: <20110207111310.GA31475-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
Mark Brown wrote at Monday, February 07, 2011 4:13 AM:
> On Fri, Feb 04, 2011 at 09:20:26AM -0800, Stephen Warren wrote:
>
> > However, I wonder how this interacts with mic detection using micbias
> > current. There is only one mic bias signal, routed to a subset of
> > the mics using the two per-mic enable GPIOs. Should I just hook up
> > the mic bias detection to both jacks somehow, or is the only option
> > to just punt on jack detection?
> >
> > There are no physical plug detection mechanisms on this board.
>
> That's a fairly unusual hardware design, it really needs explaining in
> the code - it wasn't at all obvious that you were controlling a FET
> reading the patch (and I'm still not entirely clear how exactly things
> are wired up). The simplest way to handle this is probably with a
> conditional DAPM route (look at how WM8994 handles SYSCLK for an example
> of this), though you'll need to faff around a bit.
>
> Ideally you want the micbias to be enabled all the time for detection of
> jack insertion, only flipping the bias over to the internal mic when the
> internal mic is being used for recording, and also disable the detection
> when the internal microphone is in use. I'm not sure that this is worth
> the bother.
Maybe I should just not implement mic detection for Harmony due to these
issues? In which case, I'd just let mic bias be enabled whenever capture
was active, just like the speaker enable GPIO.
Either way, I suppose I should add two explicit mic widgets, each directly
driving the appropriate GPIO, so that the user can select which mic(s)
actually get used for capture.
Does that sound reasonable?
Thansk.
--
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^ permalink raw reply
* RE: [alsa-devel] [PATCH 1/6] ASoC: Tegra: Harmony: Add headphone jack detection
From: Stephen Warren @ 2011-02-08 20:28 UTC (permalink / raw)
To: Mark Brown
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
lrg-kDsPt+C1G03kYMGBc/C6ZA@public.gmane.org
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF0310F5FB00-C7FfzLzN0UxDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
Stephen Warren wrote at Friday, February 04, 2011 1:32 PM:
> Stephen Warren wrote at Thursday, February 03, 2011 4:25 PM:
> >
> > Mark Brown wrote at Thursday, February 03, 2011 3:36 PM:
> > > On Thu, Feb 03, 2011 at 01:56:13PM -0700, Stephen Warren wrote:
> > >
> > > > +static struct snd_soc_jack harmony_hp_jack;
> > > > +
> > >
> > > Since you've changed to using a platform device you should really be
> > > dynamically allocating this I guess. But this isn't actually a
> > > practical problem so not worth caring about.
> >
> > Uggh. The code may as well be consistent. I'll fix this up and resubmit
> > if you haven't already applied it.
>
> Hmm. Looking at this a bit more, solving it fully is kinda nasty; I'd have
> to move not only that jack definition, but also all the pins and gpios
> into struct tegra_harmony, since snd_soc_jack_add_{pins,gpios} modify all
> of those structures. But, there would still have to be static const
> "template" copies of those data structures to initialize the copies in
> struct tegra_harmony.
>
> The same thing then applies to some of the subsequent changes, for the
> mic jacks etc.
>
> That seems like a lot of overhead, both code-wise, and runtime space-wise,
> to solve a problem that as you mention isn't a practical concern.
Mark, I'm happy to go either way on this; the SW engineer in me doesn't like
non-const globals and inconsistency with the rest of the state data, but
equally fixing this seems like it would bloat the code and might make it
less readable.
Let me know which way you'd prefer it to go.
Thanks.
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^ permalink raw reply
* Re: [RFC 1/5] ARM: P2V: separate PHYS_OFFSET from platform definitions
From: Wan ZongShun @ 2011-02-08 11:22 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Viresh Kumar, Srinidhi Kasagar, Kevin Hilman, Anton Vorontsov,
Lennert Buytenhek, Kukjin Kim, Erik Gilling, linux-sh,
Vincent Sanders, Hans J. Koch, Magnus Damm, Marc Singer,
Tony Lindgren, David Brown, Alessandro Rubini, Jiandong Zheng,
linux-arm-msm, Olof Johansson, Ryan Mallon, linux-samsung-soc,
Ben Dooks, linux-tegra, linux-omap, linux-arm-kernel, Daniel
In-Reply-To: <E1PaDOb-00023Z-CR@rmk-PC.arm.linux.org.uk>
2011/1/5 Russell King - ARM Linux <linux@arm.linux.org.uk>:
> This uncouple PHYS_OFFSET from the platform definitions, thereby
> facilitating run-time computation of the physical memory offset.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
> arch/arm/include/asm/memory.h | 2 ++
> arch/arm/kernel/tcm.c | 2 +-
> arch/arm/mach-aaec2000/include/mach/memory.h | 2 +-
> arch/arm/mach-at91/include/mach/memory.h | 2 +-
> arch/arm/mach-bcmring/include/mach/hardware.h | 2 +-
> arch/arm/mach-bcmring/include/mach/memory.h | 2 +-
> arch/arm/mach-clps711x/include/mach/memory.h | 2 +-
> arch/arm/mach-cns3xxx/include/mach/memory.h | 2 +-
> arch/arm/mach-davinci/include/mach/memory.h | 4 ++--
> arch/arm/mach-dove/include/mach/memory.h | 2 +-
> arch/arm/mach-ebsa110/include/mach/memory.h | 2 +-
> arch/arm/mach-ep93xx/include/mach/memory.h | 10 +++++-----
> arch/arm/mach-footbridge/include/mach/memory.h | 2 +-
> arch/arm/mach-h720x/include/mach/memory.h | 2 +-
> arch/arm/mach-integrator/include/mach/memory.h | 2 +-
> arch/arm/mach-iop13xx/include/mach/memory.h | 2 +-
> arch/arm/mach-iop32x/include/mach/memory.h | 2 +-
> arch/arm/mach-iop33x/include/mach/memory.h | 2 +-
> arch/arm/mach-ixp2000/include/mach/memory.h | 2 +-
> arch/arm/mach-ixp23xx/include/mach/memory.h | 2 +-
> arch/arm/mach-ixp4xx/include/mach/memory.h | 2 +-
> arch/arm/mach-kirkwood/include/mach/memory.h | 2 +-
> arch/arm/mach-ks8695/include/mach/memory.h | 2 +-
> arch/arm/mach-lh7a40x/include/mach/memory.h | 2 +-
> arch/arm/mach-loki/include/mach/memory.h | 2 +-
> arch/arm/mach-lpc32xx/include/mach/memory.h | 2 +-
> arch/arm/mach-mmp/include/mach/memory.h | 2 +-
> arch/arm/mach-msm/board-msm7x30.c | 2 +-
> arch/arm/mach-msm/include/mach/memory.h | 10 +++++-----
> arch/arm/mach-mv78xx0/include/mach/memory.h | 2 +-
> arch/arm/mach-mx3/mach-kzm_arm11_01.c | 2 +-
> arch/arm/mach-netx/include/mach/memory.h | 2 +-
> arch/arm/mach-nomadik/include/mach/memory.h | 2 +-
> arch/arm/mach-ns9xxx/include/mach/memory.h | 2 +-
> arch/arm/mach-nuc93x/include/mach/memory.h | 2 +-
> arch/arm/mach-orion5x/include/mach/memory.h | 2 +-
> arch/arm/mach-pnx4008/include/mach/memory.h | 2 +-
> arch/arm/mach-pxa/include/mach/memory.h | 2 +-
> arch/arm/mach-realview/include/mach/memory.h | 4 ++--
> arch/arm/mach-rpc/include/mach/memory.h | 2 +-
> arch/arm/mach-s3c2400/include/mach/memory.h | 2 +-
> arch/arm/mach-s3c2410/include/mach/memory.h | 2 +-
> arch/arm/mach-s3c24a0/include/mach/memory.h | 2 +-
> arch/arm/mach-s3c64xx/include/mach/memory.h | 2 +-
> arch/arm/mach-s5p6442/include/mach/memory.h | 2 +-
> arch/arm/mach-s5p64x0/include/mach/memory.h | 2 +-
> arch/arm/mach-s5pc100/include/mach/memory.h | 2 +-
> arch/arm/mach-s5pv210/include/mach/memory.h | 2 +-
> arch/arm/mach-s5pv310/include/mach/memory.h | 2 +-
> arch/arm/mach-sa1100/include/mach/memory.h | 2 +-
> arch/arm/mach-shark/include/mach/memory.h | 2 +-
> arch/arm/mach-shmobile/include/mach/memory.h | 2 +-
> arch/arm/mach-tegra/include/mach/memory.h | 2 +-
> arch/arm/mach-u300/include/mach/memory.h | 6 +++---
> arch/arm/mach-u300/u300.c | 2 +-
> arch/arm/mach-ux500/include/mach/memory.h | 2 +-
> arch/arm/mach-versatile/include/mach/memory.h | 2 +-
> arch/arm/mach-vexpress/include/mach/memory.h | 2 +-
> arch/arm/mach-w90x900/include/mach/memory.h | 2 +-
> arch/arm/plat-omap/include/plat/memory.h | 4 ++--
> arch/arm/plat-spear/include/plat/memory.h | 2 +-
> arch/arm/plat-stmp3xxx/include/mach/memory.h | 2 +-
> arch/arm/plat-tcc/include/mach/memory.h | 2 +-
> 63 files changed, 77 insertions(+), 75 deletions(-)
>
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 23c2e8e..00b04ae 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -24,6 +24,8 @@
> */
> #define UL(x) _AC(x, UL)
>
> +#define PHYS_OFFSET PLAT_PHYS_OFFSET
> +
> #ifdef CONFIG_MMU
>
> /*
> diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
> index 26685c2..f5cf660 100644
> --- a/arch/arm/kernel/tcm.c
> +++ b/arch/arm/kernel/tcm.c
> @@ -15,7 +15,7 @@
> #include <linux/string.h> /* memcpy */
> #include <asm/cputype.h>
> #include <asm/mach/map.h>
> -#include <mach/memory.h>
> +#include <asm/memory.h>
> #include "tcm.h"
>
> static struct gen_pool *tcm_pool;
> diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h
> index 4f93c56..4a10bf0 100644
> --- a/arch/arm/mach-aaec2000/include/mach/memory.h
> +++ b/arch/arm/mach-aaec2000/include/mach/memory.h
> @@ -12,6 +12,6 @@
> #define __ASM_ARCH_MEMORY_H
>
>
> -#define PHYS_OFFSET UL(0xf0000000)
> +#define PLAT_PHYS_OFFSET UL(0xf0000000)
>
> #endif /* __ASM_ARCH_MEMORY_H */
> diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h
> index 14f4ef4..c2cfe50 100644
> --- a/arch/arm/mach-at91/include/mach/memory.h
> +++ b/arch/arm/mach-at91/include/mach/memory.h
> @@ -23,6 +23,6 @@
>
> #include <mach/hardware.h>
>
> -#define PHYS_OFFSET (AT91_SDRAM_BASE)
> +#define PLAT_PHYS_OFFSET (AT91_SDRAM_BASE)
>
> #endif
> diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
> index 447eb34..8bf3564 100644
> --- a/arch/arm/mach-bcmring/include/mach/hardware.h
> +++ b/arch/arm/mach-bcmring/include/mach/hardware.h
> @@ -31,7 +31,7 @@
> * *_SIZE is the size of the region
> * *_BASE is the virtual address
> */
> -#define RAM_START PHYS_OFFSET
> +#define RAM_START PLAT_PHYS_OFFSET
>
> #define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
> #define RAM_BASE PAGE_OFFSET
> diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h
> index 114f942..15162e4 100644
> --- a/arch/arm/mach-bcmring/include/mach/memory.h
> +++ b/arch/arm/mach-bcmring/include/mach/memory.h
> @@ -23,7 +23,7 @@
> * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
> */
>
> -#define PHYS_OFFSET CFG_GLOBAL_RAM_BASE
> +#define PLAT_PHYS_OFFSET CFG_GLOBAL_RAM_BASE
>
> /*
> * Maximum DMA memory allowed is 14M
> diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
> index f45c8e8..3a032a6 100644
> --- a/arch/arm/mach-clps711x/include/mach/memory.h
> +++ b/arch/arm/mach-clps711x/include/mach/memory.h
> @@ -23,7 +23,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0xc0000000)
> +#define PLAT_PHYS_OFFSET UL(0xc0000000)
>
> #if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12)
>
> diff --git a/arch/arm/mach-cns3xxx/include/mach/memory.h b/arch/arm/mach-cns3xxx/include/mach/memory.h
> index 3b6b769..dc16c5c 100644
> --- a/arch/arm/mach-cns3xxx/include/mach/memory.h
> +++ b/arch/arm/mach-cns3xxx/include/mach/memory.h
> @@ -13,7 +13,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #define __phys_to_bus(x) ((x) + PHYS_OFFSET)
> #define __bus_to_phys(x) ((x) - PHYS_OFFSET)
> diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
> index 22eb97c..7882272 100644
> --- a/arch/arm/mach-davinci/include/mach/memory.h
> +++ b/arch/arm/mach-davinci/include/mach/memory.h
> @@ -26,9 +26,9 @@
> #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
> #error Cannot enable DaVinci and DA8XX platforms concurrently
> #elif defined(CONFIG_ARCH_DAVINCI_DA8XX)
> -#define PHYS_OFFSET DA8XX_DDR_BASE
> +#define PLAT_PHYS_OFFSET DA8XX_DDR_BASE
> #else
> -#define PHYS_OFFSET DAVINCI_DDR_BASE
> +#define PLAT_PHYS_OFFSET DAVINCI_DDR_BASE
> #endif
>
> #define DDR2_SDRCR_OFFSET 0xc
> diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h
> index d668720..bbc93fe 100644
> --- a/arch/arm/mach-dove/include/mach/memory.h
> +++ b/arch/arm/mach-dove/include/mach/memory.h
> @@ -5,6 +5,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-ebsa110/include/mach/memory.h b/arch/arm/mach-ebsa110/include/mach/memory.h
> index 0ca66d0..8e49066 100644
> --- a/arch/arm/mach-ebsa110/include/mach/memory.h
> +++ b/arch/arm/mach-ebsa110/include/mach/memory.h
> @@ -19,7 +19,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> /*
> * Cache flushing area - SRAM
> diff --git a/arch/arm/mach-ep93xx/include/mach/memory.h b/arch/arm/mach-ep93xx/include/mach/memory.h
> index 554064e..c9400cf 100644
> --- a/arch/arm/mach-ep93xx/include/mach/memory.h
> +++ b/arch/arm/mach-ep93xx/include/mach/memory.h
> @@ -6,15 +6,15 @@
> #define __ASM_ARCH_MEMORY_H
>
> #if defined(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
> #elif defined(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)
> -#define PHYS_OFFSET UL(0xc0000000)
> +#define PLAT_PHYS_OFFSET UL(0xc0000000)
> #elif defined(CONFIG_EP93XX_SDCE1_PHYS_OFFSET)
> -#define PHYS_OFFSET UL(0xd0000000)
> +#define PLAT_PHYS_OFFSET UL(0xd0000000)
> #elif defined(CONFIG_EP93XX_SDCE2_PHYS_OFFSET)
> -#define PHYS_OFFSET UL(0xe0000000)
> +#define PLAT_PHYS_OFFSET UL(0xe0000000)
> #elif defined(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET)
> -#define PHYS_OFFSET UL(0xf0000000)
> +#define PLAT_PHYS_OFFSET UL(0xf0000000)
> #else
> #error "Kconfig bug: No EP93xx PHYS_OFFSET set"
> #endif
> diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h
> index 8d64f45..5c6df37 100644
> --- a/arch/arm/mach-footbridge/include/mach/memory.h
> +++ b/arch/arm/mach-footbridge/include/mach/memory.h
> @@ -62,7 +62,7 @@ extern unsigned long __bus_to_pfn(unsigned long);
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #define FLUSH_BASE_PHYS 0x50000000
>
> diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h
> index ef4c1e2..9d36876 100644
> --- a/arch/arm/mach-h720x/include/mach/memory.h
> +++ b/arch/arm/mach-h720x/include/mach/memory.h
> @@ -7,7 +7,7 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x40000000)
> +#define PLAT_PHYS_OFFSET UL(0x40000000)
> /*
> * This is the maximum DMA address that can be DMAd to.
> * There should not be more than (0xd0000000 - 0xc0000000)
> diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h
> index 991f24d..334d5e2 100644
> --- a/arch/arm/mach-integrator/include/mach/memory.h
> +++ b/arch/arm/mach-integrator/include/mach/memory.h
> @@ -23,7 +23,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #define BUS_OFFSET UL(0x80000000)
> #define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET)
> diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
> index 3ad4553..1afa99e 100644
> --- a/arch/arm/mach-iop13xx/include/mach/memory.h
> +++ b/arch/arm/mach-iop13xx/include/mach/memory.h
> @@ -6,7 +6,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #ifndef __ASSEMBLY__
>
> diff --git a/arch/arm/mach-iop32x/include/mach/memory.h b/arch/arm/mach-iop32x/include/mach/memory.h
> index c30f645..169cc23 100644
> --- a/arch/arm/mach-iop32x/include/mach/memory.h
> +++ b/arch/arm/mach-iop32x/include/mach/memory.h
> @@ -8,6 +8,6 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0xa0000000)
> +#define PLAT_PHYS_OFFSET UL(0xa0000000)
>
> #endif
> diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h
> index a30a96a..8e1daf7 100644
> --- a/arch/arm/mach-iop33x/include/mach/memory.h
> +++ b/arch/arm/mach-iop33x/include/mach/memory.h
> @@ -8,6 +8,6 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h
> index 98e3471..5f0c4fd 100644
> --- a/arch/arm/mach-ixp2000/include/mach/memory.h
> +++ b/arch/arm/mach-ixp2000/include/mach/memory.h
> @@ -13,7 +13,7 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #include <mach/ixp2000-regs.h>
>
> diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h
> index 6ef65d8..6cf0704 100644
> --- a/arch/arm/mach-ixp23xx/include/mach/memory.h
> +++ b/arch/arm/mach-ixp23xx/include/mach/memory.h
> @@ -17,7 +17,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET (0x00000000)
> +#define PLAT_PHYS_OFFSET (0x00000000)
>
> #define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)
>
> diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
> index 0136eaa..6d388c9 100644
> --- a/arch/arm/mach-ixp4xx/include/mach/memory.h
> +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
> @@ -12,7 +12,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
>
> diff --git a/arch/arm/mach-kirkwood/include/mach/memory.h b/arch/arm/mach-kirkwood/include/mach/memory.h
> index 45431e1..4600b44 100644
> --- a/arch/arm/mach-kirkwood/include/mach/memory.h
> +++ b/arch/arm/mach-kirkwood/include/mach/memory.h
> @@ -5,6 +5,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
> index bace9a6..f7e1b9b 100644
> --- a/arch/arm/mach-ks8695/include/mach/memory.h
> +++ b/arch/arm/mach-ks8695/include/mach/memory.h
> @@ -18,7 +18,7 @@
> /*
> * Physical SRAM offset.
> */
> -#define PHYS_OFFSET KS8695_SDRAM_PA
> +#define PLAT_PHYS_OFFSET KS8695_SDRAM_PA
>
> #ifndef __ASSEMBLY__
>
> diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
> index edb8f5f..f77bde8 100644
> --- a/arch/arm/mach-lh7a40x/include/mach/memory.h
> +++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
> @@ -17,7 +17,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0xc0000000)
> +#define PLAT_PHYS_OFFSET UL(0xc0000000)
>
> /*
> * Sparsemem version of the above
> diff --git a/arch/arm/mach-loki/include/mach/memory.h b/arch/arm/mach-loki/include/mach/memory.h
> index 2ed7e6e..6636665 100644
> --- a/arch/arm/mach-loki/include/mach/memory.h
> +++ b/arch/arm/mach-loki/include/mach/memory.h
> @@ -5,6 +5,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h
> index 044e1ac..a647dd6 100644
> --- a/arch/arm/mach-lpc32xx/include/mach/memory.h
> +++ b/arch/arm/mach-lpc32xx/include/mach/memory.h
> @@ -22,6 +22,6 @@
> /*
> * Physical DRAM offset of bank 0
> */
> -#define PHYS_OFFSET UL(0x80000000)
> +#define PLAT_PHYS_OFFSET UL(0x80000000)
>
> #endif
> diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h
> index bdb21d7..d68b50a 100644
> --- a/arch/arm/mach-mmp/include/mach/memory.h
> +++ b/arch/arm/mach-mmp/include/mach/memory.h
> @@ -9,6 +9,6 @@
> #ifndef __ASM_MACH_MEMORY_H
> #define __ASM_MACH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif /* __ASM_MACH_MEMORY_H */
> diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
> index 05241df..1931e07 100644
> --- a/arch/arm/mach-msm/board-msm7x30.c
> +++ b/arch/arm/mach-msm/board-msm7x30.c
> @@ -25,11 +25,11 @@
>
> #include <asm/mach-types.h>
> #include <asm/mach/arch.h>
> +#include <asm/memory.h>
> #include <asm/setup.h>
>
> #include <mach/gpio.h>
> #include <mach/board.h>
> -#include <mach/memory.h>
> #include <mach/msm_iomap.h>
> #include <mach/dma.h>
>
> diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> index 070e17d..176875d 100644
> --- a/arch/arm/mach-msm/include/mach/memory.h
> +++ b/arch/arm/mach-msm/include/mach/memory.h
> @@ -18,15 +18,15 @@
>
> /* physical offset of RAM */
> #if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A)
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
> #elif defined(CONFIG_ARCH_QSD8X50)
> -#define PHYS_OFFSET UL(0x20000000)
> +#define PLAT_PHYS_OFFSET UL(0x20000000)
> #elif defined(CONFIG_ARCH_MSM7X30)
> -#define PHYS_OFFSET UL(0x00200000)
> +#define PLAT_PHYS_OFFSET UL(0x00200000)
> #elif defined(CONFIG_ARCH_MSM8X60)
> -#define PHYS_OFFSET UL(0x40200000)
> +#define PLAT_PHYS_OFFSET UL(0x40200000)
> #else
> -#define PHYS_OFFSET UL(0x10000000)
> +#define PLAT_PHYS_OFFSET UL(0x10000000)
> #endif
>
> #endif
> diff --git a/arch/arm/mach-mv78xx0/include/mach/memory.h b/arch/arm/mach-mv78xx0/include/mach/memory.h
> index e663042..a648c51 100644
> --- a/arch/arm/mach-mv78xx0/include/mach/memory.h
> +++ b/arch/arm/mach-mv78xx0/include/mach/memory.h
> @@ -5,6 +5,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
> index 042cd56..d8ebde8 100644
> --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
> +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
> @@ -27,6 +27,7 @@
>
> #include <asm/irq.h>
> #include <asm/mach-types.h>
> +#include <asm/memory.h>
> #include <asm/setup.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/irq.h>
> @@ -36,7 +37,6 @@
> #include <mach/clock.h>
> #include <mach/common.h>
> #include <mach/iomux-mx3.h>
> -#include <mach/memory.h>
>
> #include "devices-imx31.h"
> #include "devices.h"
> diff --git a/arch/arm/mach-netx/include/mach/memory.h b/arch/arm/mach-netx/include/mach/memory.h
> index 9a363f2..5956149 100644
> --- a/arch/arm/mach-netx/include/mach/memory.h
> +++ b/arch/arm/mach-netx/include/mach/memory.h
> @@ -20,7 +20,7 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x80000000)
> +#define PLAT_PHYS_OFFSET UL(0x80000000)
>
> #endif
>
> diff --git a/arch/arm/mach-nomadik/include/mach/memory.h b/arch/arm/mach-nomadik/include/mach/memory.h
> index 1e5689d..d332521 100644
> --- a/arch/arm/mach-nomadik/include/mach/memory.h
> +++ b/arch/arm/mach-nomadik/include/mach/memory.h
> @@ -23,6 +23,6 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h
> index 6107193..5c65aee 100644
> --- a/arch/arm/mach-ns9xxx/include/mach/memory.h
> +++ b/arch/arm/mach-ns9xxx/include/mach/memory.h
> @@ -19,6 +19,6 @@
> #define NS9XXX_CS2STAT_LENGTH UL(0x1000)
> #define NS9XXX_CS3STAT_LENGTH UL(0x1000)
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-nuc93x/include/mach/memory.h b/arch/arm/mach-nuc93x/include/mach/memory.h
> index 323ab0d..ef9864b 100644
> --- a/arch/arm/mach-nuc93x/include/mach/memory.h
> +++ b/arch/arm/mach-nuc93x/include/mach/memory.h
> @@ -16,6 +16,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h
> index 52a2955..6769917 100644
> --- a/arch/arm/mach-orion5x/include/mach/memory.h
> +++ b/arch/arm/mach-orion5x/include/mach/memory.h
> @@ -7,6 +7,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-pnx4008/include/mach/memory.h b/arch/arm/mach-pnx4008/include/mach/memory.h
> index 0e87700..1275db6 100644
> --- a/arch/arm/mach-pnx4008/include/mach/memory.h
> +++ b/arch/arm/mach-pnx4008/include/mach/memory.h
> @@ -16,6 +16,6 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x80000000)
> +#define PLAT_PHYS_OFFSET UL(0x80000000)
>
> #endif
> diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
> index 92361a6..7f68724 100644
> --- a/arch/arm/mach-pxa/include/mach/memory.h
> +++ b/arch/arm/mach-pxa/include/mach/memory.h
> @@ -15,7 +15,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0xa0000000)
> +#define PLAT_PHYS_OFFSET UL(0xa0000000)
>
> #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
> void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes);
> diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
> index 5dafc15..e05fc2c 100644
> --- a/arch/arm/mach-realview/include/mach/memory.h
> +++ b/arch/arm/mach-realview/include/mach/memory.h
> @@ -24,9 +24,9 @@
> * Physical DRAM offset.
> */
> #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
> -#define PHYS_OFFSET UL(0x70000000)
> +#define PLAT_PHYS_OFFSET UL(0x70000000)
> #else
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
> #endif
>
> #if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA)
> diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h
> index 78191bf..18a2210 100644
> --- a/arch/arm/mach-rpc/include/mach/memory.h
> +++ b/arch/arm/mach-rpc/include/mach/memory.h
> @@ -21,7 +21,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x10000000)
> +#define PLAT_PHYS_OFFSET UL(0x10000000)
>
> /*
> * Cache flushing area - ROM
> diff --git a/arch/arm/mach-s3c2400/include/mach/memory.h b/arch/arm/mach-s3c2400/include/mach/memory.h
> index cf5901f..3f33670 100644
> --- a/arch/arm/mach-s3c2400/include/mach/memory.h
> +++ b/arch/arm/mach-s3c2400/include/mach/memory.h
> @@ -15,6 +15,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x0C000000)
> +#define PLAT_PHYS_OFFSET UL(0x0C000000)
>
> #endif
> diff --git a/arch/arm/mach-s3c2410/include/mach/memory.h b/arch/arm/mach-s3c2410/include/mach/memory.h
> index 6f1e587..f92b97b 100644
> --- a/arch/arm/mach-s3c2410/include/mach/memory.h
> +++ b/arch/arm/mach-s3c2410/include/mach/memory.h
> @@ -11,6 +11,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x30000000)
> +#define PLAT_PHYS_OFFSET UL(0x30000000)
>
> #endif
> diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h
> index 7d74fd5..7d208a7 100644
> --- a/arch/arm/mach-s3c24a0/include/mach/memory.h
> +++ b/arch/arm/mach-s3c24a0/include/mach/memory.h
> @@ -11,7 +11,7 @@
> #ifndef __ASM_ARCH_24A0_MEMORY_H
> #define __ASM_ARCH_24A0_MEMORY_H __FILE__
>
> -#define PHYS_OFFSET UL(0x10000000)
> +#define PLAT_PHYS_OFFSET UL(0x10000000)
>
> #define __virt_to_bus(x) __virt_to_phys(x)
> #define __bus_to_virt(x) __phys_to_virt(x)
> diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h
> index 42cc54e..4760cda 100644
> --- a/arch/arm/mach-s3c64xx/include/mach/memory.h
> +++ b/arch/arm/mach-s3c64xx/include/mach/memory.h
> @@ -13,7 +13,7 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x50000000)
> +#define PLAT_PHYS_OFFSET UL(0x50000000)
>
> #define CONSISTENT_DMA_SIZE SZ_8M
>
> diff --git a/arch/arm/mach-s5p6442/include/mach/memory.h b/arch/arm/mach-s5p6442/include/mach/memory.h
> index 9ddd877..cfe259d 100644
> --- a/arch/arm/mach-s5p6442/include/mach/memory.h
> +++ b/arch/arm/mach-s5p6442/include/mach/memory.h
> @@ -13,7 +13,7 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x20000000)
> +#define PLAT_PHYS_OFFSET UL(0x20000000)
> #define CONSISTENT_DMA_SIZE SZ_8M
>
> #endif /* __ASM_ARCH_MEMORY_H */
> diff --git a/arch/arm/mach-s5p64x0/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h
> index 1b036b0..365a6eb 100644
> --- a/arch/arm/mach-s5p64x0/include/mach/memory.h
> +++ b/arch/arm/mach-s5p64x0/include/mach/memory.h
> @@ -13,7 +13,7 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H __FILE__
>
> -#define PHYS_OFFSET UL(0x20000000)
> +#define PLAT_PHYS_OFFSET UL(0x20000000)
> #define CONSISTENT_DMA_SIZE SZ_8M
>
> #endif /* __ASM_ARCH_MEMORY_H */
> diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h
> index 4b60d18..bda4e79 100644
> --- a/arch/arm/mach-s5pc100/include/mach/memory.h
> +++ b/arch/arm/mach-s5pc100/include/mach/memory.h
> @@ -13,6 +13,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x20000000)
> +#define PLAT_PHYS_OFFSET UL(0x20000000)
>
> #endif
> diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h
> index d503e0c..7b5fcf0 100644
> --- a/arch/arm/mach-s5pv210/include/mach/memory.h
> +++ b/arch/arm/mach-s5pv210/include/mach/memory.h
> @@ -13,7 +13,7 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x20000000)
> +#define PLAT_PHYS_OFFSET UL(0x20000000)
> #define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M)
>
> /*
> diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-s5pv310/include/mach/memory.h
> index 1dffb48..470b01b 100644
> --- a/arch/arm/mach-s5pv310/include/mach/memory.h
> +++ b/arch/arm/mach-s5pv310/include/mach/memory.h
> @@ -13,7 +13,7 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H __FILE__
>
> -#define PHYS_OFFSET UL(0x40000000)
> +#define PLAT_PHYS_OFFSET UL(0x40000000)
>
> /* Maximum of 256MiB in one bank */
> #define MAX_PHYSMEM_BITS 32
> diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
> index 128a1df..a44da6a 100644
> --- a/arch/arm/mach-sa1100/include/mach/memory.h
> +++ b/arch/arm/mach-sa1100/include/mach/memory.h
> @@ -12,7 +12,7 @@
> /*
> * Physical DRAM offset is 0xc0000000 on the SA1100
> */
> -#define PHYS_OFFSET UL(0xc0000000)
> +#define PLAT_PHYS_OFFSET UL(0xc0000000)
>
> #ifndef __ASSEMBLY__
>
> diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
> index d9c4812..9afb170 100644
> --- a/arch/arm/mach-shark/include/mach/memory.h
> +++ b/arch/arm/mach-shark/include/mach/memory.h
> @@ -15,7 +15,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x08000000)
> +#define PLAT_PHYS_OFFSET UL(0x08000000)
>
> #ifndef __ASSEMBLY__
>
> diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h
> index 377584e..ad00c3c 100644
> --- a/arch/arm/mach-shmobile/include/mach/memory.h
> +++ b/arch/arm/mach-shmobile/include/mach/memory.h
> @@ -1,7 +1,7 @@
> #ifndef __ASM_MACH_MEMORY_H
> #define __ASM_MACH_MEMORY_H
>
> -#define PHYS_OFFSET UL(CONFIG_MEMORY_START)
> +#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START)
> #define MEM_SIZE UL(CONFIG_MEMORY_SIZE)
>
> /* DMA memory at 0xf6000000 - 0xffdfffff */
> diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
> index 6151bab..537db3a 100644
> --- a/arch/arm/mach-tegra/include/mach/memory.h
> +++ b/arch/arm/mach-tegra/include/mach/memory.h
> @@ -22,7 +22,7 @@
> #define __MACH_TEGRA_MEMORY_H
>
> /* physical offset of RAM */
> -#define PHYS_OFFSET UL(0)
> +#define PLAT_PHYS_OFFSET UL(0)
>
> #endif
>
> diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
> index bf134bc..888e2e3 100644
> --- a/arch/arm/mach-u300/include/mach/memory.h
> +++ b/arch/arm/mach-u300/include/mach/memory.h
> @@ -15,17 +15,17 @@
>
> #ifdef CONFIG_MACH_U300_DUAL_RAM
>
> -#define PHYS_OFFSET UL(0x48000000)
> +#define PLAT_PHYS_OFFSET UL(0x48000000)
> #define BOOT_PARAMS_OFFSET (PHYS_OFFSET + 0x100)
>
> #else
>
> #ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
> -#define PHYS_OFFSET (0x28000000 + \
> +#define PLAT_PHYS_OFFSET (0x28000000 + \
> (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \
> (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
> #else
> -#define PHYS_OFFSET (0x28000000 + \
> +#define PLAT_PHYS_OFFSET (0x28000000 + \
> (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
> (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
> #endif
> diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
> index 07c35a8..48b3b7f 100644
> --- a/arch/arm/mach-u300/u300.c
> +++ b/arch/arm/mach-u300/u300.c
> @@ -19,9 +19,9 @@
> #include <linux/io.h>
> #include <mach/hardware.h>
> #include <mach/platform.h>
> -#include <mach/memory.h>
> #include <asm/mach-types.h>
> #include <asm/mach/arch.h>
> +#include <asm/memory.h>
>
> static void __init u300_reserve(void)
> {
> diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h
> index 510571a..2ef697a 100644
> --- a/arch/arm/mach-ux500/include/mach/memory.h
> +++ b/arch/arm/mach-ux500/include/mach/memory.h
> @@ -12,7 +12,7 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
> #define BUS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-versatile/include/mach/memory.h b/arch/arm/mach-versatile/include/mach/memory.h
> index 79aeab8..dacc9d8 100644
> --- a/arch/arm/mach-versatile/include/mach/memory.h
> +++ b/arch/arm/mach-versatile/include/mach/memory.h
> @@ -23,6 +23,6 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/mach-vexpress/include/mach/memory.h b/arch/arm/mach-vexpress/include/mach/memory.h
> index be28232..5b7fcd4 100644
> --- a/arch/arm/mach-vexpress/include/mach/memory.h
> +++ b/arch/arm/mach-vexpress/include/mach/memory.h
> @@ -20,6 +20,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x60000000)
> +#define PLAT_PHYS_OFFSET UL(0x60000000)
>
> #endif
> diff --git a/arch/arm/mach-w90x900/include/mach/memory.h b/arch/arm/mach-w90x900/include/mach/memory.h
> index 971b807..f02905b 100644
> --- a/arch/arm/mach-w90x900/include/mach/memory.h
> +++ b/arch/arm/mach-w90x900/include/mach/memory.h
> @@ -18,6 +18,6 @@
> #ifndef __ASM_ARCH_MEMORY_H
> #define __ASM_ARCH_MEMORY_H
>
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif
> diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
> index f8d922f..e6720aa 100644
> --- a/arch/arm/plat-omap/include/plat/memory.h
> +++ b/arch/arm/plat-omap/include/plat/memory.h
> @@ -37,9 +37,9 @@
> * Physical DRAM offset.
> */
> #if defined(CONFIG_ARCH_OMAP1)
> -#define PHYS_OFFSET UL(0x10000000)
> +#define PLAT_PHYS_OFFSET UL(0x10000000)
> #else
> -#define PHYS_OFFSET UL(0x80000000)
> +#define PLAT_PHYS_OFFSET UL(0x80000000)
> #endif
>
> /*
> diff --git a/arch/arm/plat-spear/include/plat/memory.h b/arch/arm/plat-spear/include/plat/memory.h
> index 27a4aba..7e3599e 100644
> --- a/arch/arm/plat-spear/include/plat/memory.h
> +++ b/arch/arm/plat-spear/include/plat/memory.h
> @@ -15,6 +15,6 @@
> #define __PLAT_MEMORY_H
>
> /* Physical DRAM offset */
> -#define PHYS_OFFSET UL(0x00000000)
> +#define PLAT_PHYS_OFFSET UL(0x00000000)
>
> #endif /* __PLAT_MEMORY_H */
> diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h
> index 7b875a0..61fa548 100644
> --- a/arch/arm/plat-stmp3xxx/include/mach/memory.h
> +++ b/arch/arm/plat-stmp3xxx/include/mach/memory.h
> @@ -17,6 +17,6 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x40000000)
> +#define PLAT_PHYS_OFFSET UL(0x40000000)
>
> #endif
> diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h
> index cd91ba8..28a6e0c 100644
> --- a/arch/arm/plat-tcc/include/mach/memory.h
> +++ b/arch/arm/plat-tcc/include/mach/memory.h
> @@ -13,6 +13,6 @@
> /*
> * Physical DRAM offset.
> */
> -#define PHYS_OFFSET UL(0x20000000)
> +#define PLAT_PHYS_OFFSET UL(0x20000000)
>
> #endif
> --
> 1.6.2.5
>
>
Acked-by: Wan ZongShun <mcuos.com@gmail.com>
Thanks!
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^ permalink raw reply
* RE: [PATCH] [ARM] tegra: Add i2c support
From: Stephen Warren @ 2011-02-07 17:45 UTC (permalink / raw)
To: Ben Dooks (embedded platforms), Colin Cross
Cc: mike-UTxiZqZC01RS1MOuV/RT9w@public.gmane.org,
gadiyar-l0cyMroinI0@public.gmane.org,
Jean Delvare (PC drivers, core),
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <AANLkTimYURYGix-0Xk3wdf1A-XEAJbBXR_JDn1BFw_uq@mail.gmail.com>
Stephen Warren wrote at Sent: Monday, January 31, 2011 3:49 PM:
>
> Colin Cross wrote at Tuesday, December 21, 2010 5:12 PM:
> >
> > On Thu, Sep 2, 2010 at 3:21 PM, Colin Cross <ccross-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org> wrote:
> > > Signed-off-by: Colin Cross <ccross-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
> > > ---
> > > drivers/i2c/busses/Kconfig | 7 +
> > > drivers/i2c/busses/Makefile | 1 +
> > > drivers/i2c/busses/i2c-tegra.c | 665 ++++++++++++++++++++++++++++++++++++++++
> > > include/linux/i2c-tegra.h | 25 ++
> > > 4 files changed, 698 insertions(+), 0 deletions(-)
> > > create mode 100644 drivers/i2c/busses/i2c-tegra.c
> > > create mode 100644 include/linux/i2c-tegra.h
> > >
> > Ben, this didn't make it into 2.6.37? Can it go into next-i2c?
>
> I didn't see any response to this request, at least not in the linux-tegra
> archives.
Ben, did Colin's latest patch look good; could it be applied?
Colin, perhaps you could repost the patch in case it's fallen out of Ben's
inbox.
As background, I'd really like this patch to show up in 2.6.39; the ASoC
driver I've upstreamed for Tegra Harmony (and which will be in 2.6.39) relies
on this I2C driver to provide communication with the audio codec. Hence, the
ASoC driver is useless without the I2C driver also merged.
Thanks.
--
nvpublic
^ permalink raw reply
* Re: [RFC 1/5] ARM: P2V: separate PHYS_OFFSET from platform definitions
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-02-07 16:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Viresh Kumar, Srinidhi Kasagar, Kevin Hilman, Anton Vorontsov,
Lennert Buytenhek, Kukjin Kim, linux-sh, Vincent Sanders,
Hans J. Koch, Magnus Damm, Scott Branden, Marc Singer,
Tony Lindgren, David Brown, Alessandro Rubini, Sascha Hauer,
Wan ZongShun, linux-arm-msm, STEricsson, Ryan Mallon,
linux-samsung-soc, Ben Dooks, linux-tegra, linux-omap
In-Reply-To: <E1PaDOb-00023Z-CR@rmk-PC.arm.linux.org.uk>
On 20:22 Tue 04 Jan , Russell King - ARM Linux wrote:
> This uncouple PHYS_OFFSET from the platform definitions, thereby
> facilitating run-time computation of the physical memory offset.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
> arch/arm/include/asm/memory.h | 2 ++
> arch/arm/kernel/tcm.c | 2 +-
> arch/arm/mach-aaec2000/include/mach/memory.h | 2 +-
> arch/arm/mach-at91/include/mach/memory.h | 2 +-
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Best Regards,
J.
^ permalink raw reply
* Re: [RFC 1/5] ARM: P2V: separate PHYS_OFFSET from platform definitions
From: Tony Lindgren @ 2011-02-07 15:57 UTC (permalink / raw)
To: Magnus Damm
Cc: Viresh Kumar, Srinidhi Kasagar, Kevin Hilman, Anton Vorontsov,
Lennert Buytenhek, Kukjin Kim, Russell King - ARM Linux,
Erik Gilling, linux-sh, Vincent Sanders, Hans J. Koch,
Marc Singer, David Brown, Alessandro Rubini, Jiandong Zheng,
Wan ZongShun, linux-arm-msm, Olof Johansson, Ryan Mallon,
linux-samsung-soc, Ben Dooks, linux-tegra, linux-omap,
linux-arm-kernel
In-Reply-To: <AANLkTi=qtRP1tAs1wPnGugE2rGBTERgHuUKKBWhbs=ST@mail.gmail.com>
* Magnus Damm <magnus.damm@gmail.com> [110105 21:10]:
> On Wed, Jan 5, 2011 at 5:22 AM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > This uncouple PHYS_OFFSET from the platform definitions, thereby
> > facilitating run-time computation of the physical memory offset.
> >
> > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> > ---
> > arch/arm/include/asm/memory.h | 2 ++
> > arch/arm/kernel/tcm.c | 2 +-
> ...
> > arch/arm/mach-shmobile/include/mach/memory.h | 2 +-
>
> Applied on top of sh-2.6 git c422a5992e9ca072e8e472ee8f518649fb07470e
> and successfully booted on a sh7372-based Mackerel board.
>
> Acked-by: Magnus Damm <damm@opensource.se>
Acked-by: Tony Lindgren <tony@atomide.com>
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^ permalink raw reply
* Re: [alsa-devel] [PATCH 6/6] ASoC: Tegra: Harmony: Support both int and ext mics
From: Mark Brown @ 2011-02-07 11:13 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
lrg-kDsPt+C1G03kYMGBc/C6ZA@public.gmane.org
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF0310C8EB68-C7FfzLzN0UxDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
On Fri, Feb 04, 2011 at 09:20:26AM -0800, Stephen Warren wrote:
> However, I wonder how this interacts with mic detection using micbias current.
> There is only one mic bias signal, routed to a subset of the mics using the
> two per-mic enable GPIOs. Should I just hook up the mic bias detection to
> both jacks somehow, or is the only option to just punt on jack detection?
> There are no physical plug detection mechanisms on this board.
That's a fairly unusual hardware design, it really needs explaining in
the code - it wasn't at all obvious that you were controlling a FET
reading the patch (and I'm still not entirely clear how exactly things
are wired up). The simplest way to handle this is probably with a
conditional DAPM route (look at how WM8994 handles SYSCLK for an example
of this), though you'll need to faff around a bit.
Ideally you want the micbias to be enabled all the time for detection of
jack insertion, only flipping the bias over to the internal mic when the
internal mic is being used for recording, and also disable the detection
when the internal microphone is in use. I'm not sure that this is worth
the bother.
> > This would greatly simplify the driver code without really impacting the
> > level of configuration applications need to do (and allowing them to use
> > both simultaneously if they want to).
> I guess you could, although even with L/R routing implemented for the
> single-mic case, I think the only option for dual-mic would be to capture
> each mic on its own channel, which seems like an unlikely use case to me.
> But who knows, maybe it could be useful for e.g. noise-cancelling in SW?
Most likely would seem to be using the mic jack as a line input for some
purpose and combining it with the results of the internal microphone.
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^ permalink raw reply
* [PATCH 2/2] ARM: tegra: add TrimSlice board
From: Mike Rapoport @ 2011-02-07 8:10 UTC (permalink / raw)
To: linux-tegra
Cc: Olof Johansson, Mike Rapoport, linux-arm-kernel, Erik Gilling,
Colin Cross
In-Reply-To: <cover.1297063443.git.mike@compulab.co.il>
Add basic support for CompuLab TrimSlice platform
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
---
arch/arm/mach-tegra/Kconfig | 6 +
arch/arm/mach-tegra/Makefile | 3 +
arch/arm/mach-tegra/board-trimslice-pinmux.c | 145 ++++++++++++++++++++++++++
arch/arm/mach-tegra/board-trimslice.c | 104 ++++++++++++++++++
arch/arm/mach-tegra/board-trimslice.h | 22 ++++
5 files changed, 280 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-tegra/board-trimslice-pinmux.c
create mode 100644 arch/arm/mach-tegra/board-trimslice.c
create mode 100644 arch/arm/mach-tegra/board-trimslice.h
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index acd9552..f0fda77 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -27,6 +27,12 @@ config MACH_HARMONY
help
Support for nVidia Harmony development platform
+config MACH_TRIMSLICE
+ bool "TrimSlice board"
+ select TEGRA_PCI
+ help
+ Support for CompuLab TrimSlice platform
+
choice
prompt "Low-level debug console UART"
default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index cdbc68e..0e1844b 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -19,3 +19,6 @@ obj-$(CONFIG_TEGRA_PCI) += pcie.o
obj-${CONFIG_MACH_HARMONY} += board-harmony.o
obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o
obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o
+
+obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o
+obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
new file mode 100644
index 0000000..6d4fc9f
--- /dev/null
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -0,0 +1,145 @@
+/*
+ * arch/arm/mach-tegra/board-trimslice-pinmux.c
+ *
+ * Copyright (C) 2011 CompuLab, Ltd.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <mach/pinmux.h>
+
+#include "board-trimslice.h"
+
+static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
+ {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+};
+
+void __init trimslice_pinmux_init(void)
+{
+ tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux));
+}
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
new file mode 100644
index 0000000..ef233b2
--- /dev/null
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -0,0 +1,104 @@
+/*
+ * arch/arm/mach-tegra/board-trimslice.c
+ *
+ * Copyright (C) 2011 CompuLab, Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Based on board-harmony.c
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/io.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/setup.h>
+
+#include <mach/iomap.h>
+
+#include "board.h"
+#include "clock.h"
+
+#include "board-trimslice.h"
+
+static struct plat_serial8250_port debug_uart_platform_data[] = {
+ {
+ .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
+ .mapbase = TEGRA_UARTA_BASE,
+ .irq = INT_UARTA,
+ .flags = UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = 216000000,
+ }, {
+ .flags = 0
+ }
+};
+
+static struct platform_device debug_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = debug_uart_platform_data,
+ },
+};
+
+static struct platform_device *trimslice_devices[] __initdata = {
+ &debug_uart,
+};
+
+static void __init tegra_trimslice_fixup(struct machine_desc *desc,
+ struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+ mi->nr_banks = 2;
+ mi->bank[0].start = PHYS_OFFSET;
+ mi->bank[0].size = 448 * SZ_1M;
+ mi->bank[1].start = SZ_512M;
+ mi->bank[1].size = SZ_512M;
+}
+
+static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
+ /* name parent rate enabled */
+ { "uarta", "pll_p", 216000000, true },
+ { NULL, NULL, 0, 0},
+};
+
+static int __init tegra_trimslice_pci_init(void)
+{
+ return tegra_pcie_init(true, true);
+}
+subsys_initcall(tegra_trimslice_pci_init);
+
+static void __init tegra_trimslice_init(void)
+{
+ tegra_common_init();
+
+ tegra_clk_init_from_table(trimslice_clk_init_table);
+
+ trimslice_pinmux_init();
+
+ platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
+}
+
+MACHINE_START(TRIMSLICE, "trimslice")
+ .boot_params = 0x00000100,
+ .fixup = tegra_trimslice_fixup,
+ .init_irq = tegra_init_irq,
+ .init_machine = tegra_trimslice_init,
+ .map_io = tegra_map_common_io,
+ .timer = &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h
new file mode 100644
index 0000000..16ec0f0
--- /dev/null
+++ b/arch/arm/mach-tegra/board-trimslice.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-tegra/board-trimslice.h
+ *
+ * Copyright (C) 2011 CompuLab, Ltd.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H
+#define _MACH_TEGRA_BOARD_TRIMSLICE_H
+
+void trimslice_pinmux_init(void);
+
+#endif
--
1.7.3.1
^ permalink raw reply related
* [PATCH 1/2] ARM: update trimslice entry in the machine registry
From: Mike Rapoport @ 2011-02-07 8:10 UTC (permalink / raw)
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA
Cc: Colin Cross, Erik Gilling, Olof Johansson,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mike Rapoport
In-Reply-To: <cover.1297063443.git.mike-UTxiZqZC01RS1MOuV/RT9w@public.gmane.org>
Signed-off-by: Mike Rapoport <mike-UTxiZqZC01RS1MOuV/RT9w@public.gmane.org>
---
arch/arm/tools/mach-types | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2fea897..bda8b81 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -3190,7 +3190,7 @@ synergy MACH_SYNERGY SYNERGY 3205
ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
punica MACH_PUNICA PUNICA 3208
-sbc_nt250 MACH_SBC_NT250 SBC_NT250 3209
+trimslice MACH_TRIMSLICE TRIMSLICE 3209
mx27_wmultra MACH_MX27_WMULTRA MX27_WMULTRA 3210
mackerel MACH_MACKEREL MACKEREL 3211
fa9x27 MACH_FA9X27 FA9X27 3213
--
1.7.3.1
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^ permalink raw reply related
* [PATCH 0/2] ARM: tegra: add TrimSlice support
From: Mike Rapoport @ 2011-02-07 8:10 UTC (permalink / raw)
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA
Cc: Colin Cross, Erik Gilling, Olof Johansson,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mike Rapoport
These patches add basic support for TrimSlice platform.
The mach-types update is required until the updated machine registry
is merged, otherwise the kernel would not build.
The patches are also available at git repository
git://git.kernel.org/pub/scm/linux/kernel/git/rppt/linux-tegra.git trimslice/upstream
The following changes since commit 8dbdea8444d303a772bceb1ba963f0e3273bfc5e:
Merge branch 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6 (2011-02-06 12:05:58 -0800)
Mike Rapoport (2):
ARM: update trimslice entry in the machine registry
ARM: tegra: add TrimSlice board
arch/arm/mach-tegra/Kconfig | 6 +
arch/arm/mach-tegra/Makefile | 3 +
arch/arm/mach-tegra/board-trimslice-pinmux.c | 145 ++++++++++++++++++++++++++
arch/arm/mach-tegra/board-trimslice.c | 104 ++++++++++++++++++
arch/arm/mach-tegra/board-trimslice.h | 22 ++++
arch/arm/tools/mach-types | 2 +-
6 files changed, 281 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-tegra/board-trimslice-pinmux.c
create mode 100644 arch/arm/mach-tegra/board-trimslice.c
create mode 100644 arch/arm/mach-tegra/board-trimslice.h
--
1.7.3.1
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^ permalink raw reply
* Re: [rtc-linux] [PATCH v5] mfd: tps6586x: add RTC driver for TI TPS6586x
From: Varun Wadekar @ 2011-02-07 7:30 UTC (permalink / raw)
To: Mark Brown
Cc: rtc-linux-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Andy Ritger,
Stephen Warren, Bharat Nihalani
In-Reply-To: <20110203132810.GB28460-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org>
> I don't maintain the RTC stuff, Alessandro does (though the patches
> actually get queued via Andrew Morton). I was just randomly reviewing
> the code.
Alessandro, did you get a chance to review this patch?
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^ permalink raw reply
* RE: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support forre-enabling l2x0
From: Santosh Shilimkar @ 2011-02-07 6:13 UTC (permalink / raw)
To: Colin Cross
Cc: Russell King - ARM Linux, Will Deacon, Catalin Marinas,
Linus Walleij, konkers-z5hGa2qSFaRBDgjK7y7TUQ, Tony Lindgren,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, olof-nZhT3qVonbNeoWH0uzbU5w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <AANLkTik_r4k_5o+F47vRbGPcWLwfgHgWqhym49XfhBZ9-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
> -----Original Message-----
> From: ccross-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org [mailto:ccross-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org] On Behalf Of
> Colin Cross
> Sent: Saturday, February 05, 2011 10:06 PM
> To: Santosh Shilimkar
> Cc: Russell King - ARM Linux; Will Deacon; Catalin Marinas; Linus
> Walleij; konkers-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org; Tony Lindgren; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org;
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Subject: Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support
> forre-enabling l2x0
>
> On Sat, Feb 5, 2011 at 4:41 AM, Santosh Shilimkar
> <santosh.shilimkar-l0cyMroinI0@public.gmane.org> wrote:
[....]
> >> On Sat, Feb 05, 2011 at 01:21:24PM +0530, Santosh Shilimkar
> wrote:
> >> > GIC save/restore on OMAP follows different strategy. There is a
> >> > Predefined layout to save content and restore is done
> atomically
> >> > by boot ROM code.
> >> > L2 cache also same case. Only AUXCTRL needs to be programmed on
> >> > wakeup from low power mode and that too with secure call. Rest
> >> > of the registers are managed by boot ROM code.
> >> >
> >> > TWD is already managed through framework. Othe CPU low power
> >> > sequence is very small and OMAP has restrictions on the last
> >> > core to go down and first to wakeup.
> >> >
> >> > So at least I don't see any use of common notifiers for GIC
> >> > and L2 will help OMAP lower power code.
> >>
> >> What this means is that we're going to end up littering things
> like
> >> GIC
> >> and other stuff with lots of individual SoC specific code to save
> >> state
> >> into individual SoC specific structures. This is not sane, and
> >> we're
> >> not going to corrupt generic code with SoC specific code.
> >
> > Fully agree and hence flagged it early.
> >
[....]
>
> Would putting dummy values in the areas the boot ROM uses and then
> letting the common GIC code restore over them cause any problems?
Ya there are few issue. GIC and GIC OMAP extension are managed
together by BOOT ROM code. It's far optimal save and restore. Only
needed registers from OMAP point of view are saved/restored.
And for such reasons I would not like to use dummy stuff.
Regards
Santosh
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^ permalink raw reply
* Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support forre-enabling l2x0
From: Colin Cross @ 2011-02-05 16:36 UTC (permalink / raw)
To: Santosh Shilimkar
Cc: Russell King - ARM Linux, Will Deacon, Catalin Marinas,
Linus Walleij, konkers, Tony Lindgren, linux-kernel, linux-tegra,
olof, linux-arm-kernel
In-Reply-To: <cb528285e8aa8cdda01d7ced0121b2cf@mail.gmail.com>
On Sat, Feb 5, 2011 at 4:41 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
>> Sent: Saturday, February 05, 2011 3:18 PM
>> To: Santosh Shilimkar
>> Cc: Colin Cross; Will Deacon; Catalin Marinas; Linus Walleij;
>> konkers@android.com; Tony Lindgren; linux-kernel@vger.kernel.org;
>> linux-tegra@vger.kernel.org; olof@lixom.net; linux-arm-
>> kernel@lists.infradead.org
>> Subject: Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support
>> forre-enabling l2x0
>>
>> On Sat, Feb 05, 2011 at 01:21:24PM +0530, Santosh Shilimkar wrote:
>> > GIC save/restore on OMAP follows different strategy. There is a
>> > Predefined layout to save content and restore is done atomically
>> > by boot ROM code.
>> > L2 cache also same case. Only AUXCTRL needs to be programmed on
>> > wakeup from low power mode and that too with secure call. Rest
>> > of the registers are managed by boot ROM code.
>> >
>> > TWD is already managed through framework. Othe CPU low power
>> > sequence is very small and OMAP has restrictions on the last
>> > core to go down and first to wakeup.
>> >
>> > So at least I don't see any use of common notifiers for GIC
>> > and L2 will help OMAP lower power code.
>>
>> What this means is that we're going to end up littering things like
>> GIC
>> and other stuff with lots of individual SoC specific code to save
>> state
>> into individual SoC specific structures. This is not sane, and
>> we're
>> not going to corrupt generic code with SoC specific code.
>
> Fully agree and hence flagged it early.
>
> Regards,
> Santosh
>
Would putting dummy values in the areas the boot ROM uses and then
letting the common GIC code restore over them cause any problems?
^ permalink raw reply
* RE: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support forre-enabling l2x0
From: Santosh Shilimkar @ 2011-02-05 10:41 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Colin Cross, Will Deacon, Catalin Marinas, Linus Walleij, konkers,
Tony Lindgren, linux-kernel, linux-tegra, olof, linux-arm-kernel
In-Reply-To: <20110205094730.GA23965@n2100.arm.linux.org.uk>
> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> Sent: Saturday, February 05, 2011 3:18 PM
> To: Santosh Shilimkar
> Cc: Colin Cross; Will Deacon; Catalin Marinas; Linus Walleij;
> konkers@android.com; Tony Lindgren; linux-kernel@vger.kernel.org;
> linux-tegra@vger.kernel.org; olof@lixom.net; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support
> forre-enabling l2x0
>
> On Sat, Feb 05, 2011 at 01:21:24PM +0530, Santosh Shilimkar wrote:
> > GIC save/restore on OMAP follows different strategy. There is a
> > Predefined layout to save content and restore is done atomically
> > by boot ROM code.
> > L2 cache also same case. Only AUXCTRL needs to be programmed on
> > wakeup from low power mode and that too with secure call. Rest
> > of the registers are managed by boot ROM code.
> >
> > TWD is already managed through framework. Othe CPU low power
> > sequence is very small and OMAP has restrictions on the last
> > core to go down and first to wakeup.
> >
> > So at least I don't see any use of common notifiers for GIC
> > and L2 will help OMAP lower power code.
>
> What this means is that we're going to end up littering things like
> GIC
> and other stuff with lots of individual SoC specific code to save
> state
> into individual SoC specific structures. This is not sane, and
> we're
> not going to corrupt generic code with SoC specific code.
Fully agree and hence flagged it early.
Regards,
Santosh
^ permalink raw reply
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