* [PATCH v4 16/37] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra, linux-pm, linux-kernel,
dri-devel, devicetree
In-Reply-To: <20200609131404.17523-1-digetx@gmail.com>
The current conversion ratio results in a higher frequency than needed,
that is not very actual now since the Display Controller driver got
support for memory bandwidth management and hence memory frequency can
go lower now without bad consequences. Since memory freq now goes to a
lower rates, the responsiveness of interactive applications become worse
due to a quite high polling interval value that is currently set to 500ms.
Changing polling interval to 30ms results in a good responsiveness of the
system.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/devfreq/tegra20-devfreq.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c
index 249d0dc44f6c..7cdea4ba38f7 100644
--- a/drivers/devfreq/tegra20-devfreq.c
+++ b/drivers/devfreq/tegra20-devfreq.c
@@ -79,16 +79,12 @@ static int tegra_devfreq_get_dev_status(struct device *dev,
/*
* EMC_COUNT returns number of memory events, that number is lower
- * than the number of clocks. Conversion ratio of 1/8 results in a
- * bit higher bandwidth than actually needed, it is good enough for
- * the time being because drivers don't support requesting minimum
- * needed memory bandwidth yet.
- *
- * TODO: adjust the ratio value once relevant drivers will support
- * memory bandwidth management.
+ * than the number of total EMC clocks over the sampling period.
+ * The clocks number is converted to maximum possible number of
+ * memory events using the ratio of 1/4.
*/
stat->busy_time = readl_relaxed(tegra->regs + MC_STAT_EMC_COUNT);
- stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 8;
+ stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 4;
stat->current_frequency = clk_get_rate(tegra->emc_clock);
writel_relaxed(EMC_GATHER_CLEAR, tegra->regs + MC_STAT_CONTROL);
@@ -98,7 +94,7 @@ static int tegra_devfreq_get_dev_status(struct device *dev,
}
static struct devfreq_dev_profile tegra_devfreq_profile = {
- .polling_ms = 500,
+ .polling_ms = 30,
.target = tegra_devfreq_target,
.get_dev_status = tegra_devfreq_get_dev_status,
};
--
2.26.0
^ permalink raw reply related
* [PATCH v4 15/37] PM / devfreq: tegra30: Add error messages to tegra_devfreq_target()
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra, linux-pm, linux-kernel,
dri-devel, devicetree
In-Reply-To: <20200609131404.17523-1-digetx@gmail.com>
It's useful to now when something goes wrong instead of failing silently,
so let's add error messages to tegra_devfreq_target() to prevent situation
where it fails silently.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/devfreq/tegra30-devfreq.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c
index 13f93c6038ab..a03fb16c5c4c 100644
--- a/drivers/devfreq/tegra30-devfreq.c
+++ b/drivers/devfreq/tegra30-devfreq.c
@@ -641,12 +641,16 @@ static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
dev_pm_opp_put(opp);
err = clk_set_min_rate(tegra->emc_clock, rate * KHZ);
- if (err)
+ if (err) {
+ dev_err(dev, "Failed to set min rate: %d\n", err);
return err;
+ }
err = clk_set_rate(tegra->emc_clock, 0);
- if (err)
+ if (err) {
+ dev_err(dev, "Failed to set rate: %d\n", err);
goto restore_min_rate;
+ }
return 0;
--
2.26.0
^ permalink raw reply related
* [PATCH v4 14/37] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target()
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra, linux-pm, linux-kernel,
dri-devel, devicetree
In-Reply-To: <20200609131404.17523-1-digetx@gmail.com>
It's useful to now when something goes wrong instead of failing silently,
so let's add error messages to tegra_devfreq_target() to prevent situation
where it fails silently.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/devfreq/tegra20-devfreq.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c
index bf504ca4dea2..249d0dc44f6c 100644
--- a/drivers/devfreq/tegra20-devfreq.c
+++ b/drivers/devfreq/tegra20-devfreq.c
@@ -44,19 +44,25 @@ static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
int err;
opp = devfreq_recommended_opp(dev, freq, flags);
- if (IS_ERR(opp))
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to find opp for %lu Hz\n", *freq);
return PTR_ERR(opp);
+ }
rate = dev_pm_opp_get_freq(opp);
dev_pm_opp_put(opp);
err = clk_set_min_rate(tegra->emc_clock, rate);
- if (err)
+ if (err) {
+ dev_err(dev, "failed to set min rate: %d\n", err);
return err;
+ }
err = clk_set_rate(tegra->emc_clock, 0);
- if (err)
+ if (err) {
+ dev_err(dev, "failed to set rate: %d\n", err);
goto restore_min_rate;
+ }
return 0;
--
2.26.0
^ permalink raw reply related
* [PATCH v4 13/37] PM / devfreq: tegra30: Use MC timings for building OPP table
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The clk_round_rate() won't be usable for building OPP table once
interconnect support will be added to the EMC driver because that CLK API
function limits the rounded rate based on the clk rate that is imposed by
active clk-users, and thus, the rounding won't work as expected if
interconnect will set the minimum EMC clock rate before devfreq driver is
loaded. The struct tegra_mc contains memory timings which could be used by
the devfreq driver for building up OPP table instead of rounding clock
rate, this patch implements this idea.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/devfreq/tegra30-devfreq.c | 98 ++++++++++++++++++++++---------
1 file changed, 70 insertions(+), 28 deletions(-)
diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c
index 423dd35c95b3..13f93c6038ab 100644
--- a/drivers/devfreq/tegra30-devfreq.c
+++ b/drivers/devfreq/tegra30-devfreq.c
@@ -19,6 +19,8 @@
#include <linux/reset.h>
#include <linux/workqueue.h>
+#include <soc/tegra/mc.h>
+
#include "governor.h"
#define ACTMON_GLB_STATUS 0x0
@@ -153,6 +155,18 @@ struct tegra_devfreq_device {
unsigned long target_freq;
};
+struct tegra_devfreq_soc_data {
+ const char *mc_compatible;
+};
+
+static const struct tegra_devfreq_soc_data tegra30_soc = {
+ .mc_compatible = "nvidia,tegra30-mc",
+};
+
+static const struct tegra_devfreq_soc_data tegra124_soc = {
+ .mc_compatible = "nvidia,tegra124-mc",
+};
+
struct tegra_devfreq {
struct devfreq *devfreq;
@@ -771,15 +785,44 @@ static struct devfreq_governor tegra_devfreq_governor = {
.interrupt_driven = true,
};
+static struct tegra_mc *tegra_get_memory_controller(const char *compatible)
+{
+ struct platform_device *pdev;
+ struct device_node *np;
+ struct tegra_mc *mc;
+
+ np = of_find_compatible_node(NULL, NULL, compatible);
+ if (!np)
+ return ERR_PTR(-ENOENT);
+
+ pdev = of_find_device_by_node(np);
+ of_node_put(np);
+ if (!pdev)
+ return ERR_PTR(-ENODEV);
+
+ mc = platform_get_drvdata(pdev);
+ if (!mc)
+ return ERR_PTR(-EPROBE_DEFER);
+
+ return mc;
+}
+
static int tegra_devfreq_probe(struct platform_device *pdev)
{
+ const struct tegra_devfreq_soc_data *soc_data;
struct tegra_devfreq_device *dev;
struct tegra_devfreq *tegra;
struct devfreq *devfreq;
+ struct tegra_mc *mc;
unsigned int i;
- long rate;
int err;
+ soc_data = of_device_get_match_data(&pdev->dev);
+
+ mc = tegra_get_memory_controller(soc_data->mc_compatible);
+ if (IS_ERR(mc))
+ return PTR_ERR(mc);
+
tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
if (!tegra)
return -ENOMEM;
@@ -825,6 +868,30 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
return err;
}
+ if (!mc->num_timings) {
+ tegra->max_freq = clk_get_rate(tegra->clock) / KHZ;
+
+ err = dev_pm_opp_add(&pdev->dev, tegra->max_freq, 0);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to add OPP: %d\n", err);
+ return err;
+ }
+ }
+
+ for (i = 0; i < mc->num_timings; i++) {
+ /*
+ * Memory Controller timings are sorted in ascending clock
+ * rate order, so the last timing will be the max freq.
+ */
+ tegra->max_freq = mc->timings[i].rate / KHZ;
+
+ err = dev_pm_opp_add(&pdev->dev, tegra->max_freq, 0);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to add OPP: %d\n", err);
+ goto remove_opps;
+ }
+ }
+
reset_control_assert(tegra->reset);
err = clk_prepare_enable(tegra->clock);
@@ -836,37 +903,12 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
reset_control_deassert(tegra->reset);
- rate = clk_round_rate(tegra->emc_clock, ULONG_MAX);
- if (rate < 0) {
- dev_err(&pdev->dev, "Failed to round clock rate: %ld\n", rate);
- return rate;
- }
-
- tegra->max_freq = rate / KHZ;
-
for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
dev = tegra->devices + i;
dev->config = actmon_device_configs + i;
dev->regs = tegra->regs + dev->config->offset;
}
- for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) {
- rate = clk_round_rate(tegra->emc_clock, rate);
-
- if (rate < 0) {
- dev_err(&pdev->dev,
- "Failed to round clock rate: %ld\n", rate);
- err = rate;
- goto remove_opps;
- }
-
- err = dev_pm_opp_add(&pdev->dev, rate / KHZ, 0);
- if (err) {
- dev_err(&pdev->dev, "Failed to add OPP: %d\n", err);
- goto remove_opps;
- }
- }
-
platform_set_drvdata(pdev, tegra);
tegra->clk_rate_change_nb.notifier_call = tegra_actmon_clk_notify_cb;
@@ -921,8 +963,8 @@ static int tegra_devfreq_remove(struct platform_device *pdev)
}
static const struct of_device_id tegra_devfreq_of_match[] = {
- { .compatible = "nvidia,tegra30-actmon" },
- { .compatible = "nvidia,tegra124-actmon" },
+ { .compatible = "nvidia,tegra30-actmon", .data = &tegra30_soc, },
+ { .compatible = "nvidia,tegra124-actmon", .data = &tegra124_soc, },
{ },
};
--
2.26.0
^ permalink raw reply related
* [PATCH v4 12/37] PM / devfreq: tegra20: Use MC timings for building OPP table
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The clk_round_rate() won't be usable for building OPP table once
interconnect support will be added to the EMC driver because that CLK API
function limits the rounded rate based on the clk rate that is imposed by
active clk-users, and thus, the rounding won't work as expected if
interconnect will set the minimum EMC clock rate before devfreq driver is
loaded. The struct tegra_mc contains memory timings which could be used by
the devfreq driver for building up OPP table instead of rounding clock
rate, this patch implements this idea.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/devfreq/tegra20-devfreq.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c
index 6469dc69c5e0..bf504ca4dea2 100644
--- a/drivers/devfreq/tegra20-devfreq.c
+++ b/drivers/devfreq/tegra20-devfreq.c
@@ -123,8 +123,7 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
{
struct tegra_devfreq *tegra;
struct tegra_mc *mc;
- unsigned long max_rate;
- unsigned long rate;
+ unsigned int i;
int err;
mc = tegra_get_memory_controller();
@@ -151,12 +150,17 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
tegra->regs = mc->regs;
- max_rate = clk_round_rate(tegra->emc_clock, ULONG_MAX);
-
- for (rate = 0; rate <= max_rate; rate++) {
- rate = clk_round_rate(tegra->emc_clock, rate);
+ if (!mc->num_timings) {
+ err = dev_pm_opp_add(&pdev->dev,
+ clk_get_rate(tegra->emc_clock), 0);
+ if (err) {
+ dev_err(&pdev->dev, "failed to add OPP: %d\n", err);
+ return err;
+ }
+ }
- err = dev_pm_opp_add(&pdev->dev, rate, 0);
+ for (i = 0; i < mc->num_timings; i++) {
+ err = dev_pm_opp_add(&pdev->dev, mc->timings[i].rate, 0);
if (err) {
dev_err(&pdev->dev, "failed to add opp: %d\n", err);
goto remove_opps;
--
2.26.0
^ permalink raw reply related
* [PATCH v4 11/37] PM / devfreq: tegra30: Silence deferred probe error
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tegra EMC driver was turned into a regular kernel driver, it also could
be compiled as a loadable kernel module now. Hence EMC clock isn't
guaranteed to be available and clk_get("emc") may return -EPROBE_DEFER and
there is no good reason to spam KMSG with a error about missing EMC clock
in this case, so let's silence the deferred probe error.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/devfreq/tegra30-devfreq.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c
index e94a27804c20..423dd35c95b3 100644
--- a/drivers/devfreq/tegra30-devfreq.c
+++ b/drivers/devfreq/tegra30-devfreq.c
@@ -801,9 +801,12 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
}
tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
- if (IS_ERR(tegra->emc_clock)) {
- dev_err(&pdev->dev, "Failed to get emc clock\n");
- return PTR_ERR(tegra->emc_clock);
+ err = PTR_ERR_OR_ZERO(tegra->emc_clock);
+ if (err) {
+ if (err != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get emc clock: %d\n",
+ err);
+ return err;
}
err = platform_get_irq(pdev, 0);
--
2.26.0
^ permalink raw reply related
* [PATCH v4 10/37] PM / devfreq: tegra20: Silence deferred probe error
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tegra EMC driver was turned into a regular kernel driver, it also could
be compiled as a loadable kernel module now. Hence EMC clock isn't
guaranteed to be available and clk_get("emc") may return -EPROBE_DEFER and
there is no good reason to spam KMSG with a error about missing EMC clock
in this case, so let's silence the deferred probe error.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/devfreq/tegra20-devfreq.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c
index ff82bac9ee4e..6469dc69c5e0 100644
--- a/drivers/devfreq/tegra20-devfreq.c
+++ b/drivers/devfreq/tegra20-devfreq.c
@@ -141,9 +141,11 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
/* EMC is a system-critical clock that is always enabled */
tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
- if (IS_ERR(tegra->emc_clock)) {
- err = PTR_ERR(tegra->emc_clock);
- dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
+ err = PTR_ERR_OR_ZERO(tegra->emc_clock);
+ if (err) {
+ if (err != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "failed to get emc clock: %d\n",
+ err);
return err;
}
--
2.26.0
^ permalink raw reply related
* [PATCH v4 09/37] memory: tegra20-emc: Initialize MC timings
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra, linux-pm, linux-kernel,
dri-devel, devicetree
In-Reply-To: <20200609131404.17523-1-digetx@gmail.com>
We're going to add interconnect support to the EMC driver. Once this
support will be added, the Tegra20 devfreq driver will no longer be
able to use clk_round_rate(emc) for building up OPP table. It's quite
handy that struct tegra_mc contains memory timings which could be used
by the devfreq drivers instead of the clk rate-rounding. The tegra_mc
timings are populated by the MC driver only for Tegra30+ SoCs, hence
the Tegra20 EMC could populate timings by itself.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/tegra20-emc.c | 47 ++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index c1cad4ce6251..5bf75b316a2f 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -10,7 +10,7 @@ config TEGRA_MC
config TEGRA20_EMC
tristate "NVIDIA Tegra20 External Memory Controller driver"
default y
- depends on ARCH_TEGRA_2x_SOC
+ depends on TEGRA_MC && ARCH_TEGRA_2x_SOC
help
This driver is for the External Memory Controller (EMC) found on
Tegra20 chips. The EMC controls the external DRAM on the board.
diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 0baa6590adea..2e310c51c599 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -15,12 +15,15 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/sort.h>
#include <linux/types.h>
#include <soc/tegra/fuse.h>
+#include "mc.h"
+
#define EMC_INTSTATUS 0x000
#define EMC_INTMASK 0x004
#define EMC_DBG 0x008
@@ -650,6 +653,38 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc)
emc, &tegra_emc_debug_max_rate_fops);
}
+static int tegra_emc_init_mc_timings(struct tegra_emc *emc)
+{
+ struct tegra_mc_timing *timing;
+ struct platform_device *pdev;
+ struct device_node *np;
+ struct tegra_mc *mc;
+ unsigned int i;
+
+ np = of_find_compatible_node(NULL, NULL, "nvidia,tegra20-mc-gart");
+ if (!np)
+ return -ENOENT;
+
+ pdev = of_find_device_by_node(np);
+ of_node_put(np);
+ if (!pdev)
+ return -ENOENT;
+
+ mc = platform_get_drvdata(pdev);
+ if (!mc)
+ return -EPROBE_DEFER;
+
+ mc->timings = devm_kcalloc(mc->dev, emc->num_timings, sizeof(*timing),
+ GFP_KERNEL);
+ if (!mc->timings)
+ return -ENOMEM;
+
+ for (i = 0; i < emc->num_timings; i++)
+ mc->timings[mc->num_timings++].rate = emc->timings[i].rate;
+
+ return 0;
+}
+
static int tegra_emc_probe(struct platform_device *pdev)
{
struct device_node *np;
@@ -705,6 +740,18 @@ static int tegra_emc_probe(struct platform_device *pdev)
return err;
}
+ /*
+ * Only Tegra30+ SoCs are having Memory Controller timings initialized
+ * by the MC driver. For Tegra20 we need to populate the MC timings
+ * from here. The MC timings will be used by the Tegra20 devfreq driver.
+ */
+ err = tegra_emc_init_mc_timings(emc);
+ if (err) {
+ dev_err(&pdev->dev, "failed to initialize mc timings: %d\n",
+ err);
+ return err;
+ }
+
tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
emc->clk = devm_clk_get(&pdev->dev, "emc");
--
2.26.0
^ permalink raw reply related
* [PATCH v4 08/37] soc/tegra: fuse: Export tegra_read_ram_code()
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra, linux-pm, linux-kernel,
dri-devel, devicetree
In-Reply-To: <20200609131404.17523-1-digetx@gmail.com>
The tegra_read_ram_code() is used by EMC drivers and we're going to make
these driver modular, hence this function needs to be exported.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
index 3cdd69d1bd4d..b3c930b805c5 100644
--- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -3,6 +3,7 @@
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*/
+#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -65,6 +66,7 @@ u32 tegra_read_ram_code(void)
return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
}
+EXPORT_SYMBOL_GPL(tegra_read_ram_code);
static const struct of_device_id apbmisc_match[] __initconst = {
{ .compatible = "nvidia,tegra20-apbmisc", },
--
2.26.0
^ permalink raw reply related
* [PATCH v4 07/37] memory: tegra124-emc: Use devm_platform_ioremap_resource
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Utilize that relatively new helper which makes code a bit cleaner.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/memory/tegra/tegra124-emc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c
index 98d98d09b00c..6d2897d4dca9 100644
--- a/drivers/memory/tegra/tegra124-emc.c
+++ b/drivers/memory/tegra/tegra124-emc.c
@@ -1193,7 +1193,6 @@ static int tegra_emc_probe(struct platform_device *pdev)
struct platform_device *mc;
struct device_node *np;
struct tegra_emc *emc;
- struct resource *res;
u32 ram_code;
int err;
@@ -1203,8 +1202,7 @@ static int tegra_emc_probe(struct platform_device *pdev)
emc->dev = &pdev->dev;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- emc->regs = devm_ioremap_resource(&pdev->dev, res);
+ emc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(emc->regs))
return PTR_ERR(emc->regs);
--
2.26.0
^ permalink raw reply related
* [PATCH v4 06/37] memory: tegra124-emc: Make driver modular
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra, linux-pm, linux-kernel,
dri-devel, devicetree
In-Reply-To: <20200609131404.17523-1-digetx@gmail.com>
This patch adds modularization support to the Tegra124 EMC driver. Driver
now can be compiled as a loadable kernel module.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-tegra124-emc.c | 63 +++++++++++++++++-----------
drivers/clk/tegra/clk-tegra124.c | 3 +-
drivers/clk/tegra/clk.h | 12 ------
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/tegra124-emc.c | 32 +++++++++-----
include/linux/clk/tegra.h | 11 +++++
include/soc/tegra/emc.h | 16 -------
7 files changed, 73 insertions(+), 66 deletions(-)
delete mode 100644 include/soc/tegra/emc.h
diff --git a/drivers/clk/tegra/clk-tegra124-emc.c b/drivers/clk/tegra/clk-tegra124-emc.c
index 745f9faa98d8..4d8b8f1ba7cd 100644
--- a/drivers/clk/tegra/clk-tegra124-emc.c
+++ b/drivers/clk/tegra/clk-tegra124-emc.c
@@ -11,7 +11,9 @@
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
+#include <linux/clk/tegra.h>
#include <linux/delay.h>
+#include <linux/export.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
@@ -21,10 +23,10 @@
#include <linux/string.h>
#include <soc/tegra/fuse.h>
-#include <soc/tegra/emc.h>
#include "clk.h"
+#define CLK_BASE 0x60006000
#define CLK_SOURCE_EMC 0x19c
#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
@@ -79,7 +81,9 @@ struct tegra_clk_emc {
int num_timings;
struct emc_timing *timings;
- spinlock_t *lock;
+
+ tegra124_emc_prepare_timing_change_cb *prepare_timing_change;
+ tegra124_emc_complete_timing_change_cb *complete_timing_change;
};
/* Common clock framework callback implementations */
@@ -98,7 +102,7 @@ static unsigned long emc_recalc_rate(struct clk_hw *hw,
*/
parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
- val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
+ val = readl(tegra->clk_regs);
div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
return parent_rate / (div + 2) * 2;
@@ -163,7 +167,7 @@ static u8 emc_get_parent(struct clk_hw *hw)
tegra = container_of(hw, struct tegra_clk_emc, hw);
- val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
+ val = readl(tegra->clk_regs);
return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
& CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
@@ -204,7 +208,6 @@ static int emc_set_timing(struct tegra_clk_emc *tegra,
int err;
u8 div;
u32 car_value;
- unsigned long flags = 0;
struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
if (!emc)
@@ -241,13 +244,11 @@ static int emc_set_timing(struct tegra_clk_emc *tegra,
div = timing->parent_rate / (timing->rate / 2) - 2;
- err = tegra_emc_prepare_timing_change(emc, timing->rate);
+ err = tegra->prepare_timing_change(emc, timing->rate);
if (err)
return err;
- spin_lock_irqsave(tegra->lock, flags);
-
- car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
+ car_value = readl(tegra->clk_regs);
car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
@@ -255,11 +256,9 @@ static int emc_set_timing(struct tegra_clk_emc *tegra,
car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
- writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
-
- spin_unlock_irqrestore(tegra->lock, flags);
+ writel(car_value, tegra->clk_regs);
- tegra_emc_complete_timing_change(emc, timing->rate);
+ tegra->complete_timing_change(emc, timing->rate);
clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
clk_disable_unprepare(tegra->prev_parent);
@@ -473,12 +472,15 @@ static const struct clk_ops tegra_clk_emc_ops = {
.get_parent = emc_get_parent,
};
-struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
- spinlock_t *lock)
+struct clk *
+tegra124_clk_register_emc(struct device_node *emc_np,
+ tegra124_emc_prepare_timing_change_cb *prep_cb,
+ tegra124_emc_complete_timing_change_cb *complete_cb)
{
struct tegra_clk_emc *tegra;
struct clk_init_data init;
struct device_node *node;
+ struct resource res;
u32 node_ram_code;
struct clk *clk;
int err;
@@ -487,12 +489,21 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
if (!tegra)
return ERR_PTR(-ENOMEM);
- tegra->clk_regs = base;
- tegra->lock = lock;
+ res.start = CLK_BASE + CLK_SOURCE_EMC;
+ res.end = res.start + 3;
+ res.flags = IORESOURCE_MEM;
- tegra->num_timings = 0;
+ tegra->clk_regs = ioremap(res.start, resource_size(&res));
+ if (!tegra->clk_regs) {
+ pr_err("failed to map CLK_SOURCE_EMC\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ tegra->emc_node = emc_np;
+ tegra->prepare_timing_change = prep_cb;
+ tegra->complete_timing_change = complete_cb;
- for_each_child_of_node(np, node) {
+ for_each_child_of_node(emc_np, node) {
err = of_property_read_u32(node, "nvidia,ram-code",
&node_ram_code);
if (err)
@@ -512,11 +523,6 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
if (tegra->num_timings == 0)
pr_warn("%s: no memory timings registered\n", __func__);
- tegra->emc_node = of_parse_phandle(np,
- "nvidia,external-memory-controller", 0);
- if (!tegra->emc_node)
- pr_warn("%s: couldn't find node for EMC driver\n", __func__);
-
init.name = "emc";
init.ops = &tegra_clk_emc_ops;
init.flags = CLK_IS_CRITICAL;
@@ -536,5 +542,12 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
/* Allow debugging tools to see the EMC clock */
clk_register_clkdev(clk, "emc", "tegra-clk-debug");
+ /*
+ * Don't allow the kernel module to be unloaded, unloading is not
+ * supported by the EMC driver.
+ */
+ try_module_get(THIS_MODULE);
+
return clk;
-};
+}
+EXPORT_SYMBOL_GPL(tegra124_clk_register_emc);
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 0c956e14b9ca..228d87367ac6 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -928,6 +928,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
[tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
+ [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = false },
};
static struct tegra_devclk devclks[] __initdata = {
@@ -1516,8 +1517,6 @@ static void __init tegra124_132_clock_init_post(struct device_node *np)
tegra124_reset_deassert);
tegra_add_of_provider(np, of_clk_src_onecell_get);
- clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, NULL);
-
tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
tegra_cpu_car_ops = &tegra124_cpu_car_ops;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 5ed8b95d331c..11a8bbe650c5 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -881,18 +881,6 @@ void tegra_super_clk_gen5_init(void __iomem *clk_base,
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *pll_params);
-#ifdef CONFIG_TEGRA124_EMC
-struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
- spinlock_t *lock);
-#else
-static inline struct clk *tegra_clk_register_emc(void __iomem *base,
- struct device_node *np,
- spinlock_t *lock)
-{
- return NULL;
-}
-#endif
-
void tegra114_clock_tune_cpu_trimmers_high(void);
void tegra114_clock_tune_cpu_trimmers_low(void);
void tegra114_clock_tune_cpu_trimmers_init(void);
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index bd453de9d446..c1cad4ce6251 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -28,7 +28,7 @@ config TEGRA30_EMC
external memory.
config TEGRA124_EMC
- bool "NVIDIA Tegra124 External Memory Controller driver"
+ tristate "NVIDIA Tegra124 External Memory Controller driver"
default y
depends on TEGRA_MC && ARCH_TEGRA_124_SOC
help
diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c
index d19fb7ae230d..98d98d09b00c 100644
--- a/drivers/memory/tegra/tegra124-emc.c
+++ b/drivers/memory/tegra/tegra124-emc.c
@@ -9,16 +9,17 @@
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
+#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sort.h>
#include <linux/string.h>
-#include <soc/tegra/emc.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/mc.h>
@@ -562,8 +563,8 @@ static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
return timing;
}
-int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
- unsigned long rate)
+static int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
+ unsigned long rate)
{
struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
struct emc_timing *last = &emc->last_timing;
@@ -790,8 +791,8 @@ int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
return 0;
}
-void tegra_emc_complete_timing_change(struct tegra_emc *emc,
- unsigned long rate)
+static void tegra_emc_complete_timing_change(struct tegra_emc *emc,
+ unsigned long rate)
{
struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
struct emc_timing *last = &emc->last_timing;
@@ -986,6 +987,7 @@ static const struct of_device_id tegra_emc_of_match[] = {
{ .compatible = "nvidia,tegra124-emc" },
{}
};
+MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
static struct device_node *
tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
@@ -1251,9 +1253,20 @@ static int tegra_emc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, emc);
+ tegra124_clk_register_emc(pdev->dev.of_node,
+ tegra_emc_prepare_timing_change,
+ tegra_emc_complete_timing_change);
+
if (IS_ENABLED(CONFIG_DEBUG_FS))
emc_debugfs_init(&pdev->dev, emc);
+ /*
+ * Don't allow the kernel module to be unloaded. Unloading adds some
+ * extra complexity which doesn't really worth the effort in a case of
+ * this driver.
+ */
+ try_module_get(THIS_MODULE);
+
return 0;
};
@@ -1265,9 +1278,8 @@ static struct platform_driver tegra_emc_driver = {
.suppress_bind_attrs = true,
},
};
+module_platform_driver(tegra_emc_driver);
-static int tegra_emc_init(void)
-{
- return platform_driver_register(&tegra_emc_driver);
-}
-subsys_initcall(tegra_emc_init);
+MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 3f01d43f0598..797b8bde18de 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -136,6 +136,8 @@ extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
extern void tegra210_clk_emc_update_setting(u32 emc_src_value);
struct clk;
+struct device_node;
+struct tegra_emc;
typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
unsigned long min_rate,
@@ -146,6 +148,15 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
void *cb_arg);
int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
+typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc,
+ unsigned long rate);
+typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc,
+ unsigned long rate);
+struct clk *
+tegra124_clk_register_emc(struct device_node *emc_np,
+ tegra124_emc_prepare_timing_change_cb *prep_cb,
+ tegra124_emc_complete_timing_change_cb *complete_cb);
+
struct tegra210_clk_emc_config {
unsigned long rate;
bool same_freq;
diff --git a/include/soc/tegra/emc.h b/include/soc/tegra/emc.h
deleted file mode 100644
index 05199a97ccf4..000000000000
--- a/include/soc/tegra/emc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2014 NVIDIA Corporation. All rights reserved.
- */
-
-#ifndef __SOC_TEGRA_EMC_H__
-#define __SOC_TEGRA_EMC_H__
-
-struct tegra_emc;
-
-int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
- unsigned long rate);
-void tegra_emc_complete_timing_change(struct tegra_emc *emc,
- unsigned long rate);
-
-#endif /* __SOC_TEGRA_EMC_H__ */
--
2.26.0
^ permalink raw reply related
* [PATCH v4 05/37] memory: tegra30-emc: Make driver modular
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra, linux-pm, linux-kernel,
dri-devel, devicetree
In-Reply-To: <20200609131404.17523-1-digetx@gmail.com>
This patch adds modularization support to the Tegra30 EMC driver. Driver
now can be compiled as a loadable kernel module.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/mc.c | 3 +++
drivers/memory/tegra/tegra30-emc.c | 17 ++++++++++++-----
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index 7e0e1ef87763..bd453de9d446 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -18,7 +18,7 @@ config TEGRA20_EMC
external memory.
config TEGRA30_EMC
- bool "NVIDIA Tegra30 External Memory Controller driver"
+ tristate "NVIDIA Tegra30 External Memory Controller driver"
default y
depends on TEGRA_MC && ARCH_TEGRA_3x_SOC
help
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index ec8403557ed4..772aa021b5f6 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -6,6 +6,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
+#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
@@ -298,6 +299,7 @@ int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
return 0;
}
+EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration);
unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
{
@@ -309,6 +311,7 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
return dram_count;
}
+EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count);
static int load_one_timing(struct tegra_mc *mc,
struct tegra_mc_timing *timing,
diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c
index 055af0e08a2e..85d4effb8e6f 100644
--- a/drivers/memory/tegra/tegra30-emc.c
+++ b/drivers/memory/tegra/tegra30-emc.c
@@ -1343,6 +1343,13 @@ static int tegra_emc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, emc);
tegra_emc_debugfs_init(emc);
+ /*
+ * Don't allow the kernel module to be unloaded. Unloading adds some
+ * extra complexity which doesn't really worth the effort in a case of
+ * this driver.
+ */
+ try_module_get(THIS_MODULE);
+
return 0;
unset_cb:
@@ -1393,6 +1400,7 @@ static const struct of_device_id tegra_emc_of_match[] = {
{ .compatible = "nvidia,tegra30-emc", },
{},
};
+MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
static struct platform_driver tegra_emc_driver = {
.probe = tegra_emc_probe,
@@ -1403,9 +1411,8 @@ static struct platform_driver tegra_emc_driver = {
.suppress_bind_attrs = true,
},
};
+module_platform_driver(tegra_emc_driver);
-static int __init tegra_emc_init(void)
-{
- return platform_driver_register(&tegra_emc_driver);
-}
-subsys_initcall(tegra_emc_init);
+MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver");
+MODULE_LICENSE("GPL v2");
--
2.26.0
^ permalink raw reply related
* [PATCH v4 04/37] memory: tegra20-emc: Make driver modular
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This patch adds modularization support to the Tegra20 EMC driver. Driver
now can be compiled as a loadable kernel module.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/tegra20-emc.c | 17 ++++++++++++-----
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index 9f0a96bf9ccc..7e0e1ef87763 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -8,7 +8,7 @@ config TEGRA_MC
NVIDIA Tegra SoCs.
config TEGRA20_EMC
- bool "NVIDIA Tegra20 External Memory Controller driver"
+ tristate "NVIDIA Tegra20 External Memory Controller driver"
default y
depends on ARCH_TEGRA_2x_SOC
help
diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 027f46287dbf..0baa6590adea 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -724,6 +724,13 @@ static int tegra_emc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, emc);
tegra_emc_debugfs_init(emc);
+ /*
+ * Don't allow the kernel module to be unloaded. Unloading adds some
+ * extra complexity which doesn't really worth the effort in a case of
+ * this driver.
+ */
+ try_module_get(THIS_MODULE);
+
return 0;
unset_cb:
@@ -736,6 +743,7 @@ static const struct of_device_id tegra_emc_of_match[] = {
{ .compatible = "nvidia,tegra20-emc", },
{},
};
+MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
static struct platform_driver tegra_emc_driver = {
.probe = tegra_emc_probe,
@@ -745,9 +753,8 @@ static struct platform_driver tegra_emc_driver = {
.suppress_bind_attrs = true,
},
};
+module_platform_driver(tegra_emc_driver);
-static int __init tegra_emc_init(void)
-{
- return platform_driver_register(&tegra_emc_driver);
-}
-subsys_initcall(tegra_emc_init);
+MODULE_AUTHOR("Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver");
+MODULE_LICENSE("GPL v2");
--
2.26.0
^ permalink raw reply related
* [PATCH v4 03/37] clk: tegra: Export Tegra20 EMC kernel symbols
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
We're going to modularize Tegra EMC drivers and some of the EMC clk driver
symbols need to be exported, let's export them.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clk/tegra/clk-tegra20-emc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra20-emc.c b/drivers/clk/tegra/clk-tegra20-emc.c
index 03bf0009a33c..dd74b8543bf1 100644
--- a/drivers/clk/tegra/clk-tegra20-emc.c
+++ b/drivers/clk/tegra/clk-tegra20-emc.c
@@ -13,6 +13,7 @@
#include <linux/clk-provider.h>
#include <linux/clk/tegra.h>
#include <linux/err.h>
+#include <linux/export.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
@@ -235,6 +236,7 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
emc->cb_arg = cb_arg;
}
}
+EXPORT_SYMBOL_GPL(tegra20_clk_set_emc_round_callback);
bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw)
{
@@ -291,3 +293,4 @@ int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
return 0;
}
+EXPORT_SYMBOL_GPL(tegra20_clk_prepare_emc_mc_same_freq);
--
2.26.0
^ permalink raw reply related
* [PATCH v4 02/37] clk: tegra: Remove Memory Controller lock
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra, linux-pm, linux-kernel,
dri-devel, devicetree
In-Reply-To: <20200609131404.17523-1-digetx@gmail.com>
The shared Memory Controller lock isn't needed since the time when
Memory Clock was made read-only. The lock could be removed safely now.
Hence let's remove it, this will help a tad to make further patches
cleaner.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-divider.c | 4 ++--
drivers/clk/tegra/clk-tegra114.c | 6 ++----
drivers/clk/tegra/clk-tegra124.c | 7 ++-----
drivers/clk/tegra/clk-tegra20.c | 3 +--
drivers/clk/tegra/clk-tegra30.c | 3 +--
drivers/clk/tegra/clk.h | 2 +-
6 files changed, 9 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 38daf483ddf1..56adb01638cc 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -177,10 +177,10 @@ static const struct clk_div_table mc_div_table[] = {
};
struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
- void __iomem *reg, spinlock_t *lock)
+ void __iomem *reg)
{
return clk_register_divider_table(NULL, name, parent_name,
CLK_IS_CRITICAL,
reg, 16, 1, CLK_DIVIDER_READ_ONLY,
- mc_div_table, lock);
+ mc_div_table, NULL);
}
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index bc9e47a4cb60..ca8d9737d301 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -134,7 +134,6 @@ static DEFINE_SPINLOCK(pll_d_lock);
static DEFINE_SPINLOCK(pll_d2_lock);
static DEFINE_SPINLOCK(pll_u_lock);
static DEFINE_SPINLOCK(pll_re_lock);
-static DEFINE_SPINLOCK(emc_lock);
static struct div_nmp pllxc_nmp = {
.divm_shift = 0,
@@ -1050,10 +1049,9 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
ARRAY_SIZE(mux_pllmcp_clkm),
CLK_SET_RATE_NO_REPARENT,
clk_base + CLK_SOURCE_EMC,
- 29, 3, 0, &emc_lock);
+ 29, 3, 0, NULL);
- clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
- &emc_lock);
+ clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC);
clks[TEGRA114_CLK_MC] = clk;
clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index e931319dcc9d..0c956e14b9ca 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -126,7 +126,6 @@ static DEFINE_SPINLOCK(pll_d_lock);
static DEFINE_SPINLOCK(pll_e_lock);
static DEFINE_SPINLOCK(pll_re_lock);
static DEFINE_SPINLOCK(pll_u_lock);
-static DEFINE_SPINLOCK(emc_lock);
static DEFINE_SPINLOCK(sor0_lock);
/* possible OSC frequencies in Hz */
@@ -1050,8 +1049,7 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
periph_clk_enb_refcnt);
clks[TEGRA124_CLK_DSIB] = clk;
- clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
- &emc_lock);
+ clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC);
clks[TEGRA124_CLK_MC] = clk;
/* cml0 */
@@ -1518,8 +1516,7 @@ static void __init tegra124_132_clock_init_post(struct device_node *np)
tegra124_reset_deassert);
tegra_add_of_provider(np, of_clk_src_onecell_get);
- clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
- &emc_lock);
+ clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, NULL);
tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 3efc651b42e3..2f8b6de4198f 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -802,8 +802,7 @@ static void __init tegra20_periph_clk_init(void)
clks[TEGRA20_CLK_EMC] = clk;
- clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
- NULL);
+ clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC);
clks[TEGRA20_CLK_MC] = clk;
/* dsi */
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 37244a7e68c2..88e8c485f8ae 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1042,8 +1042,7 @@ static void __init tegra30_periph_clk_init(void)
clks[TEGRA30_CLK_EMC] = clk;
- clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
- NULL);
+ clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC);
clks[TEGRA30_CLK_MC] = clk;
/* cml0 */
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 6b565f6b5f66..5ed8b95d331c 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -136,7 +136,7 @@ struct clk *tegra_clk_register_divider(const char *name,
unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
u8 frac_width, spinlock_t *lock);
struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
- void __iomem *reg, spinlock_t *lock);
+ void __iomem *reg);
/*
* Tegra PLL:
--
2.26.0
^ permalink raw reply related
* [PATCH v4 01/37] clk: Export clk_hw_reparent()
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
We're going to turn Tegra124 Memory Controller driver into a loadable
kernel module. The driver uses clk_hw_reparent(), which isn't an exported
kernel symbol. Let's export that function in order to allow modularization
of the Tegra driver.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clk/clk.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 3f588ed06ce3..2fa6394d9a1b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2439,6 +2439,7 @@ void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
}
+EXPORT_SYMBOL_GPL(clk_hw_reparent);
/**
* clk_has_parent - check if a clock is a possible parent for another
--
2.26.0
^ permalink raw reply related
* [PATCH v4 00/37] Introduce memory interconnect for NVIDIA Tegra SoCs
From: Dmitry Osipenko @ 2020-06-09 13:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Georgi Djakov, Rob Herring,
Michael Turquette, Stephen Boyd, Peter De Schrijver, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, Mikko Perttunen
Cc: Artur Świgoń, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hello,
This series brings initial support for memory interconnect to Tegra20 and
Tegra30 SoCs.
For the starter only display controllers are getting interconnect API
support, others could be supported later on. The display controllers
have the biggest demand for interconnect API right now because dynamic
memory frequency scaling can't be done safely without taking into account
bandwidth requirement from the displays.
Changelog:
v4: - All drivers that use interconnect API now select it in the Kconfig in
order to properly express the build dependency.
- The IS_ENABLED(CONFIG_INTERCONNECT) is dropped now from all patches.
- Added MODULE_AUTHOR() to the modularized drivers, for completeness.
- Added missed TEGRA_MC Kconfig dependency for the Tegra20 EMC driver.
- Added more acks from Rob Herring that I accidentally missed to add in v3.
v3: - Added acks from Rob Herring that were given to some of the v2 patches.
- Specified name of the TRM documentation chapter in the patch
"dt-bindings: host1x: Document new interconnect properties", which was
suggested by Rob Herring in the review comment to v2.
- Added patches that allow EMC drivers to be compiled as a loadable kernel
modules. This came up during of the v2 review when Georgi Djakov pointed
out that interconnect-core could be compiled as a kernel module. Please
note that the Tegra124 EMC driver is compile-tested only, I don't have
Tegra124 HW.
- In the review comment to [1] Stephen Boyd suggested that it will be
better not to make changes to clk API, which was needed in order to
avoid clashing of the interconnect driver with the devfreq in regards
to memory clk-rate rounding.
[1] https://patchwork.ozlabs.org/project/linux-tegra/patch/20200330231617.17079-3-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org/
Stephen Boyd suggested that instead we should provide OPP table via DT.
I tried to investigate whether this could be done and turned out
it's a bit complicated. Technically it should be doable, but:
1. For now we don't fully support voltage scaling of the CORE regulator
and so OPP table in the DT isn't really needed today. We can
generate table from the memory timings, which is what Tegra devfreq
drivers already do.
2. The OPP table should be defined in the DT for the Memory Controller
node and then its usage somehow should be shared by both interconnect
and devfreq drivers. It's not obvious what's the best way to do it.
So, it will be much better to postpone the DT OPP table addition
until these questions are resolved. We can infer OPPs from the
memory timings and we could get the memory rates from the memory
driver directly, avoiding the problems induced by the clk API usage.
This idea is implemented in v3, see these patches:
PM / devfreq: tegra20: Use MC timings for building OPP table
PM / devfreq: tegra30: Use MC timings for building OPP table
v2: - Instead of a single dma-mem interconnect path, the paths are now
defined per memory client.
- The EMC provider now uses #interconnect-cells=<0>.
- Dropped Tegra124 because there is no enough information about how to
properly calculate required EMC clock rate for it and I don't have
hardware for testing. Somebody else will have to work on it.
- Moved interconnect providers code into drivers/memory/tegra/*.
- Added "Create tegra20-devfreq device" patch because interconnect
is not very usable without the devfreq memory auto-scaling since
memory freq will be fixed to the display's requirement.
Artur Świgoń (1):
interconnect: Relax requirement in of_icc_get_from_provider()
Dmitry Osipenko (36):
clk: Export clk_hw_reparent()
clk: tegra: Remove Memory Controller lock
clk: tegra: Export Tegra20 EMC kernel symbols
memory: tegra20-emc: Make driver modular
memory: tegra30-emc: Make driver modular
memory: tegra124-emc: Make driver modular
memory: tegra124-emc: Use devm_platform_ioremap_resource
soc/tegra: fuse: Export tegra_read_ram_code()
memory: tegra20-emc: Initialize MC timings
PM / devfreq: tegra20: Silence deferred probe error
PM / devfreq: tegra30: Silence deferred probe error
PM / devfreq: tegra20: Use MC timings for building OPP table
PM / devfreq: tegra30: Use MC timings for building OPP table
PM / devfreq: tegra20: Add error messages to tegra_devfreq_target()
PM / devfreq: tegra30: Add error messages to tegra_devfreq_target()
PM / devfreq: tegra20: Adjust clocks conversion ratio and polling
interval
PM / devfreq: tegra20: Relax Kconfig dependency
dt-bindings: memory: tegra20: mc: Document new interconnect property
dt-bindings: memory: tegra20: emc: Document new interconnect property
dt-bindings: memory: tegra30: mc: Document new interconnect property
dt-bindings: memory: tegra30: emc: Document new interconnect property
dt-bindings: host1x: Document new interconnect properties
dt-bindings: memory: tegra20: Add memory client IDs
dt-bindings: memory: tegra30: Add memory client IDs
ARM: tegra: Add interconnect properties to Tegra20 device-tree
ARM: tegra: Add interconnect properties to Tegra30 device-tree
memory: tegra: Register as interconnect provider
memory: tegra20-emc: Use devm_platform_ioremap_resource
memory: tegra20-emc: Continue probing if timings are missing in
device-tree
memory: tegra20-emc: Register as interconnect provider
memory: tegra20-emc: Create tegra20-devfreq device
memory: tegra30-emc: Continue probing if timings are missing in
device-tree
memory: tegra30-emc: Register as interconnect provider
drm/tegra: dc: Support memory bandwidth management
drm/tegra: dc: Tune up high priority request controls for Tegra20
drm/tegra: dc: Extend debug stats with total number of events
.../display/tegra/nvidia,tegra20-host1x.txt | 68 +++++
.../memory-controllers/nvidia,tegra20-emc.txt | 2 +
.../memory-controllers/nvidia,tegra20-mc.txt | 3 +
.../nvidia,tegra30-emc.yaml | 6 +
.../memory-controllers/nvidia,tegra30-mc.yaml | 5 +
arch/arm/boot/dts/tegra20.dtsi | 22 +-
arch/arm/boot/dts/tegra30.dtsi | 23 +-
drivers/clk/clk.c | 1 +
drivers/clk/tegra/clk-divider.c | 4 +-
drivers/clk/tegra/clk-tegra114.c | 6 +-
drivers/clk/tegra/clk-tegra124-emc.c | 63 ++--
drivers/clk/tegra/clk-tegra124.c | 8 +-
drivers/clk/tegra/clk-tegra20-emc.c | 3 +
drivers/clk/tegra/clk-tegra20.c | 3 +-
drivers/clk/tegra/clk-tegra30.c | 3 +-
drivers/clk/tegra/clk.h | 14 +-
drivers/devfreq/Kconfig | 2 +-
drivers/devfreq/tegra20-devfreq.c | 52 ++--
drivers/devfreq/tegra30-devfreq.c | 115 +++++--
drivers/gpu/drm/tegra/Kconfig | 1 +
drivers/gpu/drm/tegra/dc.c | 289 +++++++++++++++++-
drivers/gpu/drm/tegra/dc.h | 13 +
drivers/gpu/drm/tegra/drm.c | 19 ++
drivers/gpu/drm/tegra/plane.c | 1 +
drivers/gpu/drm/tegra/plane.h | 4 +-
drivers/interconnect/core.c | 11 +-
drivers/memory/tegra/Kconfig | 9 +-
drivers/memory/tegra/mc.c | 117 +++++++
drivers/memory/tegra/mc.h | 8 +
drivers/memory/tegra/tegra124-emc.c | 36 ++-
drivers/memory/tegra/tegra20-emc.c | 215 +++++++++++--
drivers/memory/tegra/tegra30-emc.c | 156 ++++++++--
drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 +
include/dt-bindings/memory/tegra20-mc.h | 53 ++++
include/dt-bindings/memory/tegra30-mc.h | 67 ++++
include/linux/clk/tegra.h | 11 +
include/soc/tegra/emc.h | 16 -
include/soc/tegra/mc.h | 3 +
38 files changed, 1235 insertions(+), 199 deletions(-)
delete mode 100644 include/soc/tegra/emc.h
--
2.26.0
^ permalink raw reply
* Re: [PATCH v6 3/4] mmc: mediatek: command queue support
From: Matthias Brugger @ 2020-06-09 11:28 UTC (permalink / raw)
To: Chun-Hung Wu, mirq-linux, Jonathan Hunter, Al Cooper,
Adrian Hunter, Florian Fainelli, bcm-kernel-feedback-list,
Andy Gross, Bjorn Andersson, Michal Simek, Thierry Reding,
Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland,
Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman,
Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison
Cc: devicetree, wsd_upstream, linux-arm-msm, linux-mmc, linux-kernel,
linux-mediatek, linux-tegra, kernel-team, linux-arm-kernel
In-Reply-To: <1591665502-6573-4-git-send-email-chun-hung.wu@mediatek.com>
On 09/06/2020 03:18, Chun-Hung Wu wrote:
> Support command queue for mt6779 platform.
> a. Add msdc_set_busy_timeout() to calculate emmc write timeout.
> b. Connect mtk msdc driver to cqhci driver through
> host->cq_host->ops = &msdc_cmdq_ops;
> c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides
> more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO.
> d. Use the options below to separate support for CQHCI or not, because
> some of our platform does not support CQHCI hence no kernel option:
> CONFIG_MMC_CQHCI.
> #if IS_ENABLED(CONFIG_MMC_CQHCI)
> XXX //Support CQHCI
> #else
> XXX //Not support CQHCI
> #endif
>
I think that we don't need the #if IS_ENABLED() because we add a boolean in the
msdc_host.
> Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>
> ---
> drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 119 insertions(+)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 84a7bd44..9d69269 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -31,6 +31,8 @@
> #include <linux/mmc/sdio.h>
> #include <linux/mmc/slot-gpio.h>
>
> +#include "cqhci.h"
> +
> #define MAX_BD_NUM 1024
>
> /*--------------------------------------------------------------------------*/
> @@ -152,6 +154,7 @@
> #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
> #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
> #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
> +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */
>
> /* MSDC_INTEN mask */
> #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
> @@ -182,6 +185,7 @@
> /* SDC_CFG mask */
> #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
> #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
> +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */
> #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
> #define SDC_CFG_SDIO (0x1 << 19) /* RW */
> #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
> @@ -230,6 +234,7 @@
> #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
>
> #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
> +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */
> #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
>
> #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
> @@ -431,9 +436,11 @@ struct msdc_host {
> /* cmd response sample selection for HS400 */
> bool hs400_mode; /* current eMMC will run at hs400 mode */
> bool internal_cd; /* Use internal card-detect logic */
> + bool cqhci; /* support eMMC hw cmdq */
> struct msdc_save_para save_para; /* used when gate HCLK */
> struct msdc_tune_para def_tune_para; /* default tune setting */
> struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
> + struct cqhci_host *cq_host;
> };
>
> static const struct mtk_mmc_compatible mt8135_compat = {
> @@ -764,6 +771,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
> (u32)(timeout > 255 ? 255 : timeout));
> }
>
> +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
> +{
> + u64 timeout;
> +
> + timeout = msdc_timeout_cal(host, ns, clks);
> + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
> + (u32)(timeout > 8191 ? 8191 : timeout));
> +}
> +
> static void msdc_gate_clock(struct msdc_host *host)
> {
> clk_disable_unprepare(host->src_clk_cg);
> @@ -1480,6 +1496,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
> pm_runtime_put_noidle(host->dev);
> }
>
> +#if IS_ENABLED(CONFIG_MMC_CQHCI)
> +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
> +{
> + int cmd_err = 0, dat_err = 0;
> +
> + if (intsts & MSDC_INT_RSPCRCERR) {
> + cmd_err = -EILSEQ;
> + dev_err(host->dev, "%s: CMD CRC ERR", __func__);
> + } else if (intsts & MSDC_INT_CMDTMO) {
> + cmd_err = -ETIMEDOUT;
> + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
> + }
> +
> + if (intsts & MSDC_INT_DATCRCERR) {
> + dat_err = -EILSEQ;
> + dev_err(host->dev, "%s: DATA CRC ERR", __func__);
> + } else if (intsts & MSDC_INT_DATTMO) {
> + dat_err = -ETIMEDOUT;
> + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
> + }
> +
> + if (cmd_err || dat_err) {
> + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
> + cmd_err, dat_err, intsts);
> + }
> +
> + return cqhci_irq(host->mmc, 0, cmd_err, dat_err);
> +}
> +#endif
> +
> static irqreturn_t msdc_irq(int irq, void *dev_id)
> {
> struct msdc_host *host = (struct msdc_host *) dev_id;
> @@ -1516,6 +1562,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id)
> if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
> break;
>
> +#if IS_ENABLED(CONFIG_MMC_CQHCI)
> + if ((host->mmc->caps2 & MMC_CAP2_CQE) &&
> + (events & MSDC_INT_CMDQ)) {
> + msdc_cmdq_irq(host, events);
> + /* clear interrupts */
> + writel(events, host->base + MSDC_INT);
> + return IRQ_HANDLED;
> + }
> +#endif
> +
> if (!mrq) {
> dev_err(host->dev,
> "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
> @@ -2200,6 +2256,36 @@ static int msdc_get_cd(struct mmc_host *mmc)
> return !val;
> }
>
> +static void msdc_cqe_enable(struct mmc_host *mmc)
> +{
> + struct msdc_host *host = mmc_priv(mmc);
> +
> + /* enable cmdq irq */
> + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
> + /* enable busy check */
> + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
> + /* default write data / busy timeout 20s */
> + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
> + /* default read data timeout 1s */
> + msdc_set_timeout(host, 1000000000ULL, 0);
> +}
> +
> +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
> +{
> + struct msdc_host *host = mmc_priv(mmc);
> +
> + /* disable cmdq irq */
> + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
> + /* disable busy check */
> + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
> +
> + if (recovery) {
> + sdr_set_field(host->base + MSDC_DMA_CTRL,
> + MSDC_DMA_CTRL_STOP, 1);
> + msdc_reset_hw(host);
> + }
> +}
> +
> static const struct mmc_host_ops mt_msdc_ops = {
> .post_req = msdc_post_req,
> .pre_req = msdc_pre_req,
> @@ -2216,6 +2302,11 @@ static int msdc_get_cd(struct mmc_host *mmc)
> .hw_reset = msdc_hw_reset,
> };
>
> +static const struct cqhci_host_ops msdc_cmdq_ops = {
> + .enable = msdc_cqe_enable,
> + .disable = msdc_cqe_disable,
> +};
> +
> static void msdc_of_property_parse(struct platform_device *pdev,
> struct msdc_host *host)
> {
> @@ -2236,6 +2327,12 @@ static void msdc_of_property_parse(struct platform_device *pdev,
> host->hs400_cmd_resp_sel_rising = true;
> else
> host->hs400_cmd_resp_sel_rising = false;
> +
> + if (of_property_read_bool(pdev->dev.of_node,
> + "mediatek,cqhci"))
> + host->cqhci = true;
> + else
> + host->cqhci = false;
Does this mean that there are mt6779 contoller which do not support cqhci?
Otherwise could add the boolean in struct mtk_mmc_compatible and get rid of the
device tree requirement.
Regards,
Matthias
^ permalink raw reply
* Re: [PATCH v6 1/4] mmc: mediatek: add MT6779 MMC driver support
From: Matthias Brugger @ 2020-06-09 11:25 UTC (permalink / raw)
To: Chun-Hung Wu, mirq-linux, Jonathan Hunter, Al Cooper,
Adrian Hunter, Florian Fainelli, bcm-kernel-feedback-list,
Andy Gross, Bjorn Andersson, Michal Simek, Thierry Reding,
Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland,
Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman,
Martin
Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree,
wsd_upstream, linux-arm-kernel, linux-arm-msm, linux-tegra
In-Reply-To: <1591665502-6573-2-git-send-email-chun-hung.wu@mediatek.com>
On 09/06/2020 03:18, Chun-Hung Wu wrote:
> MT6779 add cqhci support, so need to add new code
> to support it.
>
Please work on the commit message. For example it mentions cqhci while the code
does not. Better describe what technical specification the controller has etc
> Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>
> ---
> drivers/mmc/host/mtk-sd.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index b221c02..8ada675 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -538,6 +538,18 @@ struct msdc_host {
> .use_internal_cd = true,
> };
>
> +static const struct mtk_mmc_compatible mt6779_compat = {
> + .clk_div_bits = 12,
> + .hs400_tune = false,
> + .pad_tune_reg = MSDC_PAD_TUNE0,
> + .async_fifo = true,
> + .data_tune = true,
> + .busy_check = true,
> + .stop_clk_fix = true,
> + .enhance_rx = true,
> + .support_64g = true,
> +};
> +
> static const struct of_device_id msdc_of_ids[] = {
> { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
> { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
> @@ -547,6 +559,7 @@ struct msdc_host {
> { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
> { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
> { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
> + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
> {}
> };
> MODULE_DEVICE_TABLE(of, msdc_of_ids);
>
^ permalink raw reply
* [PATCH v6 4/4] dt-bindings: mmc: mediatek: Add document for mt6779
From: Chun-Hung Wu @ 2020-06-09 1:18 UTC (permalink / raw)
To: mirq-linux, Jonathan Hunter, Al Cooper, Adrian Hunter,
Florian Fainelli, bcm-kernel-feedback-list, Andy Gross,
Bjorn Andersson, Michal Simek, Thierry Reding, Chaotian Jing,
Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger,
Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman,
Martin
Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree,
wsd_upstream, linux-arm-kernel, linux-arm-msm, linux-tegra,
Chun-Hung Wu
In-Reply-To: <1591665502-6573-1-git-send-email-chun-hung.wu@mediatek.com>
Add compatible node for mt6779 mmc and HW cmdq selection
node "mediatek,cqhci".
Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index 8a532f4..d4d20b9 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
+ "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
"mediatek,mt7622-mmc": for MT7622 SoC
@@ -49,6 +50,9 @@ Optional properties:
error caused by stop clock(fifo full)
Valid range = [0:0x7]. if not present, default value is 0.
applied to compatible "mediatek,mt2701-mmc".
+- mediatek,cqhci: HW cmdq selection
+ If present, hw command queue is enabled.
+ If not present, hw command queue is disabled.
Examples:
mmc0: mmc@11230000 {
--
1.9.1
^ permalink raw reply related
* [PATCH v6 3/4] mmc: mediatek: command queue support
From: Chun-Hung Wu @ 2020-06-09 1:18 UTC (permalink / raw)
To: mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw, Jonathan Hunter, Al Cooper,
Adrian Hunter, Florian Fainelli,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Andy Gross,
Bjorn Andersson, Michal Simek, Thierry Reding, Chaotian Jing,
Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger,
Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman,
Martin
Cc: kernel-team-z5hGa2qSFaRBDgjK7y7TUQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Chun-Hung Wu
In-Reply-To: <1591665502-6573-1-git-send-email-chun-hung.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Support command queue for mt6779 platform.
a. Add msdc_set_busy_timeout() to calculate emmc write timeout.
b. Connect mtk msdc driver to cqhci driver through
host->cq_host->ops = &msdc_cmdq_ops;
c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides
more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO.
d. Use the options below to separate support for CQHCI or not, because
some of our platform does not support CQHCI hence no kernel option:
CONFIG_MMC_CQHCI.
#if IS_ENABLED(CONFIG_MMC_CQHCI)
XXX //Support CQHCI
#else
XXX //Not support CQHCI
#endif
Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 84a7bd44..9d69269 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -31,6 +31,8 @@
#include <linux/mmc/sdio.h>
#include <linux/mmc/slot-gpio.h>
+#include "cqhci.h"
+
#define MAX_BD_NUM 1024
/*--------------------------------------------------------------------------*/
@@ -152,6 +154,7 @@
#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
+#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */
/* MSDC_INTEN mask */
#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
@@ -182,6 +185,7 @@
/* SDC_CFG mask */
#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
+#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */
#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
#define SDC_CFG_SDIO (0x1 << 19) /* RW */
#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
@@ -230,6 +234,7 @@
#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
+#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */
#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
@@ -431,9 +436,11 @@ struct msdc_host {
/* cmd response sample selection for HS400 */
bool hs400_mode; /* current eMMC will run at hs400 mode */
bool internal_cd; /* Use internal card-detect logic */
+ bool cqhci; /* support eMMC hw cmdq */
struct msdc_save_para save_para; /* used when gate HCLK */
struct msdc_tune_para def_tune_para; /* default tune setting */
struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
+ struct cqhci_host *cq_host;
};
static const struct mtk_mmc_compatible mt8135_compat = {
@@ -764,6 +771,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
(u32)(timeout > 255 ? 255 : timeout));
}
+static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
+{
+ u64 timeout;
+
+ timeout = msdc_timeout_cal(host, ns, clks);
+ sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
+ (u32)(timeout > 8191 ? 8191 : timeout));
+}
+
static void msdc_gate_clock(struct msdc_host *host)
{
clk_disable_unprepare(host->src_clk_cg);
@@ -1480,6 +1496,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
pm_runtime_put_noidle(host->dev);
}
+#if IS_ENABLED(CONFIG_MMC_CQHCI)
+static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
+{
+ int cmd_err = 0, dat_err = 0;
+
+ if (intsts & MSDC_INT_RSPCRCERR) {
+ cmd_err = -EILSEQ;
+ dev_err(host->dev, "%s: CMD CRC ERR", __func__);
+ } else if (intsts & MSDC_INT_CMDTMO) {
+ cmd_err = -ETIMEDOUT;
+ dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
+ }
+
+ if (intsts & MSDC_INT_DATCRCERR) {
+ dat_err = -EILSEQ;
+ dev_err(host->dev, "%s: DATA CRC ERR", __func__);
+ } else if (intsts & MSDC_INT_DATTMO) {
+ dat_err = -ETIMEDOUT;
+ dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
+ }
+
+ if (cmd_err || dat_err) {
+ dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
+ cmd_err, dat_err, intsts);
+ }
+
+ return cqhci_irq(host->mmc, 0, cmd_err, dat_err);
+}
+#endif
+
static irqreturn_t msdc_irq(int irq, void *dev_id)
{
struct msdc_host *host = (struct msdc_host *) dev_id;
@@ -1516,6 +1562,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id)
if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
break;
+#if IS_ENABLED(CONFIG_MMC_CQHCI)
+ if ((host->mmc->caps2 & MMC_CAP2_CQE) &&
+ (events & MSDC_INT_CMDQ)) {
+ msdc_cmdq_irq(host, events);
+ /* clear interrupts */
+ writel(events, host->base + MSDC_INT);
+ return IRQ_HANDLED;
+ }
+#endif
+
if (!mrq) {
dev_err(host->dev,
"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
@@ -2200,6 +2256,36 @@ static int msdc_get_cd(struct mmc_host *mmc)
return !val;
}
+static void msdc_cqe_enable(struct mmc_host *mmc)
+{
+ struct msdc_host *host = mmc_priv(mmc);
+
+ /* enable cmdq irq */
+ writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
+ /* enable busy check */
+ sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
+ /* default write data / busy timeout 20s */
+ msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
+ /* default read data timeout 1s */
+ msdc_set_timeout(host, 1000000000ULL, 0);
+}
+
+void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
+{
+ struct msdc_host *host = mmc_priv(mmc);
+
+ /* disable cmdq irq */
+ sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
+ /* disable busy check */
+ sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
+
+ if (recovery) {
+ sdr_set_field(host->base + MSDC_DMA_CTRL,
+ MSDC_DMA_CTRL_STOP, 1);
+ msdc_reset_hw(host);
+ }
+}
+
static const struct mmc_host_ops mt_msdc_ops = {
.post_req = msdc_post_req,
.pre_req = msdc_pre_req,
@@ -2216,6 +2302,11 @@ static int msdc_get_cd(struct mmc_host *mmc)
.hw_reset = msdc_hw_reset,
};
+static const struct cqhci_host_ops msdc_cmdq_ops = {
+ .enable = msdc_cqe_enable,
+ .disable = msdc_cqe_disable,
+};
+
static void msdc_of_property_parse(struct platform_device *pdev,
struct msdc_host *host)
{
@@ -2236,6 +2327,12 @@ static void msdc_of_property_parse(struct platform_device *pdev,
host->hs400_cmd_resp_sel_rising = true;
else
host->hs400_cmd_resp_sel_rising = false;
+
+ if (of_property_read_bool(pdev->dev.of_node,
+ "mediatek,cqhci"))
+ host->cqhci = true;
+ else
+ host->cqhci = false;
}
static int msdc_drv_probe(struct platform_device *pdev)
@@ -2351,6 +2448,8 @@ static int msdc_drv_probe(struct platform_device *pdev)
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
+ if (host->cqhci)
+ mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
/* MMC core transfer sizes tunable parameters */
mmc->max_segs = MAX_BD_NUM;
if (host->dev_comp->support_64g)
@@ -2366,6 +2465,26 @@ static int msdc_drv_probe(struct platform_device *pdev)
host->dma_mask = DMA_BIT_MASK(32);
mmc_dev(mmc)->dma_mask = &host->dma_mask;
+#if IS_ENABLED(CONFIG_MMC_CQHCI)
+ if (mmc->caps2 & MMC_CAP2_CQE) {
+ host->cq_host = devm_kzalloc(host->mmc->parent,
+ sizeof(*host->cq_host),
+ GFP_KERNEL);
+ if (!host->cq_host) {
+ ret = -ENOMEM;
+ goto host_free;
+ }
+ host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
+ host->cq_host->mmio = host->base + 0x800;
+ host->cq_host->ops = &msdc_cmdq_ops;
+ cqhci_init(host->cq_host, mmc, true);
+ mmc->max_segs = 128;
+ /* cqhci 16bit length */
+ /* 0 size, means 65536 so we don't have to -1 here */
+ mmc->max_seg_size = 64 * 1024;
+ }
+#endif
+
host->timeout_clks = 3 * 1048576;
host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2 * sizeof(struct mt_gpdma_desc),
--
1.9.1
^ permalink raw reply related
* [PATCH v6 2/4] mmc: mediatek: refine msdc timeout api
From: Chun-Hung Wu @ 2020-06-09 1:18 UTC (permalink / raw)
To: mirq-linux, Jonathan Hunter, Al Cooper, Adrian Hunter,
Florian Fainelli, bcm-kernel-feedback-list, Andy Gross,
Bjorn Andersson, Michal Simek, Thierry Reding, Chaotian Jing,
Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger,
Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman,
Martin
Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree,
wsd_upstream, linux-arm-kernel, linux-arm-msm, linux-tegra,
Chun-Hung Wu
In-Reply-To: <1591665502-6573-1-git-send-email-chun-hung.wu@mediatek.com>
Extract msdc timeout api common part to have
better code architecture and avoid redundant code.
Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 8ada675..84a7bd44 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -723,21 +723,21 @@ static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
}
}
-/* clock control primitives */
-static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
+static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
{
- u32 timeout, clk_ns;
+ u64 timeout, clk_ns;
u32 mode = 0;
- host->timeout_ns = ns;
- host->timeout_clks = clks;
if (host->mmc->actual_clock == 0) {
timeout = 0;
} else {
- clk_ns = 1000000000UL / host->mmc->actual_clock;
- timeout = (ns + clk_ns - 1) / clk_ns + clks;
+ clk_ns = 1000000000ULL;
+ do_div(clk_ns, host->mmc->actual_clock);
+ timeout = ns + clk_ns - 1;
+ do_div(timeout, clk_ns);
+ timeout += clks;
/* in 1048576 sclk cycle unit */
- timeout = (timeout + (0x1 << 20) - 1) >> 20;
+ timeout = DIV_ROUND_UP(timeout, (0x1 << 20));
if (host->dev_comp->clk_div_bits == 8)
sdr_get_field(host->base + MSDC_CFG,
MSDC_CFG_CKMOD, &mode);
@@ -747,9 +747,21 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
/*DDR mode will double the clk cycles for data timeout */
timeout = mode >= 2 ? timeout * 2 : timeout;
timeout = timeout > 1 ? timeout - 1 : 0;
- timeout = timeout > 255 ? 255 : timeout;
}
- sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
+ return timeout;
+}
+
+/* clock control primitives */
+static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
+{
+ u64 timeout;
+
+ host->timeout_ns = ns;
+ host->timeout_clks = clks;
+
+ timeout = msdc_timeout_cal(host, ns, clks);
+ sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
+ (u32)(timeout > 255 ? 255 : timeout));
}
static void msdc_gate_clock(struct msdc_host *host)
--
1.9.1
^ permalink raw reply related
* [PATCH v6 1/4] mmc: mediatek: add MT6779 MMC driver support
From: Chun-Hung Wu @ 2020-06-09 1:18 UTC (permalink / raw)
To: mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw, Jonathan Hunter, Al Cooper,
Adrian Hunter, Florian Fainelli,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Andy Gross,
Bjorn Andersson, Michal Simek, Thierry Reding, Chaotian Jing,
Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger,
Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman,
Martin
Cc: kernel-team-z5hGa2qSFaRBDgjK7y7TUQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Chun-Hung Wu
In-Reply-To: <1591665502-6573-1-git-send-email-chun-hung.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
MT6779 add cqhci support, so need to add new code
to support it.
Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index b221c02..8ada675 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -538,6 +538,18 @@ struct msdc_host {
.use_internal_cd = true,
};
+static const struct mtk_mmc_compatible mt6779_compat = {
+ .clk_div_bits = 12,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE0,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+ .enhance_rx = true,
+ .support_64g = true,
+};
+
static const struct of_device_id msdc_of_ids[] = {
{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
@@ -547,6 +559,7 @@ struct msdc_host {
{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
+ { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
{}
};
MODULE_DEVICE_TABLE(of, msdc_of_ids);
--
1.9.1
^ permalink raw reply related
* [PATCH v6 0/4] mmc: mediatek: add mmc cqhci support
From: Chun-Hung Wu @ 2020-06-09 1:18 UTC (permalink / raw)
To: mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw, Jonathan Hunter, Al Cooper,
Adrian Hunter, Florian Fainelli,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Andy Gross,
Bjorn Andersson, Michal Simek, Thierry Reding, Chaotian Jing,
Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger,
Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman,
Martin
Cc: kernel-team-z5hGa2qSFaRBDgjK7y7TUQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Chun-Hung Wu
This series provides MediaTek cqhci implementations as below:
- Extend mmc_of_parse() to parse CQE bindings
- Remove redundant host CQE bindings
- Refine msdc timeout api to reduce redundant code
- MediaTek command queue support
- dt-bindings for mt6779
v1 -> v2:
- Add more patch details in commit message
- Separate msdc timeout api refine to individual patch
v2 -> v3:
- Remove CR-Id, Change-Id and Feature in patches
- Add Signed-off-by in patches
v3 -> v4:
- Refine CQE bindings in mmc_of_parse (Ulf Hansson)
- Remove redundant host CQE bindings (Linux Walleij)
v4 -> v5:
- Add Acked-by and more maintainers
v5 -> v6:
- Move CQE bindings back to vendor driver
- Add mt6779 mmc support as an individual patch
- Error handling for cq_host devm_kzallo()
Chun-Hung Wu (4):
[1/4] mmc: mediatek: add MT6779 MMC driver support
[2/4] mmc: mediatek: refine msdc timeout api
[3/4] mmc: mediatek: command queue support
[4/4] dt-bindings: mmc: mediatek: Add document for mt6779
Documentation/devicetree/bindings/mmc/mtk-sd.txt | 4 +
drivers/mmc/host/mtk-sd.c | 164 +++++++++++++++++++++--
2 files changed, 158 insertions(+), 10 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH AUTOSEL 5.6 257/606] gpio: tegra: mask GPIO IRQs during IRQ shutdown
From: Sasha Levin @ 2020-06-08 23:06 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
stable-u79uwXL29TY76Z2rM5mHXA
Cc: Stephen Warren, Linus Walleij, Sasha Levin,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200608231211.3363633-1-sashal-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[ Upstream commit 0cf253eed5d2bdf7bb3152457b38f39b012955f7 ]
The driver currently leaves GPIO IRQs unmasked even when the GPIO IRQ
client has released the GPIO IRQ. This allows the HW to raise IRQs, and
SW to process them, after shutdown. Fix this by masking the IRQ when it's
shut down. This is usually taken care of by the irqchip core, but since
this driver has a custom irq_shutdown implementation, it must do this
explicitly itself.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Link: https://lore.kernel.org/r/20200427232605.11608-1-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org
Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Sasha Levin <sashal-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
drivers/gpio/gpio-tegra.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index acb99eff9939..86568154cdb3 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -368,6 +368,7 @@ static void tegra_gpio_irq_shutdown(struct irq_data *d)
struct tegra_gpio_info *tgi = bank->tgi;
unsigned int gpio = d->hwirq;
+ tegra_gpio_irq_mask(d);
gpiochip_unlock_as_irq(&tgi->gc, gpio);
}
--
2.25.1
^ permalink raw reply related
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