* [RFC PATCH v1 12/18] media: tegra-video: Add support for selection ioctl ops
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, frankc, hverkuil,
sakari.ailus, robh+dt, helen.koike
Cc: digetx, sboyd, gregkh, linux-media, devicetree, linux-tegra,
linux-kernel, linux-i2c
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com>
This patch adds selection v4l2 ioctl operations to allow configuring
a selection rectangle in the sensor through the Tegra video device
node.
Some sensor drivers supporting crop uses try_crop rectangle from
v4l2_subdev_pad_config during try format for computing binning.
So with selection ops support, this patch also updates try format
to use try crop rectangle either from subdev frame size enumeration
or from subdev crop boundary.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/staging/media/tegra-video/vi.c | 106 +++++++++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c
index 6f320c1..03def26 100644
--- a/drivers/staging/media/tegra-video/vi.c
+++ b/drivers/staging/media/tegra-video/vi.c
@@ -427,6 +427,13 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan,
struct v4l2_subdev *subdev;
struct v4l2_subdev_format fmt;
struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_frame_size_enum fse = {
+ .which = V4L2_SUBDEV_FORMAT_TRY,
+ };
+ struct v4l2_subdev_selection sdsel = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .target = V4L2_SEL_TGT_CROP_BOUNDS,
+ };
int ret;
subdev = tegra_channel_get_remote_subdev(chan, true);
@@ -449,6 +456,24 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan,
fmt.which = V4L2_SUBDEV_FORMAT_TRY;
fmt.pad = 0;
v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code);
+
+ /*
+ * Attempt to obtain the format size from subdev.
+ * If not available, try to get crop boundary from subdev.
+ */
+ fse.code = fmtinfo->code;
+ ret = v4l2_subdev_call(subdev, pad, enum_frame_size, pad_cfg, &fse);
+ if (ret) {
+ ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel);
+ if (ret)
+ return -EINVAL;
+ pad_cfg->try_crop.width = sdsel.r.width;
+ pad_cfg->try_crop.height = sdsel.r.height;
+ } else {
+ pad_cfg->try_crop.width = fse.max_width;
+ pad_cfg->try_crop.height = fse.max_height;
+ }
+
ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt);
if (ret < 0)
return ret;
@@ -540,6 +565,85 @@ static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan)
return 0;
}
+static int tegra_channel_g_selection(struct file *file, void *priv,
+ struct v4l2_selection *sel)
+{
+ struct tegra_vi_channel *chan = video_drvdata(file);
+ struct v4l2_subdev *subdev;
+ struct v4l2_subdev_format fmt = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ struct v4l2_subdev_selection sdsel = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .target = sel->target,
+ };
+ int ret;
+
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return -ENOTTY;
+
+ if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ /*
+ * Try the get selection operation and fallback to get format if not
+ * implemented.
+ */
+ subdev = tegra_channel_get_remote_subdev(chan, true);
+ ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel);
+ if (!ret)
+ sel->r = sdsel.r;
+ if (ret != -ENOIOCTLCMD)
+ return ret;
+
+ ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt);
+ if (ret < 0)
+ return ret;
+
+ sel->r.left = 0;
+ sel->r.top = 0;
+ sel->r.width = fmt.format.width;
+ sel->r.height = fmt.format.height;
+
+ return 0;
+}
+
+static int tegra_channel_s_selection(struct file *file, void *fh,
+ struct v4l2_selection *sel)
+{
+ struct tegra_vi_channel *chan = video_drvdata(file);
+ struct v4l2_subdev *subdev;
+ int ret;
+ struct v4l2_subdev_selection sdsel = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .target = sel->target,
+ .flags = sel->flags,
+ .r = sel->r,
+ };
+
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return -ENOTTY;
+
+ if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ if (vb2_is_busy(&chan->queue))
+ return -EBUSY;
+
+ subdev = tegra_channel_get_remote_subdev(chan, true);
+ ret = v4l2_subdev_call(subdev, pad, set_selection, NULL, &sdsel);
+ if (!ret) {
+ sel->r = sdsel.r;
+ /*
+ * Subdev active format resolution may have changed during
+ * set selection operation. So, update channel format to
+ * the sub-device active format.
+ */
+ return tegra_channel_set_subdev_active_fmt(chan);
+ }
+
+ return ret;
+}
+
static int tegra_channel_enum_input(struct file *file, void *fh,
struct v4l2_input *inp)
{
@@ -597,6 +701,8 @@ static const struct v4l2_ioctl_ops tegra_channel_ioctl_ops = {
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+ .vidioc_g_selection = tegra_channel_g_selection,
+ .vidioc_s_selection = tegra_channel_s_selection,
};
/*
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 11/18] media: tegra-video: Add support for external sensor capture
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, frankc-DDmLM1+adcrQT0dZR+AlfA,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sakari.ailus-X3B1VOXEql0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
helen.koike-ZGY8ohtN/8qB+jHODAdFcQ
Cc: digetx-Re5JQEeQqe8AvxtiuMwx3w, sboyd-DgEjT+Ai2ygdnm+yROfE0A,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
This patch adds support to capture from the external sensor
based on device graph in the device tree.
Driver walks through the device graph to create media links
between the entities and registers and unregisters video devices
when the corresponding sub-devices are bound and unbound.
Channel formats are enumerated based on available formats from
the sensor and the corresponding matched formats from the Tegra
supported video formats list.
Each Tegra CSI instance can be configured as 4-lane or 2-lane
based on supported lane configuration from the sensor through
the device tree.
Currently this driver supports V4L2 video node centric only.
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/staging/media/tegra-video/Kconfig | 1 +
drivers/staging/media/tegra-video/csi.c | 128 +++++-
drivers/staging/media/tegra-video/csi.h | 2 +
drivers/staging/media/tegra-video/tegra210.c | 2 +-
drivers/staging/media/tegra-video/vi.c | 623 +++++++++++++++++++++++++--
drivers/staging/media/tegra-video/vi.h | 23 +-
6 files changed, 727 insertions(+), 52 deletions(-)
diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig
index 566da62..1f35da4 100644
--- a/drivers/staging/media/tegra-video/Kconfig
+++ b/drivers/staging/media/tegra-video/Kconfig
@@ -5,6 +5,7 @@ config VIDEO_TEGRA
depends on VIDEO_V4L2
select MEDIA_CONTROLLER
select VIDEOBUF2_DMA_CONTIG
+ select V4L2_FWNODE
help
Choose this option if you have an NVIDIA Tegra SoC.
diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c
index fb667df..14e9050 100644
--- a/drivers/staging/media/tegra-video/csi.c
+++ b/drivers/staging/media/tegra-video/csi.c
@@ -285,26 +285,102 @@ static const struct v4l2_subdev_ops tegra_csi_ops = {
.pad = &tegra_csi_pad_ops,
};
+static int tegra_csi_channel_alloc(struct tegra_csi *csi,
+ struct device_node *node,
+ unsigned int port_num, unsigned int lanes,
+ unsigned int num_pads)
+{
+ struct tegra_csi_channel *chan;
+
+ chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+ if (!chan)
+ return -ENOMEM;
+
+ list_add_tail(&chan->list, &csi->csi_chans);
+ chan->csi = csi;
+ chan->csi_port_num = port_num;
+ chan->numlanes = lanes;
+ chan->of_node = node;
+ chan->numpads = num_pads;
+ if (num_pads & 0x2) {
+ chan->pads[0].flags = MEDIA_PAD_FL_SINK;
+ chan->pads[1].flags = MEDIA_PAD_FL_SOURCE;
+ } else {
+ chan->pads[0].flags = MEDIA_PAD_FL_SOURCE;
+ }
+
+ return 0;
+}
+
static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi)
{
struct device_node *node = csi->dev->of_node;
unsigned int port_num;
- struct tegra_csi_channel *chan;
unsigned int tpg_channels = csi->soc->csi_max_channels;
+ int ret;
/* allocate CSI channel for each CSI x2 ports */
for (port_num = 0; port_num < tpg_channels; port_num++) {
- chan = kzalloc(sizeof(*chan), GFP_KERNEL);
- if (!chan)
- return -ENOMEM;
-
- list_add_tail(&chan->list, &csi->csi_chans);
- chan->csi = csi;
- chan->csi_port_num = port_num;
- chan->numlanes = 2;
- chan->of_node = node;
- chan->numpads = 1;
- chan->pads[0].flags = MEDIA_PAD_FL_SOURCE;
+ ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tegra_csi_channels_alloc(struct tegra_csi *csi)
+{
+ struct device_node *node = csi->dev->of_node;
+ struct device_node *channel;
+ struct device_node *port;
+ struct device_node *ep;
+ unsigned int lanes, port_num, num_pads;
+ int ret;
+
+ for_each_child_of_node(node, channel) {
+ if (!of_node_name_eq(channel, "channel"))
+ continue;
+
+ num_pads = 0;
+ port = of_get_child_by_name(channel, "port");
+ if (!port)
+ continue;
+
+ ret = of_property_read_u32(port, "reg", &port_num);
+ if (ret < 0)
+ continue;
+
+ if (port_num >= csi->soc->csi_max_channels) {
+ dev_err(csi->dev, "invalid port num %d\n", port_num);
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32(port, "bus-width", &lanes);
+ if (ret < 0) {
+ dev_err(csi->dev, "missing CSI bus-width\n");
+ return -EINVAL;
+ }
+
+ if (!lanes || ((lanes & (lanes - 1)) != 0) ||
+ lanes > CSI_MAX_LANES_PER_BRICK) {
+ dev_err(csi->dev, "invalid CSI bus-width\n");
+ return -EINVAL;
+ }
+
+ for_each_child_of_node(port, ep) {
+ if (!of_node_name_eq(ep, "endpoint"))
+ continue;
+
+ num_pads++;
+ }
+
+ if (num_pads == TEGRA_CSI_PADS_NUM) {
+ ret = tegra_csi_channel_alloc(csi, channel, port_num,
+ lanes, num_pads);
+ if (ret < 0)
+ return ret;
+ }
}
return 0;
@@ -350,6 +426,15 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan)
return ret;
}
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) {
+ ret = v4l2_async_register_subdev(subdev);
+ if (ret < 0) {
+ dev_err(csi->dev,
+ "failed to register subdev: %d\n", ret);
+ return ret;
+ }
+ }
+
return 0;
}
@@ -389,8 +474,12 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi)
list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) {
subdev = &chan->subdev;
- if (subdev->dev)
+ if (subdev->dev) {
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ v4l2_async_unregister_subdev(subdev);
media_entity_cleanup(&subdev->entity);
+ }
+
list_del(&chan->list);
kfree(chan);
}
@@ -427,13 +516,14 @@ static int tegra_csi_init(struct host1x_client *client)
INIT_LIST_HEAD(&csi->csi_chans);
- if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) {
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
ret = tegra_csi_tpg_channels_alloc(csi);
- if (ret < 0) {
- dev_err(csi->dev,
- "failed to allocate tpg channels: %d\n", ret);
- goto cleanup;
- }
+ else
+ ret = tegra_csi_channels_alloc(csi);
+ if (ret < 0) {
+ dev_err(csi->dev,
+ "failed to allocate channels: %d\n", ret);
+ goto cleanup;
}
ret = tegra_csi_channels_init(csi);
diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h
index 93bd2a0..b7b754a 100644
--- a/drivers/staging/media/tegra-video/csi.h
+++ b/drivers/staging/media/tegra-video/csi.h
@@ -7,6 +7,7 @@
#define __TEGRA_CSI_H__
#include <media/media-entity.h>
+#include <media/v4l2-async.h>
#include <media/v4l2-subdev.h>
/*
@@ -16,6 +17,7 @@
* CILB.
*/
#define CSI_PORTS_PER_BRICK 2
+#define CSI_MAX_LANES_PER_BRICK 4
/* each CSI channel can have one sink and one source pads */
#define TEGRA_CSI_PADS_NUM 2
diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c
index 3492a8a..4f5080a 100644
--- a/drivers/staging/media/tegra-video/tegra210.c
+++ b/drivers/staging/media/tegra-video/tegra210.c
@@ -230,7 +230,7 @@ static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan)
tegra_channel_capture_setup(chan);
/* recover CSI block */
- subdev = tegra_channel_get_remote_subdev(chan);
+ subdev = tegra_channel_get_remote_subdev(chan, false);
tegra_csi_error_recover(subdev);
}
diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c
index 52d751f..6f320c1 100644
--- a/drivers/staging/media/tegra-video/vi.c
+++ b/drivers/staging/media/tegra-video/vi.c
@@ -12,6 +12,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
@@ -52,6 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb)
return container_of(vb, struct tegra_channel_buffer, buf);
}
+static inline struct tegra_vi_graph_entity *
+to_tegra_vi_graph_entity(struct v4l2_async_subdev *asd)
+{
+ return container_of(asd, struct tegra_vi_graph_entity, asd);
+}
+
static int tegra_get_format_idx_by_code(struct tegra_vi *vi,
unsigned int code,
unsigned int offset)
@@ -146,7 +153,7 @@ static void tegra_channel_buffer_queue(struct vb2_buffer *vb)
}
struct v4l2_subdev *
-tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan)
+tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan, bool sensor)
{
struct media_pad *pad;
struct v4l2_subdev *subdev;
@@ -156,6 +163,24 @@ tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan)
entity = pad->entity;
subdev = media_entity_to_v4l2_subdev(entity);
+ if (sensor) {
+ while (1) {
+ if ((pad->index - 1) < 0)
+ break;
+
+ pad = &entity->pads[pad->index - 1];
+ if (!(pad->flags & MEDIA_PAD_FL_SINK))
+ break;
+
+ pad = media_entity_remote_pad(pad);
+ if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
+ break;
+
+ entity = pad->entity;
+ subdev = media_entity_to_v4l2_subdev(entity);
+ }
+ }
+
return subdev;
}
@@ -165,7 +190,15 @@ int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on)
int ret;
/* stream CSI */
- subdev = tegra_channel_get_remote_subdev(chan);
+ subdev = tegra_channel_get_remote_subdev(chan, !on);
+ ret = v4l2_subdev_call(subdev, video, s_stream, on);
+ if (on && ret < 0 && ret != -ENOIOCTLCMD)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return 0;
+
+ subdev = tegra_channel_get_remote_subdev(chan, on);
ret = v4l2_subdev_call(subdev, video, s_stream, on);
if (on && ret < 0 && ret != -ENOIOCTLCMD)
return ret;
@@ -252,7 +285,7 @@ static int tegra_channel_g_parm(struct file *file, void *fh,
struct tegra_vi_channel *chan = video_drvdata(file);
struct v4l2_subdev *subdev;
- subdev = tegra_channel_get_remote_subdev(chan);
+ subdev = tegra_channel_get_remote_subdev(chan, true);
return v4l2_g_parm_cap(&chan->video, subdev, a);
}
@@ -262,7 +295,7 @@ static int tegra_channel_s_parm(struct file *file, void *fh,
struct tegra_vi_channel *chan = video_drvdata(file);
struct v4l2_subdev *subdev;
- subdev = tegra_channel_get_remote_subdev(chan);
+ subdev = tegra_channel_get_remote_subdev(chan, true);
return v4l2_s_parm_cap(&chan->video, subdev, a);
}
@@ -284,7 +317,7 @@ static int tegra_channel_enum_framesizes(struct file *file, void *fh,
fse.code = fmtinfo->code;
- subdev = tegra_channel_get_remote_subdev(chan);
+ subdev = tegra_channel_get_remote_subdev(chan, true);
ret = v4l2_subdev_call(subdev, pad, enum_frame_size, NULL, &fse);
if (ret)
return ret;
@@ -316,7 +349,7 @@ static int tegra_channel_enum_frameintervals(struct file *file, void *fh,
fie.code = fmtinfo->code;
- subdev = tegra_channel_get_remote_subdev(chan);
+ subdev = tegra_channel_get_remote_subdev(chan, true);
ret = v4l2_subdev_call(subdev, pad, enum_frame_interval, NULL, &fie);
if (ret)
return ret;
@@ -335,6 +368,9 @@ static int tegra_channel_enum_format(struct file *file, void *fh,
unsigned int index = 0, i;
unsigned long *fmts_bitmap = chan->tpg_fmts_bitmap;
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ fmts_bitmap = chan->fmts_bitmap;
+
if (f->index >= bitmap_weight(fmts_bitmap, MAX_FORMAT_NUM))
return -EINVAL;
@@ -391,8 +427,9 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan,
struct v4l2_subdev *subdev;
struct v4l2_subdev_format fmt;
struct v4l2_subdev_pad_config *pad_cfg;
+ int ret;
- subdev = tegra_channel_get_remote_subdev(chan);
+ subdev = tegra_channel_get_remote_subdev(chan, true);
pad_cfg = v4l2_subdev_alloc_pad_config(subdev);
if (!pad_cfg)
return -ENOMEM;
@@ -412,7 +449,10 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan,
fmt.which = V4L2_SUBDEV_FORMAT_TRY;
fmt.pad = 0;
v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code);
- v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt);
+ ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt);
+ if (ret < 0)
+ return ret;
+
v4l2_fill_pix_format(pix, &fmt.format);
tegra_channel_fmt_align(chan, pix, fmtinfo->bpp);
@@ -452,8 +492,11 @@ static int tegra_channel_set_format(struct file *file, void *fh,
fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
fmt.pad = 0;
v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code);
- subdev = tegra_channel_get_remote_subdev(chan);
- v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt);
+ subdev = tegra_channel_get_remote_subdev(chan, true);
+ ret = v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt);
+ if (ret < 0)
+ return ret;
+
v4l2_fill_pix_format(pix, &fmt.format);
tegra_channel_fmt_align(chan, pix, fmtinfo->bpp);
@@ -463,15 +506,52 @@ static int tegra_channel_set_format(struct file *file, void *fh,
return 0;
}
+static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan)
+{
+ int ret, index;
+ const struct tegra_video_format *fmtinfo;
+ struct v4l2_subdev *subdev;
+ struct v4l2_subdev_format fmt = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+
+ /*
+ * Initialize channel format to the sub-device active format if there
+ * is corresponding match in the Tegra supported video formats.
+ */
+ subdev = tegra_channel_get_remote_subdev(chan, true);
+ ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt);
+ if (ret)
+ return ret;
+
+ index = tegra_get_format_idx_by_code(chan->vi, fmt.format.code, 0);
+ fmtinfo = &chan->vi->soc->video_formats[index];
+ if (!fmtinfo)
+ return -EINVAL;
+
+ chan->fmtinfo = fmtinfo;
+ v4l2_fill_pix_format(&chan->format, &fmt.format);
+ chan->format.pixelformat = chan->fmtinfo->fourcc;
+ chan->format.bytesperline = chan->format.width * chan->fmtinfo->bpp;
+ chan->format.sizeimage = chan->format.bytesperline *
+ chan->format.height;
+ tegra_channel_fmt_align(chan, &chan->format, chan->fmtinfo->bpp);
+
+ return 0;
+}
+
static int tegra_channel_enum_input(struct file *file, void *fh,
struct v4l2_input *inp)
{
- /* currently driver supports internal TPG only */
+ struct tegra_vi_channel *chan = video_drvdata(file);
+ struct v4l2_subdev *subdev;
+
if (inp->index)
return -EINVAL;
inp->type = V4L2_INPUT_TYPE_CAMERA;
- strscpy(inp->name, "Tegra TPG", sizeof(inp->name));
+ subdev = tegra_channel_get_remote_subdev(chan, true);
+ strscpy(inp->name, subdev->name, sizeof(inp->name));
return 0;
}
@@ -578,6 +658,19 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan)
v4l2_ctrl_handler_free(&chan->ctrl_handler);
return chan->ctrl_handler.error;
}
+#else
+ struct v4l2_subdev *subdev;
+
+ subdev = tegra_channel_get_remote_subdev(chan, true);
+ ret = v4l2_ctrl_add_handler(&chan->ctrl_handler, subdev->ctrl_handler,
+ NULL, true);
+ if (ret < 0) {
+ dev_err(chan->vi->dev,
+ "failed to add subdev %s ctrl handler: %d\n",
+ subdev->name, ret);
+ v4l2_ctrl_handler_free(&chan->ctrl_handler);
+ return ret;
+ }
#endif
/* setup the controls */
@@ -608,6 +701,57 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan)
bitmap_set(chan->tpg_fmts_bitmap, index, 1);
}
+static void vi_fmts_bitmap_init(struct tegra_vi_channel *chan)
+{
+ int index, ret, match_code = 0;
+ struct v4l2_subdev *subdev;
+ struct v4l2_subdev_mbus_code_enum code = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+
+ bitmap_zero(chan->fmts_bitmap, MAX_FORMAT_NUM);
+
+ /*
+ * Set the bitmap bits based on all the matched formats between the
+ * available media bus formats of sub-device and the pre-defined Tegra
+ * supported video formats.
+ */
+ subdev = tegra_channel_get_remote_subdev(chan, true);
+ while (1) {
+ ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
+ NULL, &code);
+ if (ret < 0)
+ break;
+
+ index = tegra_get_format_idx_by_code(chan->vi, code.code, 0);
+ while (index >= 0) {
+ bitmap_set(chan->fmts_bitmap, index, 1);
+ if (!match_code)
+ match_code = code.code;
+ /* look for other formats with same mbus code */
+ index = tegra_get_format_idx_by_code(chan->vi,
+ code.code,
+ index + 1);
+ }
+
+ code.index++;
+ }
+
+ /*
+ * Set the bitmap bit corresponding to default tegra video format if
+ * there are no matched formats.
+ */
+ if (!match_code) {
+ match_code = tegra_default_format.code;
+ index = tegra_get_format_idx_by_code(chan->vi, match_code, 0);
+ if (index >= 0)
+ bitmap_set(chan->fmts_bitmap, index, 1);
+ }
+
+ /* initialize channel format to the sub-device active format */
+ tegra_channel_set_subdev_active_fmt(chan);
+}
+
static void tegra_channel_cleanup(struct tegra_vi_channel *chan)
{
v4l2_ctrl_handler_free(&chan->ctrl_handler);
@@ -720,6 +864,9 @@ static int tegra_channel_init(struct tegra_vi_channel *chan)
goto free_v4l2_ctrl_hdl;
}
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ v4l2_async_notifier_init(&chan->notifier);
+
return 0;
free_v4l2_ctrl_hdl:
@@ -733,29 +880,85 @@ static int tegra_channel_init(struct tegra_vi_channel *chan)
return ret;
}
-static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi)
+static int tegra_vi_channel_alloc(struct tegra_vi *vi, unsigned int port_num,
+ struct device_node *node)
{
struct tegra_vi_channel *chan;
+
+ /*
+ * Do not use devm_kzalloc as memory is freed immediately
+ * when device instance is unbound but application might still
+ * be holding the device node open. Channel memory allocated
+ * with kzalloc is freed during video device release callback.
+ */
+ chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+ if (!chan)
+ return -ENOMEM;
+
+ chan->vi = vi;
+ chan->portno = port_num;
+ chan->of_node = node;
+ list_add_tail(&chan->list, &vi->vi_chans);
+
+ return 0;
+}
+
+static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi)
+{
unsigned int port_num;
unsigned int nchannels = vi->soc->vi_max_channels;
+ int ret;
for (port_num = 0; port_num < nchannels; port_num++) {
- /*
- * Do not use devm_kzalloc as memory is freed immediately
- * when device instance is unbound but application might still
- * be holding the device node open. Channel memory allocated
- * with kzalloc is freed during video device release callback.
- */
- chan = kzalloc(sizeof(*chan), GFP_KERNEL);
- if (!chan)
- return -ENOMEM;
+ ret = tegra_vi_channel_alloc(vi, port_num, vi->dev->of_node);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tegra_vi_channels_alloc(struct tegra_vi *vi)
+{
+ struct device_node *node = vi->dev->of_node;
+ struct device_node *ep = NULL;
+ struct device_node *ports;
+ struct device_node *port;
+ unsigned int port_num;
+ int ret;
+
+ ports = of_get_child_by_name(node, "ports");
+ if (!ports)
+ return -ENODEV;
+
+ for_each_child_of_node(ports, port) {
+ if (!of_node_name_eq(port, "port"))
+ continue;
+
+ ret = of_property_read_u32(port, "reg", &port_num);
+ if (ret < 0)
+ continue;
+
+ if (port_num > vi->soc->vi_max_channels) {
+ ret = -EINVAL;
+ dev_err(vi->dev, "invalid port num %d\n", port_num);
+ goto cleanup;
+ }
- chan->vi = vi;
- chan->portno = port_num;
- list_add_tail(&chan->list, &vi->vi_chans);
+ ep = of_get_next_child(port, NULL);
+ if (ep && of_node_name_eq(ep, "endpoint")) {
+ of_node_put(ep);
+ ret = tegra_vi_channel_alloc(vi, port_num, port);
+ if (ret < 0)
+ goto cleanup;
+ }
}
return 0;
+
+cleanup:
+ of_node_put(ports);
+ return ret;
}
static int tegra_vi_channels_init(struct tegra_vi *vi)
@@ -909,6 +1112,352 @@ static int __maybe_unused vi_runtime_suspend(struct device *dev)
return 0;
}
+/*
+ * Graph Management
+ */
+static struct tegra_vi_graph_entity *
+tegra_vi_graph_find_entity(struct tegra_vi_channel *chan,
+ const struct fwnode_handle *fwnode)
+{
+ struct tegra_vi_graph_entity *entity;
+ struct v4l2_async_subdev *asd;
+
+ list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) {
+ entity = to_tegra_vi_graph_entity(asd);
+ if (entity->asd.match.fwnode == fwnode)
+ return entity;
+ }
+
+ return NULL;
+}
+
+static int tegra_vi_graph_build(struct tegra_vi_channel *chan,
+ struct tegra_vi_graph_entity *entity)
+{
+ struct tegra_vi *vi = chan->vi;
+ struct tegra_vi_graph_entity *ent;
+ struct fwnode_handle *ep = NULL;
+ struct v4l2_fwnode_link link;
+ struct media_entity *local = entity->entity;
+ struct media_entity *remote;
+ struct media_pad *local_pad;
+ struct media_pad *remote_pad;
+ u32 link_flags = MEDIA_LNK_FL_ENABLED;
+ int ret = 0;
+
+ dev_dbg(vi->dev, "creating links for entity %s\n", local->name);
+
+ while (1) {
+ ep = fwnode_graph_get_next_endpoint(entity->asd.match.fwnode,
+ ep);
+ if (!ep)
+ break;
+
+ ret = v4l2_fwnode_parse_link(ep, &link);
+ if (ret < 0) {
+ dev_err(vi->dev, "failed to parse link for %pOF: %d\n",
+ to_of_node(ep), ret);
+ continue;
+ }
+
+ if (link.local_id >= local->num_pads) {
+ dev_err(vi->dev, "invalid endpoint id %u for %pOF\n",
+ link.local_id, to_of_node(link.local_node));
+ v4l2_fwnode_put_link(&link);
+ ret = -EINVAL;
+ break;
+ }
+
+ local_pad = &local->pads[link.local_id];
+ /*
+ * Remote node is vi node. So use channel video entity and pad
+ * as remote/sink.
+ */
+ if (link.remote_node == of_fwnode_handle(vi->dev->of_node)) {
+ remote = &chan->video.entity;
+ remote_pad = &chan->pad;
+ goto create_link;
+ }
+
+ /*
+ * Skip sink ports, they will be processed from the other end
+ * of the link.
+ */
+ if (local_pad->flags & MEDIA_PAD_FL_SINK) {
+ dev_dbg(vi->dev, "skipping sink port %pOF:%u\n",
+ to_of_node(link.local_node), link.local_id);
+ v4l2_fwnode_put_link(&link);
+ continue;
+ }
+
+ /* find the remote entity from notifier list */
+ ent = tegra_vi_graph_find_entity(chan, link.remote_node);
+ if (!ent) {
+ dev_err(vi->dev, "no entity found for %pOF\n",
+ to_of_node(link.remote_node));
+ v4l2_fwnode_put_link(&link);
+ ret = -ENODEV;
+ break;
+ }
+
+ remote = ent->entity;
+ if (link.remote_id >= remote->num_pads) {
+ dev_err(vi->dev, "invalid endpoint id %u for %pOF\n",
+ link.remote_id, to_of_node(link.remote_node));
+ v4l2_fwnode_put_link(&link);
+ ret = -EINVAL;
+ break;
+ }
+
+ remote_pad = &remote->pads[link.remote_id];
+
+create_link:
+ dev_dbg(vi->dev, "creating %s:%u -> %s:%u link\n",
+ local->name, local_pad->index,
+ remote->name, remote_pad->index);
+
+ ret = media_create_pad_link(local, local_pad->index,
+ remote, remote_pad->index,
+ link_flags);
+ v4l2_fwnode_put_link(&link);
+ if (ret < 0) {
+ dev_err(vi->dev,
+ "failed to create %s:%u -> %s:%u link: %d\n",
+ local->name, local_pad->index,
+ remote->name, remote_pad->index, ret);
+ break;
+ }
+ }
+
+ fwnode_handle_put(ep);
+ return ret;
+}
+
+static int tegra_vi_graph_notify_complete(struct v4l2_async_notifier *notifier)
+{
+ struct tegra_vi_graph_entity *entity;
+ struct v4l2_async_subdev *asd;
+ struct v4l2_subdev *subdev;
+ struct tegra_vi_channel *chan;
+ struct tegra_vi *vi;
+ int ret;
+
+ chan = container_of(notifier, struct tegra_vi_channel, notifier);
+ vi = chan->vi;
+
+ dev_dbg(vi->dev, "notify complete, all subdevs registered\n");
+
+ ret = video_register_device(&chan->video, VFL_TYPE_VIDEO, -1);
+ if (ret < 0) {
+ dev_err(vi->dev,
+ "failed to register video device: %d\n", ret);
+ goto unregister_video;
+ }
+
+ /* create links between the entities */
+ list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) {
+ entity = to_tegra_vi_graph_entity(asd);
+ ret = tegra_vi_graph_build(chan, entity);
+ if (ret < 0)
+ goto unregister_video;
+ }
+
+ ret = tegra_channel_setup_ctrl_handler(chan);
+ if (ret < 0) {
+ dev_err(vi->dev,
+ "failed to setup channel controls: %d\n", ret);
+ goto unregister_video;
+ }
+
+ vi_fmts_bitmap_init(chan);
+ subdev = tegra_channel_get_remote_subdev(chan, false);
+ v4l2_set_subdev_hostdata(subdev, chan);
+
+ return 0;
+
+unregister_video:
+ video_unregister_device(&chan->video);
+ return ret;
+}
+
+static int tegra_vi_graph_notify_bound(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *subdev,
+ struct v4l2_async_subdev *asd)
+{
+ struct tegra_vi_graph_entity *entity;
+ struct tegra_vi *vi;
+ struct tegra_vi_channel *chan;
+
+ chan = container_of(notifier, struct tegra_vi_channel, notifier);
+ vi = chan->vi;
+
+ /*
+ * Locate the entity corresponding to the bound subdev and store the
+ * subdev pointer.
+ */
+ entity = tegra_vi_graph_find_entity(chan, subdev->fwnode);
+ if (!entity) {
+ dev_err(vi->dev, "no entity for subdev %s\n", subdev->name);
+ return -EINVAL;
+ }
+
+ if (entity->subdev) {
+ dev_err(vi->dev, "duplicate subdev for node %pOF\n",
+ to_of_node(entity->asd.match.fwnode));
+ return -EINVAL;
+ }
+
+ dev_dbg(vi->dev, "subdev %s bound\n", subdev->name);
+ entity->entity = &subdev->entity;
+ entity->subdev = subdev;
+
+ return 0;
+}
+
+static void tegra_vi_graph_notify_unbind(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *subdev,
+ struct v4l2_async_subdev *asd)
+{
+ struct tegra_vi_graph_entity *entity;
+ struct tegra_vi *vi;
+ struct tegra_vi_channel *chan;
+
+ chan = container_of(notifier, struct tegra_vi_channel, notifier);
+ vi = chan->vi;
+
+ video_unregister_device(&chan->video);
+
+ media_entity_remove_links(&chan->video.entity);
+ entity = tegra_vi_graph_find_entity(chan, subdev->fwnode);
+ if (entity) {
+ if (entity->entity)
+ media_entity_remove_links(entity->entity);
+ entity->entity = NULL;
+ entity->subdev = NULL;
+ }
+
+ dev_dbg(vi->dev, "subdev %s unbind\n", subdev->name);
+}
+
+static const struct v4l2_async_notifier_operations tegra_vi_async_ops = {
+ .bound = tegra_vi_graph_notify_bound,
+ .complete = tegra_vi_graph_notify_complete,
+ .unbind = tegra_vi_graph_notify_unbind,
+};
+
+static int tegra_vi_graph_parse_one(struct tegra_vi_channel *chan,
+ struct fwnode_handle *fwnode)
+{
+ struct tegra_vi *vi = chan->vi;
+ struct fwnode_handle *ep = NULL;
+ struct fwnode_handle *remote = NULL;
+ struct v4l2_async_subdev *asd;
+ struct device_node *node = NULL;
+ int ret;
+
+ dev_dbg(vi->dev, "parsing node %pOF\n", to_of_node(fwnode));
+
+ /* parse all the remote entities and put them into the list */
+ for_each_endpoint_of_node(to_of_node(fwnode), node) {
+ ep = of_fwnode_handle(node);
+ remote = fwnode_graph_get_remote_port_parent(ep);
+ if (!remote) {
+ dev_err(vi->dev,
+ "remote device at %pOF not found\n", node);
+ ret = -EINVAL;
+ goto cleanup;
+ }
+
+ /* skip entities that are already processed */
+ if (remote == dev_fwnode(vi->dev) ||
+ tegra_vi_graph_find_entity(chan, remote)) {
+ fwnode_handle_put(remote);
+ continue;
+ }
+
+ asd = v4l2_async_notifier_add_fwnode_subdev(&chan->notifier,
+ remote, sizeof(struct tegra_vi_graph_entity));
+ if (IS_ERR(asd)) {
+ ret = PTR_ERR(asd);
+ dev_err(vi->dev,
+ "failed to add subdev to notifier: %d\n", ret);
+ fwnode_handle_put(remote);
+ goto cleanup;
+ }
+
+ ret = tegra_vi_graph_parse_one(chan, remote);
+ if (ret < 0) {
+ fwnode_handle_put(remote);
+ goto cleanup;
+ }
+
+ fwnode_handle_put(remote);
+ }
+
+ return 0;
+
+cleanup:
+ dev_err(vi->dev, "failed parsing the graph: %d\n", ret);
+ v4l2_async_notifier_cleanup(&chan->notifier);
+ of_node_put(node);
+ return ret;
+}
+
+static int tegra_vi_graph_init(struct tegra_vi *vi)
+{
+ struct tegra_video_device *vid = dev_get_drvdata(vi->client.host);
+ struct tegra_vi_channel *chan;
+ struct fwnode_handle *fwnode = dev_fwnode(vi->dev);
+ int ret;
+ struct fwnode_handle *remote = NULL;
+
+ /*
+ * Walk the links to parse the full graph. Each channel will have
+ * one endpoint of the composite node. Start by parsing the
+ * composite node and parse the remote entities in turn.
+ * Each channel will register v4l2 async notifier to make the graph
+ * independent between the channels so we can the current channel
+ * in case of something wrong during graph parsing and continue with
+ * next channels.
+ */
+ list_for_each_entry(chan, &vi->vi_chans, list) {
+ remote = fwnode_graph_get_remote_node(fwnode, chan->portno, 0);
+ if (!remote)
+ continue;
+
+ ret = tegra_vi_graph_parse_one(chan, remote);
+ fwnode_handle_put(remote);
+ if (ret < 0 || list_empty(&chan->notifier.asd_list))
+ continue;
+
+ chan->notifier.ops = &tegra_vi_async_ops;
+ ret = v4l2_async_notifier_register(&vid->v4l2_dev,
+ &chan->notifier);
+ if (ret < 0) {
+ dev_err(vi->dev,
+ "failed to register channel %d notifier: %d\n",
+ chan->portno, ret);
+ v4l2_async_notifier_cleanup(&chan->notifier);
+ }
+ }
+
+ return 0;
+}
+
+void tegra_vi_graph_cleanup(struct tegra_vi *vi)
+{
+ struct tegra_vi_channel *chan;
+
+ list_for_each_entry(chan, &vi->vi_chans, list) {
+ video_unregister_device(&chan->video);
+ mutex_lock(&chan->video_lock);
+ vb2_queue_release(&chan->queue);
+ mutex_unlock(&chan->video_lock);
+ v4l2_async_notifier_unregister(&chan->notifier);
+ v4l2_async_notifier_cleanup(&chan->notifier);
+ }
+}
+
static int tegra_vi_init(struct host1x_client *client)
{
struct tegra_video_device *vid = dev_get_drvdata(client->host);
@@ -922,13 +1471,14 @@ static int tegra_vi_init(struct host1x_client *client)
INIT_LIST_HEAD(&vi->vi_chans);
- if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) {
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
ret = tegra_vi_tpg_channels_alloc(vi);
- if (ret < 0) {
- dev_err(vi->dev,
- "failed to allocate tpg channels: %d\n", ret);
- goto free_chans;
- }
+ else
+ ret = tegra_vi_channels_alloc(vi);
+ if (ret < 0) {
+ dev_err(vi->dev,
+ "failed to allocate vi channels: %d\n", ret);
+ goto free_chans;
}
ret = tegra_vi_channels_init(vi);
@@ -937,6 +1487,12 @@ static int tegra_vi_init(struct host1x_client *client)
vid->vi = vi;
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) {
+ ret = tegra_vi_graph_init(vi);
+ if (ret < 0)
+ goto free_chans;
+ }
+
return 0;
free_chans:
@@ -950,6 +1506,8 @@ static int tegra_vi_init(struct host1x_client *client)
static int tegra_vi_exit(struct host1x_client *client)
{
+ struct tegra_vi *vi = host1x_client_to_vi(client);
+
/*
* Do not cleanup the channels here as application might still be
* holding video device nodes. Channels cleanup will happen during
@@ -957,6 +1515,9 @@ static int tegra_vi_exit(struct host1x_client *client)
* device nodes are released.
*/
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ tegra_vi_graph_cleanup(vi);
+
return 0;
}
diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h
index 6272c9a..98f6d575 100644
--- a/drivers/staging/media/tegra-video/vi.h
+++ b/drivers/staging/media/tegra-video/vi.h
@@ -14,6 +14,7 @@
#include <linux/wait.h>
#include <media/media-entity.h>
+#include <media/v4l2-async.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-dev.h>
@@ -93,6 +94,19 @@ struct tegra_vi {
};
/**
+ * struct tegra_vi_graph_entity - Entity in the video graph
+ *
+ * @asd: subdev asynchronous registration information
+ * @entity: media entity from the corresponding V4L2 subdev
+ * @subdev: V4L2 subdev
+ */
+struct tegra_vi_graph_entity {
+ struct v4l2_async_subdev asd;
+ struct media_entity *entity;
+ struct v4l2_subdev *subdev;
+};
+
+/**
* struct tegra_vi_channel - Tegra video channel
*
* @list: list head for this entry
@@ -138,10 +152,13 @@ struct tegra_vi {
* @done_lock: protects the capture done queue list
*
* @portno: VI channel port number
+ * @of_node: device node of VI channel
*
* @ctrl_handler: V4L2 control handler of this video channel
+ * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats
* @tpg_fmts_bitmap: a bitmap for supported TPG formats
* @pg_mode: test pattern generator mode (disabled/direct/patch)
+ * @notifier: V4L2 asynchronous subdevs notifier
*/
struct tegra_vi_channel {
struct list_head list;
@@ -174,10 +191,14 @@ struct tegra_vi_channel {
spinlock_t done_lock;
unsigned char portno;
+ struct device_node *of_node;
struct v4l2_ctrl_handler ctrl_handler;
+ DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM);
DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM);
enum tegra_vi_pg_mode pg_mode;
+
+ struct v4l2_async_notifier notifier;
};
/**
@@ -249,7 +270,7 @@ extern const struct tegra_vi_soc tegra210_vi_soc;
#endif
struct v4l2_subdev *
-tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan);
+tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan, bool sensor);
int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on);
void tegra_channel_release_buffers(struct tegra_vi_channel *chan,
enum vb2_buffer_state state);
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 10/18] dt-bindings: tegra: Document VI and CSI port nodes
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, frankc-DDmLM1+adcrQT0dZR+AlfA,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sakari.ailus-X3B1VOXEql0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
helen.koike-ZGY8ohtN/8qB+jHODAdFcQ
Cc: digetx-Re5JQEeQqe8AvxtiuMwx3w, sboyd-DgEjT+Ai2ygdnm+yROfE0A,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
This patch documents Tegra VI and CSI port and endpoint nodes along
with the other required properties.
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
.../display/tegra/nvidia,tegra20-host1x.txt | 87 ++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
index 4731921..f70a838 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -65,6 +65,48 @@ of the following host1x client modules:
- power-domains: Must include sor powergate node as csicil is in
SOR partition.
+ Optional properties for csi node:
+
+ - channel nodes: Max upto 6 channels/streams are supported with each CSI
+ brick can as either x4 or x2 based on hw connectivity to sensor.
+
+ Required properties:
+ - reg: channel/stream index
+ - nvidia,mipi-calibrate: Should contain a phandle and a specifier
+ specifying which pads are used by this CSI port and need to be
+ calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
+
+ - port: CSI port node and its endpoint nodes as per device graph
+ bindings defined in Documentation/devicetree/bindings/graph.txt.
+ Required properties:
+ - reg: csi port index based on hw csi lanes connectivity to the
+ sensor.
+ - bus-width: number of lanes used by this port. Supported lanes
+ are 1/2/4.
+ - endpoint@0: sink node
+ Required properties:
+ - reg: endpoint id. This is used to retrieve pad for creating
+ media link
+ - remote-endpoint: phandle to sensor endpoint
+ - endpoint@1: source node
+ - reg: endpoint id. This is used to retrieve pad for creating
+ media link
+ - remote-endpoint: phandle to vi port endpoint
+
+ Optional properties for vi node:
+ - ports: Video port nodes and endpoint nodes as per device graph bindings
+ defined in Documentation/devicetree/bindings/graph.txt
+ Max 6 ports are supported and each port should have one endpoint node.
+
+ Required properties:
+ - port: VI port node and its sink endpoint node
+ Required properties:
+ - reg: should match port index
+ - endpoint@0: sink node
+ Required properties:
+ - reg: endpoint id must be 0
+ - remote-endpoint: phandle to CSI endpoint node.
+
- epp: encoder pre-processor
Required properties:
@@ -340,6 +382,22 @@ Example:
ranges = <0x0 0x0 0x54080000 0x2000>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imx219_vi_in0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&imx219_csi_out0>;
+ };
+ };
+ };
+
csi@838 {
compatible = "nvidia,tegra210-csi";
reg = <0x838 0x1300>;
@@ -362,6 +420,35 @@ Example:
<&tegra_car TEGRA210_CLK_CSI_TPG>;
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
power-domains = <&pd_sor>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ nvidia,mipi-calibrate = <&mipi 0x001>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bus-width = <2>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imx219_csi_in0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&imx219_out0>;
+ };
+
+ imx219_csi_out0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&imx219_vi_in0>;
+ };
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 09/18] media: tegra-video: Update format lookup to offset based
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, frankc, hverkuil,
sakari.ailus, robh+dt, helen.koike
Cc: digetx, sboyd, gregkh, linux-media, devicetree, linux-tegra,
linux-kernel, linux-i2c
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com>
Tegra VI supported video formats are more for non TPG and there
can be multiple pixel formats for the same media bus format.
This patch updates the helper function for format lookup based on
mbus code from pre-defined Tegra supported format list to look from
the specified list index offset.
Offset based look up is used with sensor device graph (non TPG)
where format enumeration can list all supported formats for the
specific sensor mbus codes.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/staging/media/tegra-video/vi.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c
index 0197f4e..52d751f 100644
--- a/drivers/staging/media/tegra-video/vi.c
+++ b/drivers/staging/media/tegra-video/vi.c
@@ -53,11 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb)
}
static int tegra_get_format_idx_by_code(struct tegra_vi *vi,
- unsigned int code)
+ unsigned int code,
+ unsigned int offset)
{
unsigned int i;
- for (i = 0; i < vi->soc->nformats; ++i) {
+ for (i = offset; i < vi->soc->nformats; ++i) {
if (vi->soc->video_formats[i].code == code)
return i;
}
@@ -598,11 +599,12 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan)
bitmap_zero(chan->tpg_fmts_bitmap, MAX_FORMAT_NUM);
index = tegra_get_format_idx_by_code(chan->vi,
- MEDIA_BUS_FMT_SRGGB10_1X10);
+ MEDIA_BUS_FMT_SRGGB10_1X10, 0);
bitmap_set(chan->tpg_fmts_bitmap, index, 1);
index = tegra_get_format_idx_by_code(chan->vi,
- MEDIA_BUS_FMT_RGB888_1X32_PADHI);
+ MEDIA_BUS_FMT_RGB888_1X32_PADHI,
+ 0);
bitmap_set(chan->tpg_fmts_bitmap, index, 1);
}
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 08/18] media: tegra-video: Enable TPG based on kernel config
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, frankc, hverkuil,
sakari.ailus, robh+dt, helen.koike
Cc: digetx, sboyd, gregkh, linux-media, devicetree, linux-tegra,
linux-kernel, linux-i2c
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com>
Tegra internal TPG mode is only for Tegra vi and csi testing
without a real sensor and driver should default support real
sensor.
So, This patch adds CONFIG_VIDEO_TEGRA_TPG and enables Tegra
internal TPG mode only when this config is selected.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/staging/media/tegra-video/Kconfig | 6 +++++
drivers/staging/media/tegra-video/csi.c | 38 +++++++++++++++++++++++-----
drivers/staging/media/tegra-video/tegra210.c | 6 +++++
drivers/staging/media/tegra-video/vi.c | 13 +++++++---
drivers/staging/media/tegra-video/video.c | 23 +++++++++--------
5 files changed, 65 insertions(+), 21 deletions(-)
diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig
index f6c61ec..566da62 100644
--- a/drivers/staging/media/tegra-video/Kconfig
+++ b/drivers/staging/media/tegra-video/Kconfig
@@ -10,3 +10,9 @@ config VIDEO_TEGRA
To compile this driver as a module, choose M here: the module
will be called tegra-video.
+
+config VIDEO_TEGRA_TPG
+ bool "NVIDIA Tegra VI driver TPG mode"
+ depends on VIDEO_TEGRA
+ help
+ Say yes here to enable Tegra internal TPG mode
diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c
index 40ea195..fb667df 100644
--- a/drivers/staging/media/tegra-video/csi.c
+++ b/drivers/staging/media/tegra-video/csi.c
@@ -62,6 +62,9 @@ static int csi_enum_bus_code(struct v4l2_subdev *subdev,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return -ENOIOCTLCMD;
+
if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts))
return -EINVAL;
@@ -76,6 +79,9 @@ static int csi_get_format(struct v4l2_subdev *subdev,
{
struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return -ENOIOCTLCMD;
+
fmt->format = csi_chan->format;
return 0;
@@ -121,6 +127,9 @@ static int csi_enum_framesizes(struct v4l2_subdev *subdev,
{
unsigned int i;
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return -ENOIOCTLCMD;
+
if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes))
return -EINVAL;
@@ -148,6 +157,9 @@ static int csi_enum_frameintervals(struct v4l2_subdev *subdev,
const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table;
int index;
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return -ENOIOCTLCMD;
+
/* one framerate per format and resolution */
if (fie->index > 0)
return -EINVAL;
@@ -172,6 +184,9 @@ static int csi_set_format(struct v4l2_subdev *subdev,
const struct v4l2_frmsize_discrete *sizes;
unsigned int i;
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return -ENOIOCTLCMD;
+
sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes,
ARRAY_SIZE(tegra_csi_tpg_sizes),
width, height,
@@ -208,6 +223,9 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev,
{
struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
+ if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ return -ENOIOCTLCMD;
+
vfi->interval.numerator = 1;
vfi->interval.denominator = csi_chan->framerate;
@@ -311,8 +329,12 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan)
subdev = &chan->subdev;
v4l2_subdev_init(subdev, &tegra_csi_ops);
subdev->dev = csi->dev;
- snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg",
- chan->csi_port_num);
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg",
+ chan->csi_port_num);
+ else
+ snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s",
+ kbasename(chan->of_node->full_name));
v4l2_set_subdevdata(subdev, chan);
subdev->fwnode = of_fwnode_handle(chan->of_node);
@@ -405,11 +427,13 @@ static int tegra_csi_init(struct host1x_client *client)
INIT_LIST_HEAD(&csi->csi_chans);
- ret = tegra_csi_tpg_channels_alloc(csi);
- if (ret < 0) {
- dev_err(csi->dev,
- "failed to allocate tpg channels: %d\n", ret);
- goto cleanup;
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) {
+ ret = tegra_csi_tpg_channels_alloc(csi);
+ if (ret < 0) {
+ dev_err(csi->dev,
+ "failed to allocate tpg channels: %d\n", ret);
+ goto cleanup;
+ }
}
ret = tegra_csi_channels_init(csi);
diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c
index 3baa4e3..3492a8a 100644
--- a/drivers/staging/media/tegra-video/tegra210.c
+++ b/drivers/staging/media/tegra-video/tegra210.c
@@ -631,7 +631,11 @@ const struct tegra_vi_soc tegra210_vi_soc = {
.ops = &tegra210_vi_ops,
.hw_revision = 3,
.vi_max_channels = 6,
+#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)
.vi_max_clk_hz = 499200000,
+#else
+ .vi_max_clk_hz = 998400000,
+#endif
};
/* Tegra210 CSI PHY registers accessors */
@@ -957,7 +961,9 @@ static const char * const tegra210_csi_cil_clks[] = {
"cilab",
"cilcd",
"cile",
+#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)
"csi_tpg",
+#endif
};
/* Tegra210 CSI operations */
diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c
index d621ebc..0197f4e 100644
--- a/drivers/staging/media/tegra-video/vi.c
+++ b/drivers/staging/media/tegra-video/vi.c
@@ -565,6 +565,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan)
{
int ret;
+#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)
/* add test pattern control handler to v4l2 device */
v4l2_ctrl_new_std_menu_items(&chan->ctrl_handler, &vi_ctrl_ops,
V4L2_CID_TEST_PATTERN,
@@ -576,6 +577,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan)
v4l2_ctrl_handler_free(&chan->ctrl_handler);
return chan->ctrl_handler.error;
}
+#endif
/* setup the controls */
ret = v4l2_ctrl_handler_setup(&chan->ctrl_handler);
@@ -918,10 +920,13 @@ static int tegra_vi_init(struct host1x_client *client)
INIT_LIST_HEAD(&vi->vi_chans);
- ret = tegra_vi_tpg_channels_alloc(vi);
- if (ret < 0) {
- dev_err(vi->dev, "failed to allocate tpg channels: %d\n", ret);
- goto free_chans;
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) {
+ ret = tegra_vi_tpg_channels_alloc(vi);
+ if (ret < 0) {
+ dev_err(vi->dev,
+ "failed to allocate tpg channels: %d\n", ret);
+ goto free_chans;
+ }
}
ret = tegra_vi_channels_init(vi);
diff --git a/drivers/staging/media/tegra-video/video.c b/drivers/staging/media/tegra-video/video.c
index 30816aa..e50bd70 100644
--- a/drivers/staging/media/tegra-video/video.c
+++ b/drivers/staging/media/tegra-video/video.c
@@ -60,15 +60,17 @@ static int host1x_video_probe(struct host1x_device *dev)
if (ret < 0)
goto unregister_v4l2;
- /*
- * Both vi and csi channels are available now.
- * Register v4l2 nodes and create media links for TPG.
- */
- ret = tegra_v4l2_nodes_setup_tpg(vid);
- if (ret < 0) {
- dev_err(&dev->dev,
- "failed to setup tpg graph: %d\n", ret);
- goto device_exit;
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) {
+ /*
+ * Both vi and csi channels are available now.
+ * Register v4l2 nodes and create media links for TPG.
+ */
+ ret = tegra_v4l2_nodes_setup_tpg(vid);
+ if (ret < 0) {
+ dev_err(&dev->dev,
+ "failed to setup tpg graph: %d\n", ret);
+ goto device_exit;
+ }
}
return 0;
@@ -91,7 +93,8 @@ static int host1x_video_remove(struct host1x_device *dev)
{
struct tegra_video_device *vid = dev_get_drvdata(&dev->dev);
- tegra_v4l2_nodes_cleanup_tpg(vid);
+ if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
+ tegra_v4l2_nodes_cleanup_tpg(vid);
host1x_device_exit(dev);
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 07/18] media: tegra-video: Fix channel format alignment
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, frankc-DDmLM1+adcrQT0dZR+AlfA,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sakari.ailus-X3B1VOXEql0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
helen.koike-ZGY8ohtN/8qB+jHODAdFcQ
Cc: digetx-Re5JQEeQqe8AvxtiuMwx3w, sboyd-DgEjT+Ai2ygdnm+yROfE0A,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Pixel format width is mistakenly aligned to surface align bytes
and altering width to aligned value may force sensor mode change
other than the requested one and also cause mismatch in width
programmed between sensor and vi which can lead to capture errors.
This patch removes width alignment and clamps width as per Tegra
minimum and maximum limits.
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/staging/media/tegra-video/vi.c | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c
index 1b5e660..d621ebc 100644
--- a/drivers/staging/media/tegra-video/vi.c
+++ b/drivers/staging/media/tegra-video/vi.c
@@ -359,25 +359,15 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan,
struct v4l2_pix_format *pix,
unsigned int bpp)
{
- unsigned int align;
- unsigned int min_width;
- unsigned int max_width;
- unsigned int width;
unsigned int min_bpl;
unsigned int max_bpl;
unsigned int bpl;
/*
- * The transfer alignment requirements are expressed in bytes. Compute
- * minimum and maximum values, clamp the requested width and convert
- * it back to pixels. Use bytesperline to adjust the width.
+ * The transfer alignment requirements are expressed in bytes.
+ * Clamp the requested width and height to the limits.
*/
- align = lcm(SURFACE_ALIGN_BYTES, bpp);
- min_width = roundup(TEGRA_MIN_WIDTH, align);
- max_width = rounddown(TEGRA_MAX_WIDTH, align);
- width = roundup(pix->width * bpp, align);
-
- pix->width = clamp(width, min_width, max_width) / bpp;
+ pix->width = clamp(pix->width, TEGRA_MIN_WIDTH, TEGRA_MAX_WIDTH);
pix->height = clamp(pix->height, TEGRA_MIN_HEIGHT, TEGRA_MAX_HEIGHT);
/* Clamp the requested bytes per line value. If the maximum bytes per
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 06/18] i2c: tegra: Avoid tegra_i2c_init_dma() for Tegra210 vi i2c
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, frankc-DDmLM1+adcrQT0dZR+AlfA,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sakari.ailus-X3B1VOXEql0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
helen.koike-ZGY8ohtN/8qB+jHODAdFcQ
Cc: digetx-Re5JQEeQqe8AvxtiuMwx3w, sboyd-DgEjT+Ai2ygdnm+yROfE0A,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
VI I2C is on host1x bus so APB DMA can't be used for Tegra210 VI
I2C and there are no tx and rx dma channels for VI I2C.
So, avoid attempt of requesting DMA channels.
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/i2c/busses/i2c-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 650240d..ed99dfe 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -421,7 +421,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
dma_addr_t dma_phys;
int err;
- if (!i2c_dev->hw->has_apb_dma)
+ if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi)
return 0;
if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 05/18] i2c: tegra: Fix runtime resume to re-init VI I2C
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, frankc-DDmLM1+adcrQT0dZR+AlfA,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sakari.ailus-X3B1VOXEql0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
helen.koike-ZGY8ohtN/8qB+jHODAdFcQ
Cc: digetx-Re5JQEeQqe8AvxtiuMwx3w, sboyd-DgEjT+Ai2ygdnm+yROfE0A,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
VI I2C is on host1x bus and is part of VE power domain.
During suspend/resume VE power domain goes through power off/on.
So, controller reset followed by i2c re-initialization is required
after the domain power up.
This patch fixes it.
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/i2c/busses/i2c-tegra.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index dba38a5..650240d 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -293,6 +293,8 @@ struct tegra_i2c_dev {
bool is_curr_atomic_xfer;
};
+static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit);
+
static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
unsigned long reg)
{
@@ -679,8 +681,22 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
goto disable_slow_clk;
}
+ /*
+ * VI I2C device is attached to VE power domain which goes through
+ * power ON/OFF during PM runtime resume/suspend. So, controller
+ * should go through reset and need to re-initialize after power
+ * domain ON.
+ */
+ if (i2c_dev->is_vi) {
+ ret = tegra_i2c_init(i2c_dev, true);
+ if (ret)
+ goto disable_div_clk;
+ }
+
return 0;
+disable_div_clk:
+ clk_disable(i2c_dev->div_clk);
disable_slow_clk:
if (i2c_dev->slow_clk)
clk_disable(i2c_dev->slow_clk);
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 04/18] i2c: tegra: Fix the error path in tegra_i2c_runtime_resume
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, frankc, hverkuil,
sakari.ailus, robh+dt, helen.koike
Cc: digetx, sboyd, gregkh, linux-media, devicetree, linux-tegra,
linux-kernel, linux-i2c
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com>
tegra_i2c_runtime_resume does not disable prior enabled clocks
properly.
This patch fixes it.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/i2c/busses/i2c-tegra.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 3be1018..dba38a5 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -668,7 +668,7 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
ret = clk_enable(i2c_dev->slow_clk);
if (ret < 0) {
dev_err(dev, "failed to enable slow clock: %d\n", ret);
- return ret;
+ goto disable_fast_clk;
}
}
@@ -676,11 +676,18 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
if (ret < 0) {
dev_err(i2c_dev->dev,
"Enabling div clk failed, err %d\n", ret);
- clk_disable(i2c_dev->fast_clk);
- return ret;
+ goto disable_slow_clk;
}
return 0;
+
+disable_slow_clk:
+ if (i2c_dev->slow_clk)
+ clk_disable(i2c_dev->slow_clk);
+disable_fast_clk:
+ if (!i2c_dev->hw->has_single_clk_source)
+ clk_disable(i2c_dev->fast_clk);
+ return ret;
}
static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 03/18] i2c: tegra: Don't mark VI I2C as IRQ safe runtime PM
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, frankc, hverkuil,
sakari.ailus, robh+dt, helen.koike
Cc: digetx, sboyd, gregkh, linux-media, devicetree, linux-tegra,
linux-kernel, linux-i2c
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com>
Tegra VI I2C is part of VE power domain and typically used for
camera usecases.
VE power domain is not always on and is non-IRQ safe. So, IRQ safe
device cannot be attached to a non-IRQ safe domain as it prevents
powering off the PM domain and generic power domain driver will warn.
Current driver marks all I2C devices as IRQ safe and VI I2C device
does not require IRQ safe as it will not be used for atomic transfers.
This patch has fix to make VI I2C as non-IRQ safe.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/i2c/busses/i2c-tegra.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 1577296..3be1018 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -1750,7 +1750,15 @@ static int tegra_i2c_probe(struct platform_device *pdev)
goto unprepare_slow_clk;
}
- pm_runtime_irq_safe(&pdev->dev);
+ /*
+ * VI I2C is in VE power domain which is not always on and not
+ * an IRQ safe. So, IRQ safe device can't be attached to a non-IRQ
+ * safe domain as it prevents powering off the PM domain.
+ * Also, VI I2C device don't need to use runtime IRQ safe as it will
+ * not be used for atomic transfers.
+ */
+ if (!i2c_dev->is_vi)
+ pm_runtime_irq_safe(&pdev->dev);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = tegra_i2c_runtime_resume(&pdev->dev);
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 02/18] arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2C
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, frankc-DDmLM1+adcrQT0dZR+AlfA,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sakari.ailus-X3B1VOXEql0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
helen.koike-ZGY8ohtN/8qB+jHODAdFcQ
Cc: digetx-Re5JQEeQqe8AvxtiuMwx3w, sboyd-DgEjT+Ai2ygdnm+yROfE0A,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Tegra210 VI I2C is in VE power domain and i2c-vi node should have
power-domains property.
Current Tegra210 i2c-vi device node is missing both VI I2C clocks
and power-domains property.
This patch adds them.
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 0865508..3a4ed10 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -376,6 +376,12 @@
compatible = "nvidia,tegra210-i2c-vi";
reg = <0x0 0x546c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
+ <&tegra_car TEGRA210_CLK_I2CSLOW>;
+ clock-names = "div-clk", "slow";
+ resets = <&tegra_car TEGRA210_CLK_VI_I2C>;
+ reset-names = "i2c";
+ power-domains = <&pd_venc>;
status = "disabled";
};
};
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 01/18] dt-bindings: i2c: tegra: Document Tegra210 VI I2C clocks and power-domains
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, frankc-DDmLM1+adcrQT0dZR+AlfA,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sakari.ailus-X3B1VOXEql0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
helen.koike-ZGY8ohtN/8qB+jHODAdFcQ
Cc: digetx-Re5JQEeQqe8AvxtiuMwx3w, sboyd-DgEjT+Ai2ygdnm+yROfE0A,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
This patch documents missing clocks and power-domains of Tegra210 VI I2C.
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
.../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index 18c0de3..3f2f990 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -35,12 +35,12 @@ Required properties:
Due to above changes, Tegra114 I2C driver makes incompatible with
previous hardware driver. Hence, tegra114 I2C controller is compatible
with "nvidia,tegra114-i2c".
- nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the
- host1x domain and typically used for camera use-cases. This VI I2C
- controller is mostly compatible with the programming model of the
- regular I2C controllers with a few exceptions. The I2C registers start
- at an offset of 0xc00 (instead of 0), registers are 16 bytes apart
- (rather than 4) and the controller does not support slave mode.
+ nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus
+ and is part of VE power domain and typically used for camera use-cases.
+ This VI I2C controller is mostly compatible with the programming model
+ of the regular I2C controllers with a few exceptions. The I2C registers
+ start at an offset of 0xc00 (instead of 0), registers are 16 bytes
+ apart (rather than 4) and the controller does not support slave mode.
- reg: Should contain I2C controller registers physical address and length.
- interrupts: Should contain I2C controller interrupts.
- address-cells: Address cells for I2C device address.
@@ -53,10 +53,17 @@ Required properties:
- fast-clk
Tegra114:
- div-clk
+ Tegra210:
+ - div-clk
+ - slow (only for nvidia,tegra210-i2c-vi compatible node)
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- i2c
+- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must
+ include venc powergate node as vi i2c is part of VE power domain.
+ tegra210-i2c-vi:
+ - pd_venc
- dmas: Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names: Must include the following entries:
--
2.7.4
^ permalink raw reply related
* [RFC PATCH v1 00/18] Support for Tegra video capture from external sensor
From: Sowjanya Komatineni @ 2020-06-10 6:02 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, frankc, hverkuil,
sakari.ailus, robh+dt, helen.koike
Cc: digetx, sboyd, gregkh, linux-media, devicetree, linux-tegra,
linux-kernel, linux-i2c
This series adds support for video capture from external camera sensor to
Tegra video driver.
Jetson TX1 has camera expansion connector and supports custom camera module
designed as per TX1 design specification.
This series also enables camera capture support for Jetson Nano which has
Raspberry PI camera header.
This series is tested with IMX219 camera sensor.
This series include,
VI I2C related fixes
- Camera sensor programming happens through VI I2C which is on host1x bus.
- These patches includes device tree and I2C driver fixes for VI I2C.
Tegra video driver updates
- TPG Vs Non-TPG based on Kconfig
- Support for external sensor video capture based on device graph from DT.
- Support for selection ioctl operations
- Tegra MIPI CSI pads calibration
- CSI T-CLK and T-HS settle time computation based on clock rates.
Host1x driver updates
- Adds API to allow creating mipi device for specific device node.
- Splits MIPI pads calibrate start and waiting for calibration to be done.
Device tree updates
- Adds camera connector 2V8, 1V8, 1V2 regulator supplies to Jetson TX1 DT.
- Enabled VI and CSI support in Jetson Nano DT.
Sowjanya Komatineni (18):
dt-bindings: i2c: tegra: Document Tegra210 VI I2C clocks and
power-domains
arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2C
i2c: tegra: Don't mark VI I2C as IRQ safe runtime PM
i2c: tegra: Fix the error path in tegra_i2c_runtime_resume
i2c: tegra: Fix runtime resume to re-init VI I2C
i2c: tegra: Avoid tegra_i2c_init_dma() for Tegra210 vi i2c
media: tegra-video: Fix channel format alignment
media: tegra-video: Enable TPG based on kernel config
media: tegra-video: Update format lookup to offset based
dt-bindings: tegra: Document VI and CSI port nodes
media: tegra-video: Add support for external sensor capture
media: tegra-video: Add support for selection ioctl ops
gpu: host1x: mipi: Add of_tegra_mipi_request() API
gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait
media: tegra-video: Add CSI MIPI pads calibration
media: tegra-video: Compute settle times based on the clock rate
arm64: tegra: jetson-tx1: Add camera supplies
arm64: tegra: Enable Tegra VI CSI support for Jetson Nano
.../display/tegra/nvidia,tegra20-host1x.txt | 87 +++
.../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 19 +-
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 41 ++
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 10 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 +
drivers/gpu/drm/tegra/dsi.c | 7 +-
drivers/gpu/host1x/mipi.c | 33 +-
drivers/i2c/busses/i2c-tegra.c | 41 +-
drivers/staging/media/tegra-video/Kconfig | 7 +
drivers/staging/media/tegra-video/csi.c | 245 ++++++-
drivers/staging/media/tegra-video/csi.h | 9 +
drivers/staging/media/tegra-video/tegra210.c | 25 +-
drivers/staging/media/tegra-video/vi.c | 770 +++++++++++++++++++--
drivers/staging/media/tegra-video/vi.h | 23 +-
drivers/staging/media/tegra-video/video.c | 23 +-
include/linux/host1x.h | 3 +
16 files changed, 1253 insertions(+), 96 deletions(-)
--
2.7.4
^ permalink raw reply
* Re: [PATCH v4 5/7] iio: adc: exynos: Use input_device_enabled()
From: Michał Mirosław @ 2020-06-10 1:28 UTC (permalink / raw)
To: Andrzej Pietrasiewicz
Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-acpi-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
linux-input-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
patches-yzvPICuk2AA4QjBA90+/kJqQE7yCjDx5,
ibm-acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
platform-driver-x86-u79uwXL29TY76Z2rM5mHXA, Rafael J . Wysocki,
Len Brown, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Kukjin Kim, Krzysztof Kozlowski,
Dmitry Torokhov, Shawn Guo, Sascha Hauer
In-Reply-To: <20200608112211.12125-6-andrzej.p-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
On Mon, Jun 08, 2020 at 01:22:09PM +0200, Andrzej Pietrasiewicz wrote:
> A new helper is available, so use it. Inspecting 'users' member of
> input_dev requires taking device's mutex.
[...]
> --- a/drivers/iio/adc/exynos_adc.c
> +++ b/drivers/iio/adc/exynos_adc.c
> @@ -633,7 +633,9 @@ static irqreturn_t exynos_ts_isr(int irq, void *dev_id)
> bool pressed;
> int ret;
>
> - while (info->input->users) {
> + mutex_lock(&info->input->mutex);
> + while (input_device_enabled(info->input)) {
> + mutex_unlock(&info->input->mutex);
> ret = exynos_read_s3c64xx_ts(dev, &x, &y);
> if (ret == -ETIMEDOUT)
> break;
> @@ -651,6 +653,8 @@ static irqreturn_t exynos_ts_isr(int irq, void *dev_id)
> input_sync(info->input);
>
> usleep_range(1000, 1100);
> +
> + mutex_lock(&info->input->mutex);
> }
Missed an mutex_unlock() here.
>
> writel(0, ADC_V1_CLRINTPNDNUP(info->regs));
Best Regards,
Michał Mirosław
^ permalink raw reply
* (unknown)
From: Celine Marchand @ 2020-06-10 0:50 UTC (permalink / raw)
In-Reply-To: <1327230475.528260.1591750200327.ref@mail.yahoo.com>
Urgent attention please
Dearest, how are you? I am sorry for intruding your mailbox, but I need to talk to you. I got your email address in my dream and i wonder if it is correct because i emailed you earlier without any response. You should know that my contact to you is by the special grace of God. I am in urgent need of a reliable and reputable person and i believe you are a person of fine repute, hence the revelation of your email to me in the dream.
I am Mrs. Celine Marchand a citizen of France (French). But reside in Burkina Faso for business purposes. I need your collaboration to execute some projects worth € 2.800.000 Euro and it is very urgent as am presently in very critical condition.
Please reply through this email address ( celine88492-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org ) with your full contact information for more private and confidential communication.
Thank you as i wait for your reply.
Mrs. Celine Marchand
^ permalink raw reply
* [PATCH] memory: tegra: Constify struct thermal_cooling_device_ops
From: Rikard Falkeborn @ 2020-06-09 22:12 UTC (permalink / raw)
Cc: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, josephl-DDmLM1+adcrQT0dZR+AlfA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rikard Falkeborn
tegra210_emc_cd_ops is never modified and can be made const to allow the
compiler to put it in read-only memory.
Before:
text data bss dec hex filename
27936 5600 192 33728 83c0 drivers/memory/tegra/tegra210-emc-core.o
After:
text data bss dec hex filename
28040 5504 192 33736 83c8 drivers/memory/tegra/tegra210-emc-core.o
Signed-off-by: Rikard Falkeborn <rikard.falkeborn-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/memory/tegra/tegra210-emc-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c
index cdd663ba4733..2dfcc0e2e15d 100644
--- a/drivers/memory/tegra/tegra210-emc-core.c
+++ b/drivers/memory/tegra/tegra210-emc-core.c
@@ -711,7 +711,7 @@ static int tegra210_emc_cd_set_state(struct thermal_cooling_device *cd,
return 0;
}
-static struct thermal_cooling_device_ops tegra210_emc_cd_ops = {
+static const struct thermal_cooling_device_ops tegra210_emc_cd_ops = {
.get_max_state = tegra210_emc_cd_max_state,
.get_cur_state = tegra210_emc_cd_get_state,
.set_cur_state = tegra210_emc_cd_set_state,
--
2.27.0
^ permalink raw reply related
* Re: [PATCH v3 24/39] dt-bindings: memory: tegra30: Add memory client IDs
From: Rob Herring @ 2020-06-09 20:02 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Artur Świgoń, Georgi Djakov,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Thierry Reding,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Chanwoo Choi,
linux-pm-u79uwXL29TY76Z2rM5mHXA, Michael Turquette, Stephen Boyd,
Peter De Schrijver, Mikko Perttunen,
devicetree-u79uwXL29TY76Z2rM5mHXA, MyungJoo Ham, Jonathan Hunter,
Kyungmin Park
In-Reply-To: <20200607185530.18113-25-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Sun, 07 Jun 2020 21:55:15 +0300, Dmitry Osipenko wrote:
> Each memory client have a unique hardware ID, this patch adds these IDs.
>
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
^ permalink raw reply
* Re: [PATCH v3 23/39] dt-bindings: memory: tegra20: Add memory client IDs
From: Rob Herring @ 2020-06-09 20:01 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Michael Turquette, MyungJoo Ham,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Kyungmin Park,
linux-pm-u79uwXL29TY76Z2rM5mHXA, Artur Świgoń,
Chanwoo Choi, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Thierry Reding,
Mikko Perttunen, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Jonathan Hunter, Georgi Djakov,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Peter De Schrijver,
Stephen Boyd
In-Reply-To: <20200607185530.18113-24-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Sun, 07 Jun 2020 21:55:14 +0300, Dmitry Osipenko wrote:
> Each memory client have a unique hardware ID, this patch adds these IDs.
>
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> include/dt-bindings/memory/tegra20-mc.h | 53 +++++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
^ permalink raw reply
* Re: [PATCH] dt-bindings: mfd: max77620: Convert to json-schema
From: Mark Brown @ 2020-06-09 16:31 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Linus Walleij, Bartosz Golaszewski, Lee Jones,
Zhang Rui, Daniel Lezcano, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609162621.1769610-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 319 bytes --]
On Tue, Jun 09, 2020 at 06:26:21PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Convert the Maxim MAX77620 PMIC device tree bindings from free-form text
> format to json-schema.
Acked-by: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH] dt-bindings: mfd: max77620: Convert to json-schema
From: Thierry Reding @ 2020-06-09 16:26 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, Bartosz Golaszewski, Lee Jones, Mark Brown,
Zhang Rui, Daniel Lezcano, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Convert the Maxim MAX77620 PMIC device tree bindings from free-form text
format to json-schema.
This also pulls in the GPIO, regulator, pinmux and thermal bindings for
the corresponding subdevices into the top-level binding so that it can
be described more consistently.
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
.../bindings/gpio/gpio-max77620.txt | 25 -
.../devicetree/bindings/mfd/max77620.txt | 162 -----
.../devicetree/bindings/mfd/max77620.yaml | 662 ++++++++++++++++++
.../bindings/pinctrl/pinctrl-max77620.txt | 127 ----
.../bindings/regulator/regulator-max77620.txt | 222 ------
.../bindings/thermal/max77620_thermal.txt | 70 --
6 files changed, 662 insertions(+), 606 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-max77620.txt
delete mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt
create mode 100644 Documentation/devicetree/bindings/mfd/max77620.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
delete mode 100644 Documentation/devicetree/bindings/regulator/regulator-max77620.txt
delete mode 100644 Documentation/devicetree/bindings/thermal/max77620_thermal.txt
diff --git a/Documentation/devicetree/bindings/gpio/gpio-max77620.txt b/Documentation/devicetree/bindings/gpio/gpio-max77620.txt
deleted file mode 100644
index 410e716fd3d2..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-max77620.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-GPIO driver for MAX77620 Power management IC from Maxim Semiconductor.
-
-Device has 8 GPIO pins which can be configured as GPIO as well as the
-special IO functions.
-
-Required properties:
--------------------
-- gpio-controller : Marks the device node as a gpio controller.
-- #gpio-cells : Should be two. The first cell is the pin number and
- the second cell is used to specify the gpio polarity:
- 0 = active high
- 1 = active low
-For more details, please refer generic GPIO DT binding document
-<devicetree/bindings/gpio/gpio.txt>.
-
-Example:
---------
-#include <dt-bindings/mfd/max77620.h>
-...
-max77620@3c {
- compatible = "maxim,max77620";
-
- gpio-controller;
- #gpio-cells = <2>;
-};
diff --git a/Documentation/devicetree/bindings/mfd/max77620.txt b/Documentation/devicetree/bindings/mfd/max77620.txt
deleted file mode 100644
index 5a642a51d58e..000000000000
--- a/Documentation/devicetree/bindings/mfd/max77620.txt
+++ /dev/null
@@ -1,162 +0,0 @@
-MAX77620 Power management IC from Maxim Semiconductor.
-
-Required properties:
--------------------
-- compatible: Must be one of
- "maxim,max77620"
- "maxim,max20024"
- "maxim,max77663"
-- reg: I2C device address.
-
-Optional properties:
--------------------
-- interrupts: The interrupt on the parent the controller is
- connected to.
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells: is <2> and their usage is compliant to the 2 cells
- variant of <../interrupt-controller/interrupts.txt>
- IRQ numbers for different interrupt source of MAX77620
- are defined at dt-bindings/mfd/max77620.h.
-
-- system-power-controller: Indicates that this PMIC is controlling the
- system power, see [1] for more details.
-
-[1] Documentation/devicetree/bindings/power/power-controller.txt
-
-Optional subnodes and their properties:
-=======================================
-
-Flexible power sequence configurations:
---------------------------------------
-The Flexible Power Sequencer (FPS) allows each regulator to power up under
-hardware or software control. Additionally, each regulator can power on
-independently or among a group of other regulators with an adjustable power-up
-and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed
-to be part of a sequence allowing external regulators to be sequenced along
-with internal regulators. 32KHz clock can be programmed to be part of a
-sequence.
-
-The flexible sequencing structure consists of two hardware enable inputs
-(EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.
-Each master sequencing timer is programmable through its configuration
-register to have a hardware enable source (EN1 or EN2) or a software enable
-source (SW). When enabled/disabled, the master sequencing timer generates
-eight sequencing events on different time periods called slots. The time
-period between each event is programmable within the configuration register.
-Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
-sequence slave register which allows its enable source to be specified as
-a flexible power sequencer timer or a software bit. When a FPS source of
-regulators, GPIOs and clocks specifies the enable source to be a flexible
-power sequencer, the power up and power down delays can be specified in
-the regulators, GPIOs and clocks flexible power sequencer configuration
-registers.
-
-When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
-clock are set into following state at the sequencing event that
-corresponds to its flexible sequencer configuration register.
- Sleep state: In this state, regulators, GPIOs
- and 32KHz clock get disabled at
- the sequencing event.
- Global Low Power Mode (GLPM): In this state, regulators are set in
- low power mode at the sequencing event.
-
-The configuration parameters of FPS is provided through sub-node "fps"
-and their child for FPS specific. The child node name for FPS are "fps0",
-"fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.
-
-The FPS configurations like FPS source, power up and power down slots for
-regulators, GPIOs and 32kHz clocks are provided in their respective
-configuration nodes which is explained in respective sub-system DT
-binding document.
-
-There is need for different FPS configuration parameters based on system
-state like when system state changed from active to suspend or active to
-power off (shutdown).
-
-Optional properties:
--------------------
--maxim,fps-event-source: u32, FPS event source like external
- hardware input to PMIC i.e. EN0, EN1 or
- software (SW).
- The macros are defined on
- dt-bindings/mfd/max77620.h
- for different control source.
- - MAX77620_FPS_EVENT_SRC_EN0
- for hardware input pin EN0.
- - MAX77620_FPS_EVENT_SRC_EN1
- for hardware input pin EN1.
- - MAX77620_FPS_EVENT_SRC_SW
- for software control.
-
--maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds
- when system enters in to shutdown
- state.
-
--maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds
- when system enters in to suspend state.
-
--maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS
- event cleared (set to LOW) whether it
- should go to sleep state or low-power
- state. Following are valid values:
- - MAX77620_FPS_INACTIVE_STATE_SLEEP
- to set the PMIC state to sleep.
- - MAX77620_FPS_INACTIVE_STATE_LOW_POWER
- to set the PMIC state to low
- power.
- Absence of this property or other value
- will not change device state when FPS
- event get cleared.
-
-Here supported time periods by device in microseconds are as follows:
-MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
-MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
-MAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
-
--maxim,power-ok-control: configure map power ok bit
- 1: Enables POK(Power OK) to control nRST_IO and GPIO1
- POK function.
- 0: Disables POK control.
- if property missing, do not configure MPOK bit.
- If POK mapping is enabled for GPIO1/nRST_IO then,
- GPIO1/nRST_IO pins are HIGH only if all rails
- that have POK control enabled are HIGH.
- If any of the rails goes down(which are enabled for POK
- control) then, GPIO1/nRST_IO goes LOW.
- this property is valid for max20024 only.
-
-For DT binding details of different sub modules like GPIO, pincontrol,
-regulator, power, please refer respective device-tree binding document
-under their respective sub-system directories.
-
-Example:
---------
-#include <dt-bindings/mfd/max77620.h>
-
-max77620@3c {
- compatible = "maxim,max77620";
- reg = <0x3c>;
-
- interrupt-parent = <&intc>;
- interrupts = <0 86 IRQ_TYPE_NONE>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
-
- fps {
- fps0 {
- maxim,shutdown-fps-time-period-us = <1280>;
- maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
- };
-
- fps1 {
- maxim,shutdown-fps-time-period-us = <1280>;
- maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
- };
-
- fps2 {
- maxim,shutdown-fps-time-period-us = <1280>;
- maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/mfd/max77620.yaml b/Documentation/devicetree/bindings/mfd/max77620.yaml
new file mode 100644
index 000000000000..ad2f58ce3d5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/max77620.yaml
@@ -0,0 +1,662 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/max77620.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim Semiconductor MAX77620 Power Management IC
+
+maintainers:
+ - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
+
+description:
+ The Maxim MAX77620 is a system power management IC that can be used to
+ drive the power sequences need to boot an SoC as well as provide runtime
+ configurable power supplies for various aspects of that SoC.
+
+ In addition, the MAX77620 has 8 GPIO pins which can be configured as GPIO
+ as well as a set of special I/O functions.
+
+ The MAX77620 also supports alarm interrupts when its die temperature crosses
+ 120° C and 140° C. These threshold temperatures are not configurable. The
+ device does not provide the real temperature of die, but merely indicates
+ whether the temperature is above or below the threshold levels.
+
+properties:
+ compatible:
+ enum:
+ - maxim,max77620
+ - maxim,max20024
+ - maxim,max77663
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: The interrupt on the parent the controller is connected to.
+ $ref: "/schemas/types.yaml#/definitions/uint32-array"
+
+ interrupt-controller:
+ description: Marks the device node as an interrupt controller.
+
+ "#interrupt-cells":
+ description: Must be 2 and their usage is compliant to the 2 cells
+ variant of <../interrupt-controller/interrupts.txt>. IRQ numbers for
+ different interrupt source of MAX77620 are defined at
+ dt-bindings/mfd/max77620.h.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ const: 2
+
+ system-power-controller:
+ $ref: "/schemas/types.yaml#/definitions/flag"
+ description:
+ Indicates that this PMIC is controlling the system power, see
+ ../power/power-controller.txt for more details.
+
+ "#gpio-cells":
+ description: The first cell is the pin number and the second cell is used
+ to specify the GPIO polarity (0 = active high, 1 = active low).
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ const: 2
+
+ gpio-controller:
+ description: Marks the device node as a GPIO controller.
+ type: boolean
+
+ "#thermal-sensor-cells":
+ description: Please refer to ../thermal/thermal.txt for more details.
+ const: 0
+
+ fps:
+ description: |
+ The Flexible Power Sequencer (FPS) allows each regulator to power up
+ under hardware or software control. Additionally, each regulator can
+ power on independently or among a group of other regulators with an
+ adjustable power-up and power-down delays (sequencing). GPIO1, GPIO2,
+ and GPIO3 can be programmed to be part of a sequence allowing external
+ regulators to be sequenced along with internal regulators. 32KHz clock
+ can be programmed to be part of a sequence.
+
+ The flexible sequencing structure consists of two hardware enable
+ inputs (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1
+ and FPS2. Each master sequencing timer is programmable through its
+ configuration register to have a hardware enable source (EN1 or EN2)
+ or a software enable source (SW). When enabled/disabled, the master
+ sequencing timer generates eight sequencing events on different time
+ periods called slots. The time period between each event is
+ programmable within the configuration register. Each regulator,
+ GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power sequence
+ slave register which allows its enable source to be specified as a
+ flexible power sequencer timer or a software bit. When a FPS source
+ of regulators, GPIOs and clocks specifies the enable source to be a
+ flexible power sequencer, the power up and power down delays can be
+ specified in the regulators, GPIOs and clocks flexible power
+ sequencer configuration registers.
+
+ When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
+ clock are set into following state at the sequencing event that
+ corresponds to its flexible sequencer configuration register.
+
+ Sleep state: In this state, regulators, GPIOs and 32KHz clock get
+ disabled at the sequencing event.
+
+ Global Low Power Mode (GLPM): In this state, regulators are set in
+ low power mode at the sequencing event.
+
+ The configuration parameters of FPS is provided through sub-node
+ "fps" and their child for FPS specific. The child node name for FPS
+ are "fps0", "fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.
+
+ The FPS configurations like FPS source, power up and power down slots
+ for regulators, GPIOs and 32kHz clocks are provided in their respective
+ configuration nodes which is explained in respective sub-system DT
+ binding document.
+
+ There is need for different FPS configuration parameters based on
+ system state like when system state changed from active to suspend or
+ active to power off (shutdown).
+ type: object
+ properties:
+ maxim,fps-event-source:
+ description: |
+ FPS event source like external hardware input to PMIC i.e. EN0, EN1
+ or software (SW).
+
+ The macros are defined on dt-bindings/mfd/max77620.h for different
+ control source.
+
+ - MAX77620_FPS_EVENT_SRC_EN0: for hardware input pin EN0
+ - MAX77620_FPS_EVENT_SRC_EN1: for hardware input pin EN1
+ - MAX77620_FPS_EVENT_SRC_SW: for software control
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ maxim,shutdown-fps-time-period-us:
+ description: FPS time period in microseconds when system enters into
+ shutdown state.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ maxim,suspend-fps-time-period-us:
+ description: FPS time period in microseconds when system enters into
+ suspend state.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ maxim,device-state-on-disabled-event:
+ description: |
+ Describe the PMIC state when FPS event cleared (set to LOW) whether
+ it should go to sleep state or low-power state. Following are valid
+ values:
+
+ - MAX77620_FPS_INACTIVE_STATE_SLEEP: to set the PMIC state to
+ sleep
+ - MAX77620_FPS_INACTIVE_STATE_LOW_POWER: to set the PMIC state to
+ low power
+
+ Absence of this property or other value will not change device state
+ when FPS event get cleared.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ maxim,power-ok-control:
+ description: |
+ Used to configure the map power OK bit.
+
+ - 1: Enables POK(Power OK) to control nRST_IO and GPIO1 POK
+ function.
+ - 0: Disables POK control.
+
+ If this property is missing, do not configure MPOK bit. If POK
+ mapping is enabled for GPIO1/nRST_IO then, GPIO1/nRST_IO pins are
+ HIGH only if all rails that have POK control enabled are HIGH.
+
+ If any of the rails goes down(which are enabled for POK control)
+ then, GPIO1/nRST_IO goes LOW. this property is valid for max20024
+ only.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ regulators:
+ description: |
+ The MAX77620 has multiple DCDCs (sd[0-3]) and LDOs (ldo[0-8]). Details
+ about each of these regulators are defined using child nodes named after
+ the regulator under a top-level "regulators" node. Input supplies for
+ each of the regulators are defined in the "regulators" node.
+
+ Each subnode should contain the constraints and initialization details
+ for the corresponding regulator. The definition for each of these nodes
+ is defined using the standard bindings for regulators found in:
+
+ ../regulator/regulator.txt
+
+ Additional properties required to configure FPS parameters for SDs and
+ LDOs are defined below.
+ type: object
+ properties:
+ in-sd0-supply:
+ description: input supply for SD0, INA-SD0 or INB-SD0 pins
+
+ in-sd1-supply:
+ description: input supply for SD1
+
+ in-sd2-supply:
+ description: input supply for SD2
+
+ in-sd3-supply:
+ description: input supply for SD3
+
+ in-ld0-1-supply:
+ description: input supply for LDO0 and LDO1
+
+ in-ld2-supply:
+ description: input supply for LDO2
+
+ in-ld3-5-supply:
+ description: input supply for LDO3 and LDO5
+
+ in-ld4-6-supply:
+ description: input supply for LDO4 and LDO6
+
+ in-ld7-8-supply:
+ description: input supply for LDO7 and LDO8
+
+ patternProperties:
+ "^(sd[0-3]|ldo[0-8])$":
+ type: object
+ $ref: "/schemas/regulator/regulator.yaml"
+ properties:
+ maxim,active-fps-source:
+ description: |
+ FPS source for the regulators to get enabled/disabled when the
+ system is in active state. Valid values are:
+
+ - MAX77620_FPS_SRC_0: FPS source is FPS0.
+ - MAX77620_FPS_SRC_1: FPS source is FPS1.
+ - MAX77620_FPS_SRC_2: FPS source is FPS2.
+ - MAX77620_FPS_SRC_NONE: Regulator is not controlled by FPS
+ events and it gets enabled/disabled by register access.
+
+ Absence of this property will leave the FPS configuration
+ register for that regulator at the default value.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3 ]
+
+ maxim,active-fps-power-up-slot:
+ description: Sequencing event slot number on which the regulator
+ gets enabled when master FPS input event set to HIGH. Valid
+ values are 0 to 7. This is applicable if FPS source is selected
+ as FPS0, FPS1 or FPS2.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+
+ maxim,active-fps-power-down-slot:
+ description: Sequencing event slot number on which the regulator
+ gets disabled when master FPS input event set to LOW. Valid
+ values are 0 to 7. This is applicable if FPS source is selected
+ as FPS0, FPS1 or FPS2.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+
+ maxim,suspend-fps-source:
+ description: This is same as "maxim,active-fps-source" but the
+ value gets configured when the system enters suspend.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3 ]
+
+ maxim,suspend-fps-power-up-slot:
+ description: This is same as "maxim,active-fps-power-up-slot" but
+ the value gets configured when the system enters suspend. This
+ is applicable if the suspend state FPS source is selected as
+ FPS0, FPS1 or FPS2.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+
+ maxim,suspend-fps-power-down-slot:
+ description: This is same as "maxim,active-fps-power-down-slot"
+ but this value gets configured when the system enters suspend.
+ This is applicable if the suspend state FPS source is selected
+ as FPS0, FPS1 or FPS2.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+
+ maxim,ramp-rate-setting:
+ description: |
+ Ramp rate (uV/us) setting to be configured for the device. The
+ platform may have a ramp rate different from that advertised if
+ it has design variation from Maxim's recommended rate. In this
+ case, the platform specific ramp rate is used for ramp time
+ calculation and this property is used for device register
+ configurations. The measured ramp rate of platform is provided
+ by the "regulator-ramp-delay" property as described in
+ <../regulator/regulator.txt>.
+
+ The Maxim Max77620 PMIC supports the following ramp delays:
+
+ - SD: 13.75 mV/us, 27.5 mV/us, 55 mV/us
+ - LDOs: 5 mV/us, 100 mV/us
+
+ Note: If the measured ramp delay is same as advertised ramp
+ delay then it is not required to provide the ramp delay with
+ property "maxim,ramp-rate-setting". The ramp rate can be
+ provided by the regulator-ramp-delay which will be used for
+ ramp time calculation for voltage change as well as for
+ device configuration.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 5000, 13750, 27500, 55000, 100000 ]
+
+patternProperties:
+ "^gpio(@[0-9]+)?$":
+ type: object
+ properties:
+ gpio-hog:
+ $ref: "/schemas/types.yaml#/definitions/flag"
+
+ output-high:
+ $ref: "/schemas/types.yaml#/definitions/flag"
+
+ gpios:
+ $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+
+ "^pinmux(@[0-9]+)?$":
+ type: object
+ patternProperties:
+ "^gpio[0-7_]+$":
+ type: object
+ properties:
+ pins:
+ items:
+ pattern: "^gpio[0-7]$"
+ minItems: 1
+ maxItems: 8
+
+ function:
+ $ref: "/schemas/types.yaml#/definitions/string"
+ enum:
+ - gpio
+ - lpm-control-in
+ - fps-out
+ - 32k-out1
+ - sd0-dvs-in
+ - sd1-dvs-in
+ - reference-out
+
+ drive-push-pull:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1 ]
+
+ drive-open-drain:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1 ]
+
+ bias-pull-up:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1 ]
+
+ bias-pull-down:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1 ]
+
+ maxim,active-fps-source:
+ description: |
+ FPS source for the GPIOs to get enabled/disabled when the system
+ is in active state. Valid values are:
+
+ - MAX77620_FPS_SRC_0: FPS source is FPS0.
+ - MAX77620_FPS_SRC_1: FPS source is FPS1.
+ - MAX77620_FPS_SRC_2: FPS source is FPS2.
+ - MAX77620_FPS_SRC_NONE: GPIO is not controlled by FPS events
+ and it gets enabled/disabled by register access.
+
+ Absence of this property will leave the FPS configuration
+ register for that GPIO at the default value.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4 ]
+
+ maxim,active-fps-power-up-slot:
+ description: Sequencing event slot number on which the GPIO gets
+ enabled when master FPS input event set to HIGH. Valid values
+ are 0 to 7. This is applicable if FPS source is selected as
+ FPS0, FPS1 or FPS2.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+
+ maxim,active-fps-power-down-slot:
+ description: Sequencing event slot number on which the GPIO gets
+ disabled when master FPS input event set to LOW. Valid values
+ are 0 to 7. This is applicable if FPS source is selected as
+ FPS0, FPS1 or FPS2.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+
+ maxim,suspend-fps-source:
+ description: This is same as "maxim,active-fps-source" but the
+ value gets configured when the system enters suspend.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4 ]
+
+ maxim,suspend-fps-power-up-slot:
+ description: This is same as "maxim,active-fps-power-up-slot" but
+ the value gets configured when the system enters suspend. This
+ is applicable if the suspend state FPS source is selected as
+ FPS0, FPS1 or FPS2.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+
+ maxim,suspend-fps-power-down-slot:
+ description: This is same as "maxim,active-fps-power-down-slot"
+ but this value gets configured when the system enters suspend.
+ This is applicable if the suspend state FPS source is selected
+ as FPS0, FPS1 or FPS2.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+
+ required:
+ - pins
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: maxim,max77620
+ then:
+ properties:
+ fps:
+ properties:
+ maxim,shutdown-fps-time-period-us:
+ enum: [ 40, 80, 160, 320, 640, 1280, 2560, 5120 ]
+
+ maxim,suspend-fps-time-period-us:
+ enum: [ 40, 80, 160, 320, 640, 1280, 2560, 5120 ]
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: maxim,max20024
+ then:
+ properties:
+ fps:
+ properties:
+ maxim,shutdown-fps-time-period-us:
+ enum: [ 20, 40, 80, 160, 320, 640, 1280, 2540 ]
+
+ maxim,suspend-fps-time-period-us:
+ enum: [ 20, 40, 80, 160, 320, 640, 1280, 2540 ]
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: maxim,max77663
+ then:
+ properties:
+ fps:
+ properties:
+ maxim,shutdown-fps-time-period-us:
+ enum: [ 20, 40, 80, 160, 320, 640, 1280, 2540 ]
+
+ maxim,suspend-fps-time-period-us:
+ enum: [ 20, 40, 80, 160, 320, 640, 1280, 2540 ]
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/mfd/max77620.h>
+ #include <dt-bindings/thermal/thermal.h>
+
+ i2c@7000d000 {
+ reg = <0x7000d000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic: pmic@3c {
+ compatible = "maxim,max77620";
+ reg = <0x3c>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ #thermal-sensor-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&default>;
+
+ fps {
+ fps0 {
+ maxim,shutdown-fps-time-period-us = <1280>;
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+ };
+
+ fps1 {
+ maxim,shutdown-fps-time-period-us = <1280>;
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ };
+
+ fps2 {
+ maxim,shutdown-fps-time-period-us = <1280>;
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;
+ };
+ };
+
+ default: pinmux {
+ gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ gpio1 {
+ pins = "gpio1";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+ };
+
+ gpio2 {
+ pins = "gpio2";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+ };
+ };
+
+ regulators {
+ in-ldo0-1-supply = <&sd2>;
+ in-ldo7-8-supply = <&sd2>;
+
+ sd0 {
+ regulator-name = "vdd-core";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+ };
+
+ sd1 {
+ regulator-name = "vddio-ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+ };
+
+ sd2 {
+ regulator-name = "vdd-pre-reg";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ sd3 {
+ regulator-name = "vdd-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo0 {
+ regulator-name = "avdd-sys";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1 {
+ regulator-name = "vdd-pex";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ ldo2 {
+ regulator-name = "vddio-sdmmc3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo3 {
+ regulator-name = "vdd-cam-hv";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo4 {
+ regulator-name = "vdd-rtc";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo5 {
+ regulator-name = "avdd-ts-hv";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo6 {
+ regulator-name = "vdd-ts";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo7 {
+ regulator-name = "vdd-gen-pll-edp";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo8 {
+ regulator-name = "vdd-hdmi-dp";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+ };
+ };
+ };
+
+ thermal-zones {
+ pmic-die {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmic>;
+
+ trips {
+ pmic_die_warn_temp_thresh: hot-die {
+ temperature = <120000>;
+ type = "hot";
+ hysteresis = <0>;
+ };
+
+ pmic_die_crit_temp_thresh: cirtical-die {
+ temperature = <140000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&pmic_die_warn_temp_thresh>;
+ cooling-device = <&cool_dev THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ contribution = <100>;
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
deleted file mode 100644
index 511fc234558b..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
+++ /dev/null
@@ -1,127 +0,0 @@
-Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.
-
-Device has 8 GPIO pins which can be configured as GPIO as well as the
-special IO functions.
-
-Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
-for details of the common pinctrl bindings used by client devices,
-including the meaning of the phrase "pin configuration node".
-
-Optional Pinmux properties:
---------------------------
-Following properties are required if default setting of pins are required
-at boot.
-- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
-- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
- <pinctrl-bindings.txt>.
-
-The pin configurations are defined as child of the pinctrl states node. Each
-sub-node have following properties:
-
-Required properties:
-------------------
-- pins: List of pins. Valid values of pins properties are:
- gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.
-
-Optional properties:
--------------------
-Following are optional properties defined as pinmux DT binding document
-<pinctrl-bindings.txt>. Absence of properties will leave the configuration
-on default.
- function,
- drive-push-pull,
- drive-open-drain,
- bias-pull-up,
- bias-pull-down.
-
-Valid values for function properties are:
- gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,
- reference-out
-
-Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These
-customised properties are required to configure FPS configuration parameters
-of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more
-detail of Flexible Power Sequence (FPS).
-
-- maxim,active-fps-source: FPS source for the GPIOs to get
- enabled/disabled when system is in
- active state. Valid values are:
- - MAX77620_FPS_SRC_0,
- FPS source is FPS0.
- - MAX77620_FPS_SRC_1,
- FPS source is FPS1
- - MAX77620_FPS_SRC_2 and
- FPS source is FPS2
- - MAX77620_FPS_SRC_NONE.
- GPIO is not controlled
- by FPS events and it gets
- enabled/disabled by register
- access.
- Absence of this property will leave
- the FPS configuration register for that
- GPIO to default configuration.
-
-- maxim,active-fps-power-up-slot: Sequencing event slot number on which
- the GPIO get enabled when
- master FPS input event set to HIGH.
- Valid values are 0 to 7.
- This is applicable if FPS source is
- selected as FPS0, FPS1 or FPS2.
-
-- maxim,active-fps-power-down-slot: Sequencing event slot number on which
- the GPIO get disabled when master
- FPS input event set to LOW.
- Valid values are 0 to 7.
- This is applicable if FPS source is
- selected as FPS0, FPS1 or FPS2.
-
-- maxim,suspend-fps-source: This is same as property
- "maxim,active-fps-source" but value
- get configured when system enters in
- to suspend state.
-
-- maxim,suspend-fps-power-up-slot: This is same as property
- "maxim,active-fps-power-up-slot" but
- this value get configured into FPS
- configuration register when system
- enters into suspend.
- This is applicable if suspend state
- FPS source is selected as FPS0, FPS1 or
-
-- maxim,suspend-fps-power-down-slot: This is same as property
- "maxim,active-fps-power-down-slot" but
- this value get configured into FPS
- configuration register when system
- enters into suspend.
- This is applicable if suspend state
- FPS source is selected as FPS0, FPS1 or
- FPS2.
-
-Example:
---------
-#include <dt-bindings/mfd/max77620.h>
-...
-max77620@3c {
-
- pinctrl-names = "default";
- pinctrl-0 = <&spmic_default>;
-
- spmic_default: pinmux@0 {
- pin_gpio0 {
- pins = "gpio0";
- function = "gpio";
- };
-
- pin_gpio1 {
- pins = "gpio1";
- function = "fps-out";
- maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
- };
-
- pin_gpio2 {
- pins = "gpio2";
- function = "fps-out";
- maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/regulator/regulator-max77620.txt b/Documentation/devicetree/bindings/regulator/regulator-max77620.txt
deleted file mode 100644
index 1c4bfe786736..000000000000
--- a/Documentation/devicetree/bindings/regulator/regulator-max77620.txt
+++ /dev/null
@@ -1,222 +0,0 @@
-Regulator DT binding for MAX77620 Power management IC from Maxim Semiconductor.
-
-Device has multiple DCDC(sd[0-3] and LDOs(ldo[0-8]). The input supply
-of these regulators are defined under parent device node.
-Details of regulator properties are defined as child node under
-sub-node "regulators" which is child node of device node.
-
-Please refer file <Documentation/devicetree/bindings/regulator/regulator.txt>
-for common regulator bindings used by client.
-
-Following are properties of parent node related to regulators.
-
-Optional properties:
--------------------
-The input supply of regulators are the optional properties on the
-parent device node. The input supply of these regulators are provided
-through following properties:
-in-sd0-supply: Input supply for SD0, INA-SD0 or INB-SD0 pins.
-in-sd1-supply: Input supply for SD1.
-in-sd2-supply: Input supply for SD2.
-in-sd3-supply: Input supply for SD3.
-in-ldo0-1-supply: Input supply for LDO0 and LDO1.
-in-ldo2-supply: Input supply for LDO2.
-in-ldo3-5-supply: Input supply for LDO3 and LDO5
-in-ldo4-6-supply: Input supply for LDO4 and LDO6.
-in-ldo7-8-supply: Input supply for LDO7 and LDO8.
-
-Optional sub nodes for regulators under "regulators" subnode:
-------------------------------------------------------------
-The subnodes name is the name of regulator and it must be one of:
- sd[0-3], ldo[0-8]
-
-Each sub-node should contain the constraints and initialization
-information for that regulator. The definition for each of these
-nodes is defined using the standard binding for regulators found at
-<Documentation/devicetree/bindings/regulator/regulator.txt>.
-
-Theres are also additional properties for SD/LDOs. These additional properties
-are required to configure FPS configuration parameters for SDs and LDOs.
-Please refer <devicetree/bindings/mfd/max77620.txt> for more detail of Flexible
-Power Sequence (FPS).
-Following are additional properties:
-
-- maxim,active-fps-source: FPS source for the regulators to get
- enabled/disabled when system is in
- active state. Valid values are:
- - MAX77620_FPS_SRC_0,
- FPS source is FPS0.
- - MAX77620_FPS_SRC_1,
- FPS source is FPS1
- - MAX77620_FPS_SRC_2 and
- FPS source is FPS2
- - MAX77620_FPS_SRC_NONE.
- Regulator is not controlled
- by FPS events and it gets
- enabled/disabled by register
- access.
- Absence of this property will leave
- the FPS configuration register for that
- regulator to default configuration.
-
-- maxim,active-fps-power-up-slot: Sequencing event slot number on which
- the regulator get enabled when
- master FPS input event set to HIGH.
- Valid values are 0 to 7.
- This is applicable if FPS source is
- selected as FPS0, FPS1 or FPS2.
-
-- maxim,active-fps-power-down-slot: Sequencing event slot number on which
- the regulator get disabled when master
- FPS input event set to LOW.
- Valid values are 0 to 7.
- This is applicable if FPS source is
- selected as FPS0, FPS1 or FPS2.
-
-- maxim,suspend-fps-source: This is same as property
- "maxim,active-fps-source" but value
- get configured when system enters in
- to suspend state.
-
-- maxim,suspend-fps-power-up-slot: This is same as property
- "maxim,active-fps-power-up-slot" but
- this value get configured into FPS
- configuration register when system
- enters into suspend.
- This is applicable if suspend state
- FPS source is selected as FPS0, FPS1 or
-
-- maxim,suspend-fps-power-down-slot: This is same as property
- "maxim,active-fps-power-down-slot" but
- this value get configured into FPS
- configuration register when system
- enters into suspend.
- This is applicable if suspend state
- FPS source is selected as FPS0, FPS1 or
- FPS2.
-- maxim,ramp-rate-setting: integer, ramp rate(uV/us) setting to be
- configured to the device.
- The platform may have different ramp
- rate than advertised ramp rate if it has
- design variation from Maxim's
- recommended. On this case, platform
- specific ramp rate is used for ramp time
- calculation and this property is used
- for device register configurations.
- The measured ramp rate of platform is
- provided by the regulator-ramp-delay
- as described in <devicetree/bindings/
- regulator/regulator.txt>.
- Maxim Max77620 supports following ramp
- delay:
- SD: 13.75mV/us, 27.5mV/us, 55mV/us
- LDOs: 5mV/us, 100mV/us
-
-Note: If the measured ramp delay is same as advertised ramp delay then it is not
-required to provide the ramp delay with property "maxim,ramp-rate-setting". The
-ramp rate can be provided by the regulator-ramp-delay which will be used for
-ramp time calculation for voltage change as well as for device configuration.
-
-Example:
---------
-#include <dt-bindings/mfd/max77620.h>
-...
-max77620@3c {
- in-ldo0-1-supply = <&max77620_sd2>;
- in-ldo7-8-supply = <&max77620_sd2>;
- regulators {
- sd0 {
- regulator-name = "vdd-core";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
- };
-
- sd1 {
- regulator-name = "vddio-ddr";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-boot-on;
- maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
- };
-
- sd2 {
- regulator-name = "vdd-pre-reg";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- };
-
- sd3 {
- regulator-name = "vdd-1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo0 {
- regulator-name = "avdd-sys";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo1 {
- regulator-name = "vdd-pex";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- ldo2 {
- regulator-name = "vddio-sdmmc3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo3 {
- regulator-name = "vdd-cam-hv";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo4 {
- regulator-name = "vdd-rtc";
- regulator-min-microvolt = <1250000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo5 {
- regulator-name = "avdd-ts-hv";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo6 {
- regulator-name = "vdd-ts";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo7 {
- regulator-name = "vdd-gen-pll-edp";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo8 {
- regulator-name = "vdd-hdmi-dp";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/thermal/max77620_thermal.txt b/Documentation/devicetree/bindings/thermal/max77620_thermal.txt
deleted file mode 100644
index 323a3b3822aa..000000000000
--- a/Documentation/devicetree/bindings/thermal/max77620_thermal.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-Thermal driver for MAX77620 Power management IC from Maxim Semiconductor.
-
-Maxim Semiconductor MAX77620 supports alarm interrupts when its
-die temperature crosses 120C and 140C. These threshold temperatures
-are not configurable. Device does not provide the real temperature
-of die other than just indicating whether temperature is above or
-below threshold level.
-
-Required properties:
--------------------
-#thermal-sensor-cells: Please refer <devicetree/bindings/thermal/thermal.txt>
- for more details.
- The value must be 0.
-
-For more details, please refer generic thermal DT binding document
-<devicetree/bindings/thermal/thermal.txt>.
-
-Please refer <devicetree/bindings/mfd/max77620.txt> for mfd DT binding
-document for the MAX77620.
-
-Example:
---------
-#include <dt-bindings/mfd/max77620.h>
-#include <dt-bindings/thermal/thermal.h>
-...
-
-i2c@7000d000 {
- spmic: max77620@3c {
- compatible = "maxim,max77620";
- :::::
- #thermal-sensor-cells = <0>;
- :::
- };
-};
-
-cool_dev: cool-dev {
- compatible = "cooling-dev";
- #cooling-cells = <2>;
-};
-
-thermal-zones {
- PMIC-Die {
- polling-delay = <0>;
- polling-delay-passive = <0>;
- thermal-sensors = <&spmic>;
-
- trips {
- pmic_die_warn_temp_thresh: hot-die {
- temperature = <120000>;
- type = "hot";
- hysteresis = <0>;
- };
-
- pmic_die_cirt_temp_thresh: cirtical-die {
- temperature = <140000>;
- type = "critical";
- hysteresis = <0>;
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&pmic_die_warn_temp_thresh>;
- cooling-device = <&cool_dev THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- contribution = <100>;
- };
- };
- };
-};
--
2.24.1
^ permalink raw reply related
* [PATCH v6 6/6] drm/tegra: output: rgb: Wrap directly-connected panel into DRM bridge
From: Dmitry Osipenko @ 2020-06-09 13:28 UTC (permalink / raw)
To: Thierry Reding, Sam Ravnborg, Laurent Pinchart, Rob Herring,
Frank Rowand
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609132855.20975-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Currently Tegra DRM driver manually manages display panel, but this
management could be moved out into DRM core if we'll wrap panel into
DRM bridge. This patch wraps RGB panel into a DRM bridge and removes
manual handling of the panel from the RGB output code.
Suggested-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Acked-by: Sam Ravnborg <sam-uyr5N9Q2VtJg9hUCZPvPmw@public.gmane.org>
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/gpu/drm/tegra/rgb.c | 53 +++++++++++++------------------------
1 file changed, 18 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
index 9a7024ec96bc..a4c5a6066c54 100644
--- a/drivers/gpu/drm/tegra/rgb.c
+++ b/drivers/gpu/drm/tegra/rgb.c
@@ -8,7 +8,6 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge_connector.h>
-#include <drm/drm_panel.h>
#include <drm/drm_simple_kms_helper.h>
#include "drm.h"
@@ -86,15 +85,6 @@ static void tegra_dc_write_regs(struct tegra_dc *dc,
tegra_dc_writel(dc, table[i].value, table[i].offset);
}
-static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
- .reset = drm_atomic_helper_connector_reset,
- .detect = tegra_output_connector_detect,
- .fill_modes = drm_helper_probe_single_connector_modes,
- .destroy = tegra_output_connector_destroy,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
static enum drm_mode_status
tegra_rgb_connector_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -117,14 +107,8 @@ static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
struct tegra_output *output = encoder_to_output(encoder);
struct tegra_rgb *rgb = to_rgb(output);
- if (output->panel)
- drm_panel_disable(output->panel);
-
tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
tegra_dc_commit(rgb->dc);
-
- if (output->panel)
- drm_panel_unprepare(output->panel);
}
static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
@@ -133,9 +117,6 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
struct tegra_rgb *rgb = to_rgb(output);
u32 value;
- if (output->panel)
- drm_panel_prepare(output->panel);
-
tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
@@ -157,9 +138,6 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
tegra_dc_commit(rgb->dc);
-
- if (output->panel)
- drm_panel_enable(output->panel);
}
static int
@@ -278,6 +256,23 @@ int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
drm_encoder_helper_add(&output->encoder,
&tegra_rgb_encoder_helper_funcs);
+ /*
+ * Wrap directly-connected panel into DRM bridge in order to let
+ * DRM core to handle panel for us.
+ */
+ if (output->panel) {
+ output->bridge = devm_drm_panel_bridge_add(output->dev,
+ output->panel);
+ if (IS_ERR(output->bridge)) {
+ dev_err(output->dev,
+ "failed to wrap panel into bridge: %pe\n",
+ output->bridge);
+ return PTR_ERR(output->bridge);
+ }
+
+ output->panel = NULL;
+ }
+
/*
* Tegra devices that have LVDS panel utilize LVDS encoder bridge
* for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that
@@ -292,8 +287,7 @@ int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
* Newer device-trees utilize LVDS encoder bridge, which provides
* us with a connector and handles the display panel.
*
- * For older device-trees we fall back to our own connector and use
- * nvidia,panel phandle.
+ * For older device-trees we wrapped panel into the panel-bridge.
*/
if (output->bridge) {
err = drm_bridge_attach(&output->encoder, output->bridge,
@@ -313,17 +307,6 @@ int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
}
drm_connector_attach_encoder(connector, &output->encoder);
- } else {
- drm_connector_init(drm, &output->connector,
- &tegra_rgb_connector_funcs,
- DRM_MODE_CONNECTOR_LVDS);
- drm_connector_helper_add(&output->connector,
- &tegra_rgb_connector_helper_funcs);
- output->connector.dpms = DRM_MODE_DPMS_OFF;
-
- drm_connector_attach_encoder(&output->connector,
- &output->encoder);
- drm_connector_register(&output->connector);
}
err = tegra_output_init(drm, output);
--
2.26.0
^ permalink raw reply related
* [PATCH v6 5/6] drm/tegra: output: rgb: Support LVDS encoder bridge
From: Dmitry Osipenko @ 2020-06-09 13:28 UTC (permalink / raw)
To: Thierry Reding, Sam Ravnborg, Laurent Pinchart, Rob Herring,
Frank Rowand
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609132855.20975-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Newer Tegra device-trees will specify a video output graph, which involves
LVDS encoder bridge. This patch adds support for the LVDS encoder bridge
to the RGB output, allowing us to model the display hardware properly.
Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Acked-by: Sam Ravnborg <sam-uyr5N9Q2VtJg9hUCZPvPmw@public.gmane.org>
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/gpu/drm/tegra/rgb.c | 58 +++++++++++++++++++++++++++++++------
1 file changed, 49 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
index 0562a7eb793f..9a7024ec96bc 100644
--- a/drivers/gpu/drm/tegra/rgb.c
+++ b/drivers/gpu/drm/tegra/rgb.c
@@ -7,6 +7,7 @@
#include <linux/clk.h>
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge_connector.h>
#include <drm/drm_panel.h>
#include <drm/drm_simple_kms_helper.h>
@@ -267,24 +268,63 @@ int tegra_dc_rgb_remove(struct tegra_dc *dc)
int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
{
struct tegra_output *output = dc->rgb;
+ struct drm_connector *connector;
int err;
if (!dc->rgb)
return -ENODEV;
- drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
- DRM_MODE_CONNECTOR_LVDS);
- drm_connector_helper_add(&output->connector,
- &tegra_rgb_connector_helper_funcs);
- output->connector.dpms = DRM_MODE_DPMS_OFF;
-
drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS);
drm_encoder_helper_add(&output->encoder,
&tegra_rgb_encoder_helper_funcs);
- drm_connector_attach_encoder(&output->connector,
- &output->encoder);
- drm_connector_register(&output->connector);
+ /*
+ * Tegra devices that have LVDS panel utilize LVDS encoder bridge
+ * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that
+ * go to display panel's receiver.
+ *
+ * Encoder usually have a power-down control which needs to be enabled
+ * in order to transmit data to the panel. Historically devices that
+ * use an older device-tree version didn't model the bridge, assuming
+ * that encoder is turned ON by default, while today's DRM allows us
+ * to model LVDS encoder properly.
+ *
+ * Newer device-trees utilize LVDS encoder bridge, which provides
+ * us with a connector and handles the display panel.
+ *
+ * For older device-trees we fall back to our own connector and use
+ * nvidia,panel phandle.
+ */
+ if (output->bridge) {
+ err = drm_bridge_attach(&output->encoder, output->bridge,
+ NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ if (err) {
+ dev_err(output->dev, "failed to attach bridge: %d\n",
+ err);
+ return err;
+ }
+
+ connector = drm_bridge_connector_init(drm, &output->encoder);
+ if (IS_ERR(connector)) {
+ dev_err(output->dev,
+ "failed to initialize bridge connector: %pe\n",
+ connector);
+ return PTR_ERR(connector);
+ }
+
+ drm_connector_attach_encoder(connector, &output->encoder);
+ } else {
+ drm_connector_init(drm, &output->connector,
+ &tegra_rgb_connector_funcs,
+ DRM_MODE_CONNECTOR_LVDS);
+ drm_connector_helper_add(&output->connector,
+ &tegra_rgb_connector_helper_funcs);
+ output->connector.dpms = DRM_MODE_DPMS_OFF;
+
+ drm_connector_attach_encoder(&output->connector,
+ &output->encoder);
+ drm_connector_register(&output->connector);
+ }
err = tegra_output_init(drm, output);
if (err < 0) {
--
2.26.0
^ permalink raw reply related
* [PATCH v6 4/6] drm/tegra: output: Support DRM bridges
From: Dmitry Osipenko @ 2020-06-09 13:28 UTC (permalink / raw)
To: Thierry Reding, Sam Ravnborg, Laurent Pinchart, Rob Herring,
Frank Rowand
Cc: dri-devel, linux-tegra, devicetree, linux-kernel
In-Reply-To: <20200609132855.20975-1-digetx@gmail.com>
Newer Tegra device-trees will specify a video output graph which involves
a bridge. This patch adds initial support for the DRM bridges to the Tegra
DRM output.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/gpu/drm/tegra/drm.h | 2 ++
drivers/gpu/drm/tegra/output.c | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index b25443255be6..f38de08e0c95 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -12,6 +12,7 @@
#include <linux/gpio/consumer.h>
#include <drm/drm_atomic.h>
+#include <drm/drm_bridge.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder.h>
#include <drm/drm_fb_helper.h>
@@ -116,6 +117,7 @@ struct tegra_output {
struct device_node *of_node;
struct device *dev;
+ struct drm_bridge *bridge;
struct drm_panel *panel;
struct i2c_adapter *ddc;
const struct edid *edid;
diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c
index a6a711d54e88..ccd1421f1b24 100644
--- a/drivers/gpu/drm/tegra/output.c
+++ b/drivers/gpu/drm/tegra/output.c
@@ -5,6 +5,7 @@
*/
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_simple_kms_helper.h>
@@ -99,8 +100,19 @@ int tegra_output_probe(struct tegra_output *output)
if (!output->of_node)
output->of_node = output->dev->of_node;
+ err = drm_of_find_panel_or_bridge(output->of_node, -1, -1,
+ &output->panel, &output->bridge);
+ if (err && err != -ENODEV)
+ return err;
+
panel = of_parse_phandle(output->of_node, "nvidia,panel", 0);
if (panel) {
+ /*
+ * Don't mix nvidia,panel phandle with the graph in a
+ * device-tree.
+ */
+ WARN_ON(output->panel || output->bridge);
+
output->panel = of_drm_find_panel(panel);
of_node_put(panel);
--
2.26.0
^ permalink raw reply related
* [PATCH v6 3/6] drm/tegra: output: Don't leak OF node on error
From: Dmitry Osipenko @ 2020-06-09 13:28 UTC (permalink / raw)
To: Thierry Reding, Sam Ravnborg, Laurent Pinchart, Rob Herring,
Frank Rowand
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609132855.20975-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The OF node should be put before returning error in tegra_output_probe(),
otherwise node's refcount will be leaked.
Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Reviewed-by: Sam Ravnborg <sam-uyr5N9Q2VtJg9hUCZPvPmw@public.gmane.org>
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/gpu/drm/tegra/output.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c
index e36e5e7c2f69..a6a711d54e88 100644
--- a/drivers/gpu/drm/tegra/output.c
+++ b/drivers/gpu/drm/tegra/output.c
@@ -102,10 +102,10 @@ int tegra_output_probe(struct tegra_output *output)
panel = of_parse_phandle(output->of_node, "nvidia,panel", 0);
if (panel) {
output->panel = of_drm_find_panel(panel);
+ of_node_put(panel);
+
if (IS_ERR(output->panel))
return PTR_ERR(output->panel);
-
- of_node_put(panel);
}
output->edid = of_get_property(output->of_node, "nvidia,edid", &size);
@@ -113,13 +113,12 @@ int tegra_output_probe(struct tegra_output *output)
ddc = of_parse_phandle(output->of_node, "nvidia,ddc-i2c-bus", 0);
if (ddc) {
output->ddc = of_find_i2c_adapter_by_node(ddc);
+ of_node_put(ddc);
+
if (!output->ddc) {
err = -EPROBE_DEFER;
- of_node_put(ddc);
return err;
}
-
- of_node_put(ddc);
}
output->hpd_gpio = devm_gpiod_get_from_of_node(output->dev,
--
2.26.0
^ permalink raw reply related
* [PATCH v6 2/6] drm/of: Make drm_of_find_panel_or_bridge() to check graph's presence
From: Dmitry Osipenko @ 2020-06-09 13:28 UTC (permalink / raw)
To: Thierry Reding, Sam Ravnborg, Laurent Pinchart, Rob Herring,
Frank Rowand
Cc: dri-devel, linux-tegra, devicetree, linux-kernel
In-Reply-To: <20200609132855.20975-1-digetx@gmail.com>
When graph isn't defined in a device-tree, the of_graph_get_remote_node()
prints a noisy error message, telling that port node is not found. This is
undesirable behaviour in our case because absence of a panel/bridge graph
is a valid case. Let's check presence of the local port in a device-tree
before proceeding with parsing the graph.
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/gpu/drm/drm_of.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
index b50b44e76279..e0652c38f357 100644
--- a/drivers/gpu/drm/drm_of.c
+++ b/drivers/gpu/drm/drm_of.c
@@ -239,13 +239,24 @@ int drm_of_find_panel_or_bridge(const struct device_node *np,
struct drm_bridge **bridge)
{
int ret = -EPROBE_DEFER;
- struct device_node *remote;
+ struct device_node *local, *remote;
if (!panel && !bridge)
return -EINVAL;
if (panel)
*panel = NULL;
+ /*
+ * of_graph_get_remote_node() produces a noisy error message if port
+ * node isn't found and the absence of the port is a legit case here,
+ * so at first we silently check presence of the local port.
+ */
+ local = of_graph_get_local_port(np);
+ if (!local)
+ return -ENODEV;
+
+ of_node_put(local);
+
remote = of_graph_get_remote_node(np, port, endpoint);
if (!remote)
return -ENODEV;
--
2.26.0
^ permalink raw reply related
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