* Re: [PATCH v8 7/7] drm/panel-simple: Add missing connector type for some panels
From: Dmitry Osipenko @ 2020-06-20 13:19 UTC (permalink / raw)
To: Laurent Pinchart, Sam Ravnborg
Cc: Thierry Reding, Rob Herring, Frank Rowand,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
In-Reply-To: <20200620114934.GB5829-N3hz7ZxfLydczECFQUw77jytWr6r+dGw0E9HWUfgJXw@public.gmane.org>
20.06.2020 14:49, Laurent Pinchart пишет:
> Hi Sam and Dmitry,
>
> On Sat, Jun 20, 2020 at 01:21:32PM +0200, Sam Ravnborg wrote:
>> On Thu, Jun 18, 2020 at 01:27:03AM +0300, Dmitry Osipenko wrote:
>>> The DRM panel bridge core requires connector type to be set up properly,
>>> otherwise it rejects the panel. The missing connector type problem popped
>>> up while I was trying to wrap CLAA070WP03XG panel into a DRM bridge in
>>> order to test whether panel's rotation property work properly using
>>> panel-simple driver on NVIDIA Tegra30 Nexus 7 tablet device, which uses
>>> CLAA070WP03XG display panel.
>>>
>>> The NVIDIA Tegra DRM driver recently gained DRM bridges support for the
>>> RGB output and now driver wraps directly-connected panels into DRM bridge.
>>> Hence all panels should have connector type set properly now, otherwise
>>> the panel's wrapping fails.
>>>
>>> This patch adds missing connector types for the LVDS panels that are found
>>> on NVIDIA Tegra devices:
>>>
>>> 1. AUO B101AW03
>>> 2. Chunghwa CLAA070WP03XG
>>> 3. Chunghwa CLAA101WA01A
>>> 4. Chunghwa CLAA101WB01
>>> 5. EDT ET057090DHU
>>> 6. Innolux N156BGE L21
>>> 7. Samsung LTN101NT05
>>>
>>> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>
>> Very good to have this fixed.
>> I went ahead and pushed this commit to drm-misc-next as it is really
>> independent from the rest of the series.
>>
>>> ---
>>> drivers/gpu/drm/panel/panel-simple.c | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
>>> index 6764ac630e22..9eb2dbb7bfa6 100644
>>> --- a/drivers/gpu/drm/panel/panel-simple.c
>>> +++ b/drivers/gpu/drm/panel/panel-simple.c
>>> @@ -687,6 +687,7 @@ static const struct panel_desc auo_b101aw03 = {
>>> .width = 223,
>>> .height = 125,
>>> },
>>> + .connector_type = DRM_MODE_CONNECTOR_LVDS,
>
> Note that, for LVDS panels, the bus_format field is mandatory. This
> panel, for instance, according to
> http://www.vslcd.com/Specification/B101AW03%20V.0.pdf, uses
> MEDIA_BUS_FMT_RGB666_1X7X3_SPWG (see
> https://linuxtv.org/downloads/v4l-dvb-apis/userspace-api/v4l/subdev-formats.html#v4l2-mbus-pixelcode).
> The panels below need to be investigated similarly.
Okay! I'll add the missing field in v9.
>>> };
>>>
>>> static const struct display_timing auo_b101ean01_timing = {
>>> @@ -1340,6 +1341,7 @@ static const struct panel_desc chunghwa_claa070wp03xg = {
>>> .width = 94,
>>> .height = 150,
>>> },
>>> + .connector_type = DRM_MODE_CONNECTOR_LVDS,
>>> };
>>>
>>> static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
>>> @@ -1362,6 +1364,7 @@ static const struct panel_desc chunghwa_claa101wa01a = {
>>> .width = 220,
>>> .height = 120,
>>> },
>>> + .connector_type = DRM_MODE_CONNECTOR_LVDS,
>>> };
>>>
>>> static const struct drm_display_mode chunghwa_claa101wb01_mode = {
>>> @@ -1384,6 +1387,7 @@ static const struct panel_desc chunghwa_claa101wb01 = {
>>> .width = 223,
>>> .height = 125,
>>> },
>>> + .connector_type = DRM_MODE_CONNECTOR_LVDS,
>>> };
>>>
>>> static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
>>> @@ -1573,6 +1577,7 @@ static const struct panel_desc edt_et057090dhu = {
>>> },
>>> .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
>>> .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
>>> + .connector_type = DRM_MODE_CONNECTOR_LVDS,
>
> This contradicts .bus_format and .bus_flags that hint that the panel is
> a DPI panel, not an LVDS panel. According to
> https://www.lcdtek.co.uk/dwpdf/ET057090DHU-RoHS.pdf, this isn't an LVDS
> panel.
>
> I'm worried enough research hasn't gone into this patch, and I'd prefer
> reverting it until we check each panel individually.
Hello Sam and Laurent,
Oops! Good catch! Indeed, I blindly set the LVDS type to all these
panels. Please revert this patch, I'll double check each panel and
prepare an updated version of this patch. Thank you very much for the
review!
^ permalink raw reply
* Re: [PATCH v11 1/4] drm/panel: Add helper for reading DT rotation
From: Dmitry Osipenko @ 2020-06-20 14:25 UTC (permalink / raw)
To: Thierry Reding, Thomas Zimmermann, Derek Basehore, Sam Ravnborg,
Laurent Pinchart, Sean Paul, Daniel Vetter,
Ville Syrjälä, Emil Velikov, Daniel Stone
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200617231842.30671-2-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
18.06.2020 02:18, Dmitry Osipenko пишет:
> From: Derek Basehore <dbasehore-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>
> This adds a helper function for reading the rotation (panel
> orientation) from the device tree.
>
> Signed-off-by: Derek Basehore <dbasehore-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Reviewed-by: Sam Ravnborg <sam-uyr5N9Q2VtJg9hUCZPvPmw@public.gmane.org>
> ---
My t-b accidentally got lost after rebase, here it is:
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
^ permalink raw reply
* Re: [PATCH v8 7/7] drm/panel-simple: Add missing connector type for some panels
From: Sam Ravnborg @ 2020-06-20 14:31 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Laurent Pinchart, Thierry Reding, Rob Herring, Frank Rowand,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
In-Reply-To: <ea421084-a91c-bc03-5997-1723075b7cae-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Dmitry
>
> Oops! Good catch!
Yep, thanks Laurent. Should have taken a better look before applying.
> Indeed, I blindly set the LVDS type to all these
> panels. Please revert this patch, I'll double check each panel and
> prepare an updated version of this patch. Thank you very much for the
> review!
If you can prepare a fix within a few days then lets wait for that.
I will do a better review next time.
Sam
^ permalink raw reply
* Re: [PATCH v8 7/7] drm/panel-simple: Add missing connector type for some panels
From: Dmitry Osipenko @ 2020-06-20 15:05 UTC (permalink / raw)
To: Sam Ravnborg
Cc: Laurent Pinchart, Thierry Reding, Rob Herring, Frank Rowand,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
In-Reply-To: <20200620143114.GA22329-uyr5N9Q2VtJg9hUCZPvPmw@public.gmane.org>
20.06.2020 17:31, Sam Ravnborg пишет:
> Hi Dmitry
>
>>
>> Oops! Good catch!
> Yep, thanks Laurent. Should have taken a better look before applying.
>
>> Indeed, I blindly set the LVDS type to all these
>> panels. Please revert this patch, I'll double check each panel and
>> prepare an updated version of this patch. Thank you very much for the
>> review!
>
> If you can prepare a fix within a few days then lets wait for that.
> I will do a better review next time.
Hello Sam,
I should be able to make it later today or tomorrow. Could you please
clarify what do you mean by the fix, do you what it to be as an
additional patch on top of the applied one or a new version of the patch?
^ permalink raw reply
* Re: [PATCH v8 7/7] drm/panel-simple: Add missing connector type for some panels
From: Sam Ravnborg @ 2020-06-20 15:30 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Laurent Pinchart, Thierry Reding, Rob Herring, Frank Rowand,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
In-Reply-To: <e77a34c1-3e0b-7f30-25d0-a955ec8d8c86-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Dmitry
On Sat, Jun 20, 2020 at 06:05:37PM +0300, Dmitry Osipenko wrote:
> 20.06.2020 17:31, Sam Ravnborg пишет:
> > Hi Dmitry
> >
> >>
> >> Oops! Good catch!
> > Yep, thanks Laurent. Should have taken a better look before applying.
> >
> >> Indeed, I blindly set the LVDS type to all these
> >> panels. Please revert this patch, I'll double check each panel and
> >> prepare an updated version of this patch. Thank you very much for the
> >> review!
> >
> > If you can prepare a fix within a few days then lets wait for that.
> > I will do a better review next time.
>
> Hello Sam,
>
> I should be able to make it later today or tomorrow. Could you please
> clarify what do you mean by the fix, do you what it to be as an
> additional patch on top of the applied one or a new version of the patch?
An additional patch on top of the one applied.
It shall carry a proper fixes: tag like this:
Fixes: 94f07917ebe8 ("drm/panel-simple: Add missing connector type for some panels")
Cc: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Sam Ravnborg <sam-uyr5N9Q2VtJg9hUCZPvPmw@public.gmane.org>
Cc: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Sam
^ permalink raw reply
* Re: [PATCH v8 7/7] drm/panel-simple: Add missing connector type for some panels
From: Dmitry Osipenko @ 2020-06-20 16:18 UTC (permalink / raw)
To: Sam Ravnborg
Cc: Laurent Pinchart, Thierry Reding, Rob Herring, Frank Rowand,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
In-Reply-To: <20200620153012.GA22743-uyr5N9Q2VtJg9hUCZPvPmw@public.gmane.org>
20.06.2020 18:30, Sam Ravnborg пишет:
> Hi Dmitry
> On Sat, Jun 20, 2020 at 06:05:37PM +0300, Dmitry Osipenko wrote:
>> 20.06.2020 17:31, Sam Ravnborg пишет:
>>> Hi Dmitry
>>>
>>>>
>>>> Oops! Good catch!
>>> Yep, thanks Laurent. Should have taken a better look before applying.
>>>
>>>> Indeed, I blindly set the LVDS type to all these
>>>> panels. Please revert this patch, I'll double check each panel and
>>>> prepare an updated version of this patch. Thank you very much for the
>>>> review!
>>>
>>> If you can prepare a fix within a few days then lets wait for that.
>>> I will do a better review next time.
>>
>> Hello Sam,
>>
>> I should be able to make it later today or tomorrow. Could you please
>> clarify what do you mean by the fix, do you what it to be as an
>> additional patch on top of the applied one or a new version of the patch?
> An additional patch on top of the one applied.
> It shall carry a proper fixes: tag like this:
>
> Fixes: 94f07917ebe8 ("drm/panel-simple: Add missing connector type for some panels")
> Cc: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Sam Ravnborg <sam-uyr5N9Q2VtJg9hUCZPvPmw@public.gmane.org>
> Cc: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Okay!
^ permalink raw reply
* Re: [PATCH v7 31/36] staging: tegra-vde: fix common struct sg_table related issues
From: Dmitry Osipenko @ 2020-06-21 4:00 UTC (permalink / raw)
To: Marek Szyprowski
Cc: devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b, Bartlomiej Zolnierkiewicz,
David Airlie, Greg Kroah-Hartman,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Jonathan Hunter,
linaro-mm-sig-cunTk1MwBs8s++Sfvej+rw,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Thierry Reding,
Daniel Vetter, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
Mauro Carvalho Chehab, Robin Murphy, Christoph Hellwig,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200619103636.11974-32-m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
В Fri, 19 Jun 2020 12:36:31 +0200
Marek Szyprowski <m.szyprowski@samsung.com> пишет:
> The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg()
> function returns the number of the created entries in the DMA address
> space. However the subsequent calls to the
> dma_sync_sg_for_{device,cpu}() and dma_unmap_sg must be called with
> the original number of the entries passed to the dma_map_sg().
>
> struct sg_table is a common structure used for describing a
> non-contiguous memory buffer, used commonly in the DRM and graphics
> subsystems. It consists of a scatterlist with memory pages and DMA
> addresses (sgl entry), as well as the number of scatterlist entries:
> CPU pages (orig_nents entry) and DMA mapped pages (nents entry).
>
> It turned out that it was a common mistake to misuse nents and
> orig_nents entries, calling DMA-mapping functions with a wrong number
> of entries or ignoring the number of mapped entries returned by the
> dma_map_sg() function.
>
> To avoid such issues, lets use a common dma-mapping wrappers operating
> directly on the struct sg_table objects and use scatterlist page
> iterators where possible. This, almost always, hides references to the
> nents and orig_nents entries, making the code robust, easier to follow
> and copy/paste safe.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> drivers/staging/media/tegra-vde/iommu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/media/tegra-vde/iommu.c
> b/drivers/staging/media/tegra-vde/iommu.c index
> 6af863d92123..adf8dc7ee25c 100644 ---
> a/drivers/staging/media/tegra-vde/iommu.c +++
> b/drivers/staging/media/tegra-vde/iommu.c @@ -36,8 +36,8 @@ int
> tegra_vde_iommu_map(struct tegra_vde *vde,
> addr = iova_dma_addr(&vde->iova, iova);
>
> - size = iommu_map_sg(vde->domain, addr, sgt->sgl, sgt->nents,
> - IOMMU_READ | IOMMU_WRITE);
> + size = iommu_map_sgtable(vde->domain, addr, sgt,
> + IOMMU_READ | IOMMU_WRITE);
> if (!size) {
> __free_iova(&vde->iova, iova);
> return -ENXIO;
Ahh, I saw the build failure report. You're changing the DMA API in
this series, while DMA API isn't used by this driver, it uses IOMMU
API. Hence there is no need to touch this code. Similar problem in the
host1x driver patch.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* Re: Re: [PATCH] [v3] dmaengine: tegra210-adma: Fix runtime PM imbalance on error
From: dinghao.liu-Y5EWUtBUdg4nDS1+zs4M5A @ 2020-06-21 5:27 UTC (permalink / raw)
To: Jon Hunter
Cc: kjlu-OJFnDUYgAso, Laxman Dewangan, Dan Williams, Vinod Koul,
Thierry Reding, dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <f4034e16-e720-57c4-eb9d-733786212a4a-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >>
> >> Why noidle?
> >>
> >
> > _noidle is enough for fixing this bug. _sync may suspend
> > the device beyond expectation.
>
> In that case, then the other instance you are fixing with this patch is
> not correct.
>
Fine. I will fix this soon.
Regards,
Dinghao
^ permalink raw reply
* [PATCH] [v4] dmaengine: tegra210-adma: Fix runtime PM imbalance on error
From: Dinghao Liu @ 2020-06-21 5:47 UTC (permalink / raw)
To: dinghao.liu-Y5EWUtBUdg4nDS1+zs4M5A, kjlu-OJFnDUYgAso
Cc: Laxman Dewangan, Jon Hunter, Vinod Koul, Dan Williams,
Thierry Reding, dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
pm_runtime_get_sync() increments the runtime PM usage counter even
when it returns an error code. Thus a pairing decrement is needed on
the error handling path to keep the counter balanced.
Signed-off-by: Dinghao Liu <dinghao.liu-Y5EWUtBUdg4nDS1+zs4M5A@public.gmane.org>
---
v2: - Merge two patches that fix runtime PM imbalance in
tegra_adma_probe() and tegra_adma_alloc_chan_resources()
respectively.
v3: - Use pm_runtime_put_noidle() instead of pm_runtime_put_sync()
in tegra_adma_alloc_chan_resources().
v4: - Use pm_runtime_put_noidle() instead of pm_runtime_put_sync()
in tegra_adma_probe().
---
drivers/dma/tegra210-adma.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index db58d7e4f9fe..c5fa2ef74abc 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -658,6 +658,7 @@ static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
ret = pm_runtime_get_sync(tdc2dev(tdc));
if (ret < 0) {
+ pm_runtime_put_noidle(tdc2dev(tdc));
free_irq(tdc->irq, tdc);
return ret;
}
@@ -869,8 +870,10 @@ static int tegra_adma_probe(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_get_sync(&pdev->dev);
- if (ret < 0)
+ if (ret < 0) {
+ pm_runtime_put_noidle(&pdev->dev);
goto rpm_disable;
+ }
ret = tegra_adma_init(tdma);
if (ret)
--
2.17.1
^ permalink raw reply related
* Re: [PATCH 5.7 000/376] 5.7.5-rc1 review
From: Greg Kroah-Hartman @ 2020-06-21 9:24 UTC (permalink / raw)
To: Jon Hunter
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
torvalds-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b,
akpm-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b,
linux-0h96xk9xTtrk1uMJSBkQmQ, shuah-DgEjT+Ai2ygdnm+yROfE0A,
patches-ssFOTAMYnuFg9hUCZPvPmw,
ben.hutchings-4yDnlxn2s6sWdaTGBSpHTA,
lkft-triage-cunTk1MwBs8s++Sfvej+rw, stable-u79uwXL29TY76Z2rM5mHXA,
linux-tegra
In-Reply-To: <8d7dd6fa-3018-5da3-0736-0d58fad8fd68-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Sat, Jun 20, 2020 at 10:52:19AM +0100, Jon Hunter wrote:
>
> On 19/06/2020 15:28, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 5.7.5 release.
> > There are 376 patches in this series, all will be posted as a response
> > to this one. If anyone has any issues with these being applied, please
> > let me know.
> >
> > Responses should be made by Sun, 21 Jun 2020 14:15:50 +0000.
> > Anything received after that time might be too late.
> >
> > The whole patch series can be found in one patch at:
> > https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.7.5-rc1.gz
> > or in the git tree and branch at:
> > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.7.y
> > and the diffstat can be found below.
> >
> > thanks,
> >
> > greg k-h
>
> All tests are passing for Tegra ...
>
> Test results for stable-v5.7:
> 11 builds: 11 pass, 0 fail
> 26 boots: 26 pass, 0 fail
> 56 tests: 56 pass, 0 fail
>
> Linux version: 5.7.5-rc1-g19411dc6b061
> Boards tested: tegra124-jetson-tk1, tegra186-p2771-0000,
> tegra194-p2972-0000, tegra20-ventana,
> tegra210-p2371-2180, tegra210-p3450-0000,
> tegra30-cardhu-a04
Thanks for testing all of these and letting me know.
greg k-h
^ permalink raw reply
* Re: [PATCH v4] dmaengine: tegra210-adma: Fix runtime PM imbalance on error
From: Markus Elfring @ 2020-06-21 10:50 UTC (permalink / raw)
To: Dinghao Liu, dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Dan Williams,
Jonathan Hunter, Laxman Dewangan, Thierry Reding, Vinod Koul,
Aditya Pakki, Kangjie Lu, Navid Emamdoost, Qiushi Wu
I propose to combine two tags in the previous patch subject.
> pm_runtime_get_sync() increments the runtime PM usage counter even
> when it returns an error code. Thus a pairing decrement is needed on
> the error handling path to keep the counter balanced.
* Can an imperative wording be nicer for the change description?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=64677779e8962c20b580b471790fe42367750599#n151
* Would you like to add the tag “Fixes” to the commit message?
> ---
> drivers/dma/tegra210-adma.c | 5 ++++-
I find it nicer to replace the triple dashes before this diffstat
by a blank line.
Regards,
Markus
^ permalink raw reply
* Re: [PATCH v7 26/36] drm: host1x: fix common struct sg_table related issues
From: kernel test robot @ 2020-06-21 14:47 UTC (permalink / raw)
To: Marek Szyprowski, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linaro-mm-sig-cunTk1MwBs8s++Sfvej+rw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: kbuild-all-hn68Rpc1hR1g9hUCZPvPmw, Bartlomiej Zolnierkiewicz,
David Airlie, clang-built-linux-/JYPxA39Uh5TLH3MbocFFw,
Thierry Reding, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Robin Murphy,
Christoph Hellwig
In-Reply-To: <20200619103636.11974-27-m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 7211 bytes --]
Hi Marek,
I love your patch! Yet something to improve:
[auto build test ERROR on next-20200618]
[also build test ERROR on v5.8-rc1]
[cannot apply to linuxtv-media/master staging/staging-testing drm-exynos/exynos-drm-next drm-intel/for-linux-next linus/master v5.8-rc1 v5.7 v5.7-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Marek-Szyprowski/DRM-fix-struct-sg_table-nents-vs-orig_nents-misuse/20200619-184302
base: ce2cc8efd7a40cbd17841add878cb691d0ce0bba
config: arm64-randconfig-r036-20200621 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project ef455a55bcf2cfea04a99c361b182ad18b7f03f1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
All errors (new ones prefixed by >>):
>> drivers/gpu/host1x/job.c:230:10: error: implicit declaration of function 'iommu_map_sgtable' [-Werror,-Wimplicit-function-declaration]
err = iommu_map_sgtable(host->domain,
^
drivers/gpu/host1x/job.c:230:10: note: did you mean 'dma_map_sgtable'?
include/linux/dma-mapping.h:628:19: note: 'dma_map_sgtable' declared here
static inline int dma_map_sgtable(struct device *dev, struct sg_table *sgt,
^
1 error generated.
vim +/iommu_map_sgtable +230 drivers/gpu/host1x/job.c
100
101 static unsigned int pin_job(struct host1x *host, struct host1x_job *job)
102 {
103 struct host1x_client *client = job->client;
104 struct device *dev = client->dev;
105 struct iommu_domain *domain;
106 unsigned int i;
107 int err;
108
109 domain = iommu_get_domain_for_dev(dev);
110 job->num_unpins = 0;
111
112 for (i = 0; i < job->num_relocs; i++) {
113 struct host1x_reloc *reloc = &job->relocs[i];
114 dma_addr_t phys_addr, *phys;
115 struct sg_table *sgt;
116
117 reloc->target.bo = host1x_bo_get(reloc->target.bo);
118 if (!reloc->target.bo) {
119 err = -EINVAL;
120 goto unpin;
121 }
122
123 /*
124 * If the client device is not attached to an IOMMU, the
125 * physical address of the buffer object can be used.
126 *
127 * Similarly, when an IOMMU domain is shared between all
128 * host1x clients, the IOVA is already available, so no
129 * need to map the buffer object again.
130 *
131 * XXX Note that this isn't always safe to do because it
132 * relies on an assumption that no cache maintenance is
133 * needed on the buffer objects.
134 */
135 if (!domain || client->group)
136 phys = &phys_addr;
137 else
138 phys = NULL;
139
140 sgt = host1x_bo_pin(dev, reloc->target.bo, phys);
141 if (IS_ERR(sgt)) {
142 err = PTR_ERR(sgt);
143 goto unpin;
144 }
145
146 if (sgt) {
147 unsigned long mask = HOST1X_RELOC_READ |
148 HOST1X_RELOC_WRITE;
149 enum dma_data_direction dir;
150
151 switch (reloc->flags & mask) {
152 case HOST1X_RELOC_READ:
153 dir = DMA_TO_DEVICE;
154 break;
155
156 case HOST1X_RELOC_WRITE:
157 dir = DMA_FROM_DEVICE;
158 break;
159
160 case HOST1X_RELOC_READ | HOST1X_RELOC_WRITE:
161 dir = DMA_BIDIRECTIONAL;
162 break;
163
164 default:
165 err = -EINVAL;
166 goto unpin;
167 }
168
169 err = dma_map_sgtable(dev, sgt, dir, 0);
170 if (err)
171 goto unpin;
172
173 job->unpins[job->num_unpins].dev = dev;
174 job->unpins[job->num_unpins].dir = dir;
175 phys_addr = sg_dma_address(sgt->sgl);
176 }
177
178 job->addr_phys[job->num_unpins] = phys_addr;
179 job->unpins[job->num_unpins].bo = reloc->target.bo;
180 job->unpins[job->num_unpins].sgt = sgt;
181 job->num_unpins++;
182 }
183
184 for (i = 0; i < job->num_gathers; i++) {
185 struct host1x_job_gather *g = &job->gathers[i];
186 size_t gather_size = 0;
187 struct scatterlist *sg;
188 struct sg_table *sgt;
189 dma_addr_t phys_addr;
190 unsigned long shift;
191 struct iova *alloc;
192 dma_addr_t *phys;
193 unsigned int j;
194
195 g->bo = host1x_bo_get(g->bo);
196 if (!g->bo) {
197 err = -EINVAL;
198 goto unpin;
199 }
200
201 /**
202 * If the host1x is not attached to an IOMMU, there is no need
203 * to map the buffer object for the host1x, since the physical
204 * address can simply be used.
205 */
206 if (!iommu_get_domain_for_dev(host->dev))
207 phys = &phys_addr;
208 else
209 phys = NULL;
210
211 sgt = host1x_bo_pin(host->dev, g->bo, phys);
212 if (IS_ERR(sgt)) {
213 err = PTR_ERR(sgt);
214 goto unpin;
215 }
216
217 if (!IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL) && host->domain) {
218 for_each_sgtable_sg(sgt, sg, j)
219 gather_size += sg->length;
220 gather_size = iova_align(&host->iova, gather_size);
221
222 shift = iova_shift(&host->iova);
223 alloc = alloc_iova(&host->iova, gather_size >> shift,
224 host->iova_end >> shift, true);
225 if (!alloc) {
226 err = -ENOMEM;
227 goto unpin;
228 }
229
> 230 err = iommu_map_sgtable(host->domain,
231 iova_dma_addr(&host->iova, alloc),
232 sgt, IOMMU_READ);
233 if (err == 0) {
234 __free_iova(&host->iova, alloc);
235 err = -EINVAL;
236 goto unpin;
237 }
238
239 job->unpins[job->num_unpins].size = gather_size;
240 phys_addr = iova_dma_addr(&host->iova, alloc);
241 } else if (sgt) {
242 err = dma_map_sgtable(host->dev, sgt, DMA_TO_DEVICE, 0);
243 if (err)
244 goto unpin;
245
246 job->unpins[job->num_unpins].dir = DMA_TO_DEVICE;
247 job->unpins[job->num_unpins].dev = host->dev;
248 phys_addr = sg_dma_address(sgt->sgl);
249 }
250
251 job->addr_phys[job->num_unpins] = phys_addr;
252 job->gather_addr_phys[i] = phys_addr;
253
254 job->unpins[job->num_unpins].bo = g->bo;
255 job->unpins[job->num_unpins].sgt = sgt;
256 job->num_unpins++;
257 }
258
259 return 0;
260
261 unpin:
262 host1x_job_unpin(job);
263 return err;
264 }
265
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 35472 bytes --]
[-- Attachment #3: Type: text/plain, Size: 0 bytes --]
^ permalink raw reply
* [TEGRA194_CPUFREQ Patch v3 0/4] Add cpufreq driver for Tegra194
From: Sumit Gupta @ 2020-06-21 21:34 UTC (permalink / raw)
To: rjw-LthD3rsA81gm4RdzfppkhA, viresh.kumar-QSEj5FYQhm4dnm+yROfE0A,
catalin.marinas-5wv7dgnIgG8, will-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, talho-DDmLM1+adcrQT0dZR+AlfA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: bbasu-DDmLM1+adcrQT0dZR+AlfA, sumitg-DDmLM1+adcrQT0dZR+AlfA,
mperttunen-DDmLM1+adcrQT0dZR+AlfA
The patch series adds cpufreq driver for Tegra194 SOC.
v2[2] -> v3
- Set same policy for all cpus in a cluster[Viresh].
- Add compatible string for CPU Complex under cpus node[Thierry].
- Add reference to bpmp node under cpus node[Thierry].
- Bind cpufreq driver to CPU Complex compatible string[Thierry].
- Remove patch to get bpmp data as now using cpus node to get that[Thierry].
v1[1] -> v2:
- Remove cpufreq_lock mutex from tegra194_cpufreq_set_target [Viresh].
- Remove CPUFREQ_ASYNC_NOTIFICATION flag [Viresh].
- Remove redundant _begin|end() call from tegra194_cpufreq_set_target.
- Rename opp_table to freq_table [Viresh].
Sumit Gupta (4):
dt-bindings: arm: Add t194 ccplex compatible and bpmp property
arm64: tegra: Add t194 ccplex compatible and bpmp property
cpufreq: Add Tegra194 cpufreq driver
arm64: defconfig: Enable CONFIG_ARM_TEGRA194_CPUFREQ
Documentation/devicetree/bindings/arm/cpus.yaml | 9 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +
arch/arm64/configs/defconfig | 1 +
drivers/cpufreq/Kconfig.arm | 6 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra194-cpufreq.c | 403 ++++++++++++++++++++++++
6 files changed, 422 insertions(+)
create mode 100644 drivers/cpufreq/tegra194-cpufreq.c
[1] https://marc.info/?t=157539452300001&r=1&w=2
[2] https://marc.info/?l=linux-tegra&m=158602857106213&w=2
--
2.7.4
^ permalink raw reply
* [TEGRA194_CPUFREQ Patch v3 1/4] dt-bindings: arm: Add t194 ccplex compatible and bpmp property
From: Sumit Gupta @ 2020-06-21 21:34 UTC (permalink / raw)
To: rjw-LthD3rsA81gm4RdzfppkhA, viresh.kumar-QSEj5FYQhm4dnm+yROfE0A,
catalin.marinas-5wv7dgnIgG8, will-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, talho-DDmLM1+adcrQT0dZR+AlfA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: bbasu-DDmLM1+adcrQT0dZR+AlfA, sumitg-DDmLM1+adcrQT0dZR+AlfA,
mperttunen-DDmLM1+adcrQT0dZR+AlfA
In-Reply-To: <1592775274-27513-1-git-send-email-sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To do frequency scaling on all CPUs within T194 CPU Complex, we need
to query BPMP for data on valid operating points. Document a compatible
string under 'cpus' node to represent the CPU Complex for binding drivers
like cpufreq which don't have their node or CPU Complex node to bind to.
Also, document a property to point to the BPMP device that can be queried
for all CPUs.
Signed-off-by: Sumit Gupta <sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index a018147..737b55e 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -162,6 +162,7 @@ properties:
- nvidia,tegra132-denver
- nvidia,tegra186-denver
- nvidia,tegra194-carmel
+ - nvidia,tegra194-ccplex
- qcom,krait
- qcom,kryo
- qcom,kryo260
@@ -255,6 +256,14 @@ properties:
where voltage is in V, frequency is in MHz.
+ nvidia,bpmp:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ descrption: |
+ Specifies the bpmp node that needs to be queried to get
+ operating point data for all CPUs.
+
+ Optional for NVIDIA Tegra194 Carmel CPUs
+
power-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description:
--
2.7.4
^ permalink raw reply related
* [TEGRA194_CPUFREQ Patch v3 2/4] arm64: tegra: Add t194 ccplex compatible and bpmp property
From: Sumit Gupta @ 2020-06-21 21:34 UTC (permalink / raw)
To: rjw-LthD3rsA81gm4RdzfppkhA, viresh.kumar-QSEj5FYQhm4dnm+yROfE0A,
catalin.marinas-5wv7dgnIgG8, will-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, talho-DDmLM1+adcrQT0dZR+AlfA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: bbasu-DDmLM1+adcrQT0dZR+AlfA, sumitg-DDmLM1+adcrQT0dZR+AlfA,
mperttunen-DDmLM1+adcrQT0dZR+AlfA
In-Reply-To: <1592775274-27513-1-git-send-email-sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Tegra194, data on valid operating points for the CPUs needs to be
queried from BPMP. In T194, there is no node representing CPU complex.
So, add compatible string to the 'cpus' node instead of using dummy
node to bind cpufreq driver. Also, add reference to the BPMP instance
for the CPU complex.
Signed-off-by: Sumit Gupta <sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 7c9511a..0abf287 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1764,6 +1764,8 @@
};
cpus {
+ compatible = "nvidia,tegra194-ccplex";
+ nvidia,bpmp = <&bpmp>;
#address-cells = <1>;
#size-cells = <0>;
--
2.7.4
^ permalink raw reply related
* [TEGRA194_CPUFREQ Patch v3 3/4] cpufreq: Add Tegra194 cpufreq driver
From: Sumit Gupta @ 2020-06-21 21:34 UTC (permalink / raw)
To: rjw-LthD3rsA81gm4RdzfppkhA, viresh.kumar-QSEj5FYQhm4dnm+yROfE0A,
catalin.marinas-5wv7dgnIgG8, will-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, talho-DDmLM1+adcrQT0dZR+AlfA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: bbasu-DDmLM1+adcrQT0dZR+AlfA, sumitg-DDmLM1+adcrQT0dZR+AlfA,
mperttunen-DDmLM1+adcrQT0dZR+AlfA
In-Reply-To: <1592775274-27513-1-git-send-email-sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Add support for CPU frequency scaling on Tegra194. The frequency
of each core can be adjusted by writing a clock divisor value to
a MSR on the core. The range of valid divisors is queried from
the BPMP.
Signed-off-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Sumit Gupta <sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/cpufreq/Kconfig.arm | 6 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra194-cpufreq.c | 403 +++++++++++++++++++++++++++++++++++++
3 files changed, 410 insertions(+)
create mode 100644 drivers/cpufreq/tegra194-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 15c1a12..f3d8f09 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -314,6 +314,12 @@ config ARM_TEGRA186_CPUFREQ
help
This adds the CPUFreq driver support for Tegra186 SOCs.
+config ARM_TEGRA194_CPUFREQ
+ tristate "Tegra194 CPUFreq support"
+ depends on ARCH_TEGRA && TEGRA_BPMP
+ help
+ This adds CPU frequency driver support for Tegra194 SOCs.
+
config ARM_TI_CPUFREQ
bool "Texas Instruments CPUFreq support"
depends on ARCH_OMAP2PLUS
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index f6670c4..66b5563 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_ARM_TANGO_CPUFREQ) += tango-cpufreq.o
obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o
+obj-$(CONFIG_ARM_TEGRA194_CPUFREQ) += tegra194-cpufreq.o
obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o
obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c
new file mode 100644
index 0000000..8de8000
--- /dev/null
+++ b/drivers/cpufreq/tegra194-cpufreq.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved
+ */
+
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <asm/smp_plat.h>
+
+#include <soc/tegra/bpmp.h>
+#include <soc/tegra/bpmp-abi.h>
+
+#define KHZ 1000
+#define REF_CLK_MHZ 408 /* 408 MHz */
+#define US_DELAY 500
+#define US_DELAY_MIN 2
+#define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
+#define MAX_CNT ~0U
+
+/* cpufreq transisition latency */
+#define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */
+
+#define LOOP_FOR_EACH_CPU_OF_CLUSTER(cl) for (cpu = (cl * 2); \
+ cpu < ((cl + 1) * 2); cpu++)
+
+enum cluster {
+ CLUSTER0,
+ CLUSTER1,
+ CLUSTER2,
+ CLUSTER3,
+ MAX_CLUSTERS,
+};
+
+struct tegra194_cpufreq_data {
+ void __iomem *regs;
+ size_t num_clusters;
+ struct cpufreq_frequency_table **tables;
+};
+
+struct tegra_cpu_ctr {
+ u32 cpu;
+ u32 delay;
+ u32 coreclk_cnt, last_coreclk_cnt;
+ u32 refclk_cnt, last_refclk_cnt;
+};
+
+struct read_counters_work {
+ struct work_struct work;
+ struct tegra_cpu_ctr c;
+};
+
+static struct workqueue_struct *read_counters_wq;
+
+
+static enum cluster get_cpu_cluster(u8 cpu)
+{
+ return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1);
+}
+
+/*
+ * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
+ * The register provides frequency feedback information to
+ * determine the average actual frequency a core has run at over
+ * a period of time.
+ * [31:0] PLLP counter: Counts at fixed frequency (408 MHz)
+ * [63:32] Core clock counter: counts on every core clock cycle
+ * where the core is architecturally clocking
+ */
+static u64 read_freq_feedback(void)
+{
+ u64 val = 0;
+
+ asm volatile("mrs %0, s3_0_c15_c0_5" : "=r" (val) : );
+
+ return val;
+}
+
+u16 map_freq_to_ndiv(struct mrq_cpu_ndiv_limits_response *nltbl, u32 freq)
+{
+ return DIV_ROUND_UP(freq * nltbl->pdiv * nltbl->mdiv,
+ nltbl->ref_clk_hz / KHZ);
+}
+
+static inline u32 map_ndiv_to_freq(struct mrq_cpu_ndiv_limits_response
+ *nltbl, u16 ndiv)
+{
+ return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv);
+}
+
+static void tegra_read_counters(struct work_struct *work)
+{
+ struct read_counters_work *read_counters_work;
+ struct tegra_cpu_ctr *c;
+ u64 val;
+
+ /*
+ * ref_clk_counter(32 bit counter) runs on constant clk,
+ * pll_p(408MHz).
+ * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter
+ * = 10526880 usec = 10.527 sec to overflow
+ *
+ * Like wise core_clk_counter(32 bit counter) runs on core clock.
+ * It's synchronized to crab_clk (cpu_crab_clk) which runs at
+ * freq of cluster. Assuming max cluster clock ~2000MHz,
+ * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter
+ * = ~2.147 sec to overflow
+ */
+ read_counters_work = container_of(work, struct read_counters_work,
+ work);
+ c = &read_counters_work->c;
+
+ val = read_freq_feedback();
+ c->last_refclk_cnt = lower_32_bits(val);
+ c->last_coreclk_cnt = upper_32_bits(val);
+ udelay(c->delay);
+ val = read_freq_feedback();
+ c->refclk_cnt = lower_32_bits(val);
+ c->coreclk_cnt = upper_32_bits(val);
+}
+
+/*
+ * Return instantaneous cpu speed
+ * Instantaneous freq is calculated as -
+ * -Takes sample on every query of getting the freq.
+ * - Read core and ref clock counters;
+ * - Delay for X us
+ * - Read above cycle counters again
+ * - Calculates freq by subtracting current and previous counters
+ * divided by the delay time or eqv. of ref_clk_counter in delta time
+ * - Return Kcycles/second, freq in KHz
+ *
+ * delta time period = x sec
+ * = delta ref_clk_counter / (408 * 10^6) sec
+ * freq in Hz = cycles/sec
+ * = (delta cycles / x sec
+ * = (delta cycles * 408 * 10^6) / delta ref_clk_counter
+ * in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter
+ *
+ * @cpu - logical cpu whose freq to be updated
+ * Returns freq in KHz on success, 0 if cpu is offline
+ */
+static unsigned int tegra194_get_speed_common(u32 cpu, u32 delay)
+{
+ struct read_counters_work read_counters_work;
+ struct tegra_cpu_ctr c;
+ u32 delta_refcnt;
+ u32 delta_ccnt;
+ u32 rate_mhz;
+
+ /*
+ * udelay() is required to reconstruct cpu frequency over an
+ * observation window. Using workqueue to call udelay() with
+ * interrupts enabled.
+ */
+ read_counters_work.c.cpu = cpu;
+ read_counters_work.c.delay = delay;
+ INIT_WORK_ONSTACK(&read_counters_work.work, tegra_read_counters);
+ queue_work_on(cpu, read_counters_wq, &read_counters_work.work);
+ flush_work(&read_counters_work.work);
+ c = read_counters_work.c;
+
+ if (c.coreclk_cnt < c.last_coreclk_cnt)
+ delta_ccnt = c.coreclk_cnt + (MAX_CNT - c.last_coreclk_cnt);
+ else
+ delta_ccnt = c.coreclk_cnt - c.last_coreclk_cnt;
+ if (!delta_ccnt)
+ return 0;
+
+ /* ref clock is 32 bits */
+ if (c.refclk_cnt < c.last_refclk_cnt)
+ delta_refcnt = c.refclk_cnt + (MAX_CNT - c.last_refclk_cnt);
+ else
+ delta_refcnt = c.refclk_cnt - c.last_refclk_cnt;
+ if (!delta_refcnt) {
+ pr_debug("cpufreq: %d is idle, delta_refcnt: 0\n", cpu);
+ return 0;
+ }
+ rate_mhz = ((unsigned long)(delta_ccnt * REF_CLK_MHZ)) / delta_refcnt;
+
+ return (rate_mhz * KHZ); /* in KHz */
+}
+
+static unsigned int tegra194_get_speed(u32 cpu)
+{
+ return tegra194_get_speed_common(cpu, US_DELAY);
+}
+
+static unsigned int tegra194_fast_get_speed(u32 cpu)
+{
+ return tegra194_get_speed_common(cpu, US_DELAY_MIN);
+}
+
+static int tegra194_cpufreq_init(struct cpufreq_policy *policy)
+{
+ struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
+ int cl = get_cpu_cluster(policy->cpu);
+ u32 cpu;
+
+ if (cl >= data->num_clusters)
+ return -EINVAL;
+
+ policy->cur = tegra194_fast_get_speed(policy->cpu); /* boot freq */
+
+ /* set same policy for all cpus in a cluster */
+ LOOP_FOR_EACH_CPU_OF_CLUSTER(cl)
+ cpumask_set_cpu(cpu, policy->cpus);
+
+ policy->freq_table = data->tables[cl];
+ policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY;
+
+ return 0;
+}
+
+static void set_cpu_ndiv(void *data)
+{
+ struct cpufreq_frequency_table *tbl = data;
+ u64 ndiv_val = (u64)tbl->driver_data;
+
+ asm volatile("msr s3_0_c15_c0_4, %0" : : "r" (ndiv_val));
+}
+
+static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy,
+ unsigned int index)
+{
+ struct cpufreq_frequency_table *tbl = policy->freq_table + index;
+
+ on_each_cpu_mask(policy->cpus, set_cpu_ndiv, tbl, true);
+
+ return 0;
+}
+
+static struct cpufreq_driver tegra194_cpufreq_driver = {
+ .name = "tegra194",
+ .flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS |
+ CPUFREQ_NEED_INITIAL_FREQ_CHECK,
+ .verify = cpufreq_generic_frequency_table_verify,
+ .target_index = tegra194_cpufreq_set_target,
+ .get = tegra194_get_speed,
+ .init = tegra194_cpufreq_init,
+ .attr = cpufreq_generic_attr,
+};
+
+static void tegra194_cpufreq_free_resources(void)
+{
+ flush_workqueue(read_counters_wq);
+ destroy_workqueue(read_counters_wq);
+}
+
+static struct cpufreq_frequency_table *
+init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp,
+ unsigned int cluster_id)
+{
+ struct cpufreq_frequency_table *freq_table;
+ struct mrq_cpu_ndiv_limits_response resp;
+ unsigned int num_freqs, ndiv, delta_ndiv;
+ struct mrq_cpu_ndiv_limits_request req;
+ struct tegra_bpmp_message msg;
+ u16 freq_table_step_size;
+ int err, index;
+
+ memset(&req, 0, sizeof(req));
+ req.cluster_id = cluster_id;
+
+ memset(&msg, 0, sizeof(msg));
+ msg.mrq = MRQ_CPU_NDIV_LIMITS;
+ msg.tx.data = &req;
+ msg.tx.size = sizeof(req);
+ msg.rx.data = &resp;
+ msg.rx.size = sizeof(resp);
+
+ err = tegra_bpmp_transfer(bpmp, &msg);
+ if (err)
+ return ERR_PTR(err);
+
+ /*
+ * Make sure frequency table step is a multiple of mdiv to match
+ * vhint table granularity.
+ */
+ freq_table_step_size = resp.mdiv *
+ DIV_ROUND_UP(CPUFREQ_TBL_STEP_HZ, resp.ref_clk_hz);
+
+ dev_dbg(&pdev->dev, "cluster %d: frequency table step size: %d\n",
+ cluster_id, freq_table_step_size);
+
+ delta_ndiv = resp.ndiv_max - resp.ndiv_min;
+
+ if (unlikely(delta_ndiv == 0))
+ num_freqs = 1;
+ else
+ /* We store both ndiv_min and ndiv_max hence the +1 */
+ num_freqs = delta_ndiv / freq_table_step_size + 1;
+
+ num_freqs += (delta_ndiv % freq_table_step_size) ? 1 : 0;
+
+ freq_table = devm_kcalloc(&pdev->dev, num_freqs + 1,
+ sizeof(*freq_table), GFP_KERNEL);
+ if (!freq_table)
+ return ERR_PTR(-ENOMEM);
+
+ for (index = 0, ndiv = resp.ndiv_min;
+ ndiv < resp.ndiv_max;
+ index++, ndiv += freq_table_step_size) {
+ freq_table[index].driver_data = ndiv;
+ freq_table[index].frequency = map_ndiv_to_freq(&resp, ndiv);
+ }
+
+ freq_table[index].driver_data = resp.ndiv_max;
+ freq_table[index++].frequency = map_ndiv_to_freq(&resp, resp.ndiv_max);
+ freq_table[index].frequency = CPUFREQ_TABLE_END;
+
+ return freq_table;
+}
+
+static int tegra194_cpufreq_probe(struct platform_device *pdev)
+{
+ struct tegra194_cpufreq_data *data;
+ struct tegra_bpmp *bpmp;
+ int err, i;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->num_clusters = MAX_CLUSTERS;
+ data->tables = devm_kcalloc(&pdev->dev, data->num_clusters,
+ sizeof(*data->tables), GFP_KERNEL);
+ if (!data->tables)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, data);
+
+ bpmp = tegra_bpmp_get(&pdev->dev);
+ if (IS_ERR(bpmp))
+ return PTR_ERR(bpmp);
+
+ read_counters_wq = alloc_workqueue("read_counters_wq", __WQ_LEGACY, 1);
+ if (!read_counters_wq) {
+ dev_err(&pdev->dev, "fail to create_workqueue\n");
+ err = -EINVAL;
+ goto put_bpmp;
+ }
+
+ for (i = 0; i < data->num_clusters; i++) {
+ data->tables[i] = init_freq_table(pdev, bpmp, i);
+ if (IS_ERR(data->tables[i])) {
+ err = PTR_ERR(data->tables[i]);
+ goto put_bpmp;
+ }
+ }
+
+ tegra_bpmp_put(bpmp);
+
+ tegra194_cpufreq_driver.driver_data = data;
+
+ err = cpufreq_register_driver(&tegra194_cpufreq_driver);
+ if (err)
+ goto err_free_res;
+
+ return err;
+
+put_bpmp:
+ tegra_bpmp_put(bpmp);
+err_free_res:
+ tegra194_cpufreq_free_resources();
+ return err;
+}
+
+static int tegra194_cpufreq_remove(struct platform_device *pdev)
+{
+ cpufreq_unregister_driver(&tegra194_cpufreq_driver);
+ tegra194_cpufreq_free_resources();
+
+ return 0;
+}
+
+static const struct of_device_id tegra194_cpufreq_of_match[] = {
+ { .compatible = "nvidia,tegra194-ccplex", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, tegra194_cpufreq_of_match);
+
+static struct platform_driver tegra194_ccplex_driver = {
+ .driver = {
+ .name = "tegra194-cpufreq",
+ .of_match_table = tegra194_cpufreq_of_match,
+ },
+ .probe = tegra194_cpufreq_probe,
+ .remove = tegra194_cpufreq_remove,
+};
+module_platform_driver(tegra194_ccplex_driver);
+
+MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
+MODULE_AUTHOR("Sumit Gupta <sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("NVIDIA Tegra194 cpufreq driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [TEGRA194_CPUFREQ Patch v3 4/4] arm64: defconfig: Enable CONFIG_ARM_TEGRA194_CPUFREQ
From: Sumit Gupta @ 2020-06-21 21:34 UTC (permalink / raw)
To: rjw-LthD3rsA81gm4RdzfppkhA, viresh.kumar-QSEj5FYQhm4dnm+yROfE0A,
catalin.marinas-5wv7dgnIgG8, will-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, talho-DDmLM1+adcrQT0dZR+AlfA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: bbasu-DDmLM1+adcrQT0dZR+AlfA, sumitg-DDmLM1+adcrQT0dZR+AlfA,
mperttunen-DDmLM1+adcrQT0dZR+AlfA
In-Reply-To: <1592775274-27513-1-git-send-email-sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Enable Tegra194 CPU frequency scaling support by default.
Signed-off-by: Sumit Gupta <sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f9d378d..385bd35 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -91,6 +91,7 @@ CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
CONFIG_ARM_QCOM_CPUFREQ_HW=y
CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
CONFIG_ARM_TEGRA186_CPUFREQ=y
+CONFIG_ARM_TEGRA194_CPUFREQ=y
CONFIG_QORIQ_CPUFREQ=y
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_RASPBERRYPI_FIRMWARE=y
--
2.7.4
^ permalink raw reply related
* [PATCH v1 0/2] Improve descriptions of a few simple-panels
From: Dmitry Osipenko @ 2020-06-21 22:27 UTC (permalink / raw)
To: Thierry Reding, Sam Ravnborg, Laurent Pinchart
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Hello,
This is a follow up to [1], which was already applied to drm-misc and then
Laurent Pinchart spotted some problems. This series addresses those problems.
[1] https://patchwork.ozlabs.org/project/linux-tegra/patch/20200617222703.17080-8-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org/
Dmitry Osipenko (2):
drm/panel-simple: Correct EDT ET057090DHU connector type
drm/panel-simple: Add missing BUS descriptions for some panels
drivers/gpu/drm/panel/panel-simple.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
--
2.26.0
^ permalink raw reply
* [PATCH v1 1/2] drm/panel-simple: Correct EDT ET057090DHU connector type
From: Dmitry Osipenko @ 2020-06-21 22:27 UTC (permalink / raw)
To: Thierry Reding, Sam Ravnborg, Laurent Pinchart
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200621222742.25695-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The EDT ET057090DHU panel has a DPI connector and not LVDS. This patch
corrects the panel's description.
Reported-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Fixes: 94f07917ebe8 ("drm/panel-simple: Add missing connector type for some panels")
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/gpu/drm/panel/panel-simple.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index ea6973d5cf54..87edd2bdf09a 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1588,7 +1588,7 @@ static const struct panel_desc edt_et057090dhu = {
},
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
- .connector_type = DRM_MODE_CONNECTOR_LVDS,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
};
static const struct drm_display_mode edt_etm0700g0dh6_mode = {
--
2.26.0
^ permalink raw reply related
* [PATCH v1 2/2] drm/panel-simple: Add missing BUS descriptions for some panels
From: Dmitry Osipenko @ 2020-06-21 22:27 UTC (permalink / raw)
To: Thierry Reding, Sam Ravnborg, Laurent Pinchart
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200621222742.25695-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This patch adds missing BUS fields to the display panel descriptions of
the panels which are found on NVIDIA Tegra devices:
1. AUO B101AW03
2. Chunghwa CLAA070WP03XG
3. Chunghwa CLAA101WA01A
4. Chunghwa CLAA101WB01
5. Innolux N156BGE L21
6. Samsung LTN101NT05
Suggested-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/gpu/drm/panel/panel-simple.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 87edd2bdf09a..986df9937650 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -698,6 +698,8 @@ static const struct panel_desc auo_b101aw03 = {
.width = 223,
.height = 125,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
@@ -1352,6 +1354,8 @@ static const struct panel_desc chunghwa_claa070wp03xg = {
.width = 94,
.height = 150,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
@@ -1375,6 +1379,8 @@ static const struct panel_desc chunghwa_claa101wa01a = {
.width = 220,
.height = 120,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
@@ -1398,6 +1404,8 @@ static const struct panel_desc chunghwa_claa101wb01 = {
.width = 223,
.height = 125,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
@@ -2071,6 +2079,8 @@ static const struct panel_desc innolux_n156bge_l21 = {
.width = 344,
.height = 193,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
@@ -3018,6 +3028,8 @@ static const struct panel_desc samsung_ltn101nt05 = {
.width = 223,
.height = 125,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
--
2.26.0
^ permalink raw reply related
* Re: [PATCH v1 1/2] drm/panel-simple: Correct EDT ET057090DHU connector type
From: Laurent Pinchart @ 2020-06-21 22:29 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Sam Ravnborg,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200621222742.25695-2-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Dmitry,
Thank you for the patch.
On Mon, Jun 22, 2020 at 01:27:41AM +0300, Dmitry Osipenko wrote:
> The EDT ET057090DHU panel has a DPI connector and not LVDS. This patch
> corrects the panel's description.
>
> Reported-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> Fixes: 94f07917ebe8 ("drm/panel-simple: Add missing connector type for some panels")
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> ---
> drivers/gpu/drm/panel/panel-simple.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index ea6973d5cf54..87edd2bdf09a 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -1588,7 +1588,7 @@ static const struct panel_desc edt_et057090dhu = {
> },
> .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
> - .connector_type = DRM_MODE_CONNECTOR_LVDS,
> + .connector_type = DRM_MODE_CONNECTOR_DPI,
> };
>
> static const struct drm_display_mode edt_etm0700g0dh6_mode = {
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH AUTOSEL 5.7 004/388] ASoC: tegra: tegra_wm8903: Support nvidia, headset property
From: Sasha Levin @ 2020-06-21 23:33 UTC (permalink / raw)
To: Mark Brown
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
stable-u79uwXL29TY76Z2rM5mHXA, Dmitry Osipenko,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200618143930.GI5789-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
On Thu, Jun 18, 2020 at 03:39:30PM +0100, Mark Brown wrote:
>On Thu, Jun 18, 2020 at 10:30:46AM -0400, Sasha Levin wrote:
>> On Thu, Jun 18, 2020 at 12:00:23PM +0100, Mark Brown wrote:
>> > On Wed, Jun 17, 2020 at 09:01:41PM -0400, Sasha Levin wrote:
>> > > From: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> > >
>> > > [ Upstream commit 3ef9d5073b552d56bd6daf2af1e89b7e8d4df183 ]
>> > >
>> > > The microphone-jack state needs to be masked in a case of a 4-pin jack
>> > > when microphone and ground pins are shorted. Presence of nvidia,headset
>> > > tells that WM8903 CODEC driver should mask microphone's status if short
>> > > circuit is detected, i.e headphones are inserted.
>
>> > This is a new feature not a bugfix.
>
>> I saw this patch more as a hardware quirk.
>
>Pretty much any DT property is a hardware quirk :(
Which is why we're taking most of them :)
--
Thanks,
Sasha
^ permalink raw reply
* Re: [TEGRA194_CPUFREQ Patch v3 3/4] cpufreq: Add Tegra194 cpufreq driver
From: Viresh Kumar @ 2020-06-22 7:20 UTC (permalink / raw)
To: Sumit Gupta
Cc: rjw-LthD3rsA81gm4RdzfppkhA, catalin.marinas-5wv7dgnIgG8,
will-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, talho-DDmLM1+adcrQT0dZR+AlfA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, bbasu-DDmLM1+adcrQT0dZR+AlfA,
mperttunen-DDmLM1+adcrQT0dZR+AlfA
In-Reply-To: <1592775274-27513-4-git-send-email-sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 22-06-20, 03:04, Sumit Gupta wrote:
> diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c
> new file mode 100644
> index 0000000..8de8000
> --- /dev/null
> +++ b/drivers/cpufreq/tegra194-cpufreq.c
> @@ -0,0 +1,403 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved
2020
> + */
> +
> +#include <linux/cpu.h>
> +#include <linux/cpufreq.h>
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <asm/smp_plat.h>
> +
> +#include <soc/tegra/bpmp.h>
> +#include <soc/tegra/bpmp-abi.h>
> +
> +#define KHZ 1000
> +#define REF_CLK_MHZ 408 /* 408 MHz */
> +#define US_DELAY 500
> +#define US_DELAY_MIN 2
> +#define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
> +#define MAX_CNT ~0U
> +
> +/* cpufreq transisition latency */
> +#define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */
> +
> +#define LOOP_FOR_EACH_CPU_OF_CLUSTER(cl) for (cpu = (cl * 2); \
> + cpu < ((cl + 1) * 2); cpu++)
Both latency and this loop are used only once in the code, maybe just open code
it. Also you should have passed cpu as a parameter to the macro, even if it
works fine without it, for better readability.
> +
> +u16 map_freq_to_ndiv(struct mrq_cpu_ndiv_limits_response *nltbl, u32 freq)
Unused routine
> +{
> + return DIV_ROUND_UP(freq * nltbl->pdiv * nltbl->mdiv,
> + nltbl->ref_clk_hz / KHZ);
> +}
> +static int tegra194_cpufreq_init(struct cpufreq_policy *policy)
> +{
> + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
> + int cl = get_cpu_cluster(policy->cpu);
> + u32 cpu;
> +
> + if (cl >= data->num_clusters)
> + return -EINVAL;
> +
> + policy->cur = tegra194_fast_get_speed(policy->cpu); /* boot freq */
> +
> + /* set same policy for all cpus in a cluster */
> + LOOP_FOR_EACH_CPU_OF_CLUSTER(cl)
> + cpumask_set_cpu(cpu, policy->cpus);
> +
> + policy->freq_table = data->tables[cl];
> + policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY;
> +
> + return 0;
> +}
> +static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy,
> + unsigned int index)
> +{
> + struct cpufreq_frequency_table *tbl = policy->freq_table + index;
> +
> + on_each_cpu_mask(policy->cpus, set_cpu_ndiv, tbl, true);
I am still a bit confused. While setting the frequency you are calling this
routine for each CPU of the policy (cluster). Does that mean that CPUs within a
cluster can actually run at different frequencies at any given point of time ?
If cpufreq terms, a cpufreq policy represents a group of CPUs that change
frequency together, i.e. they share the clk line. If all CPUs in your system can
do DVFS separately, then you must have policy per CPU, instead of cluster.
> +static void tegra194_cpufreq_free_resources(void)
> +{
> + flush_workqueue(read_counters_wq);
Why is this required exactly? I see that you add the work request and
immediately flush it, then why would you need to do this separately ?
> + destroy_workqueue(read_counters_wq);
> +}
> +
> +static struct cpufreq_frequency_table *
> +init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp,
> + unsigned int cluster_id)
> +{
> + struct cpufreq_frequency_table *freq_table;
> + struct mrq_cpu_ndiv_limits_response resp;
> + unsigned int num_freqs, ndiv, delta_ndiv;
> + struct mrq_cpu_ndiv_limits_request req;
> + struct tegra_bpmp_message msg;
> + u16 freq_table_step_size;
> + int err, index;
> +
> + memset(&req, 0, sizeof(req));
> + req.cluster_id = cluster_id;
> +
> + memset(&msg, 0, sizeof(msg));
> + msg.mrq = MRQ_CPU_NDIV_LIMITS;
> + msg.tx.data = &req;
> + msg.tx.size = sizeof(req);
> + msg.rx.data = &resp;
> + msg.rx.size = sizeof(resp);
> +
> + err = tegra_bpmp_transfer(bpmp, &msg);
So the firmware can actually return different frequency tables for the clusters,
right ? Else you could have received the table only once and used it for all the
CPUs.
> + if (err)
> + return ERR_PTR(err);
> +
> + /*
> + * Make sure frequency table step is a multiple of mdiv to match
> + * vhint table granularity.
> + */
> + freq_table_step_size = resp.mdiv *
> + DIV_ROUND_UP(CPUFREQ_TBL_STEP_HZ, resp.ref_clk_hz);
> +
> + dev_dbg(&pdev->dev, "cluster %d: frequency table step size: %d\n",
> + cluster_id, freq_table_step_size);
> +
> + delta_ndiv = resp.ndiv_max - resp.ndiv_min;
> +
> + if (unlikely(delta_ndiv == 0))
> + num_freqs = 1;
> + else
> + /* We store both ndiv_min and ndiv_max hence the +1 */
> + num_freqs = delta_ndiv / freq_table_step_size + 1;
> +
> + num_freqs += (delta_ndiv % freq_table_step_size) ? 1 : 0;
> +
> + freq_table = devm_kcalloc(&pdev->dev, num_freqs + 1,
> + sizeof(*freq_table), GFP_KERNEL);
> + if (!freq_table)
> + return ERR_PTR(-ENOMEM);
> +
> + for (index = 0, ndiv = resp.ndiv_min;
> + ndiv < resp.ndiv_max;
> + index++, ndiv += freq_table_step_size) {
> + freq_table[index].driver_data = ndiv;
> + freq_table[index].frequency = map_ndiv_to_freq(&resp, ndiv);
> + }
> +
> + freq_table[index].driver_data = resp.ndiv_max;
> + freq_table[index++].frequency = map_ndiv_to_freq(&resp, resp.ndiv_max);
> + freq_table[index].frequency = CPUFREQ_TABLE_END;
> +
> + return freq_table;
> +}
--
viresh
^ permalink raw reply
* Re: [TEGRA194_CPUFREQ Patch v3 1/4] dt-bindings: arm: Add t194 ccplex compatible and bpmp property
From: Viresh Kumar @ 2020-06-22 7:22 UTC (permalink / raw)
To: Sumit Gupta
Cc: rjw-LthD3rsA81gm4RdzfppkhA, catalin.marinas-5wv7dgnIgG8,
will-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, talho-DDmLM1+adcrQT0dZR+AlfA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, bbasu-DDmLM1+adcrQT0dZR+AlfA,
mperttunen-DDmLM1+adcrQT0dZR+AlfA
In-Reply-To: <1592775274-27513-2-git-send-email-sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 22-06-20, 03:04, Sumit Gupta wrote:
> To do frequency scaling on all CPUs within T194 CPU Complex, we need
> to query BPMP for data on valid operating points. Document a compatible
> string under 'cpus' node to represent the CPU Complex for binding drivers
> like cpufreq which don't have their node or CPU Complex node to bind to.
> Also, document a property to point to the BPMP device that can be queried
> for all CPUs.
You shouldn't be putting how linux is going to use this information and entries
shouldn't be made just so cpufreq can bind to a driver.
Though I see that this is a real hardware register which you can use to interact
with the firmware ? And so it makes sense to have it, maybe in different form
though.
I will let Rob explain what would be the right way of doing this though.
>
> Signed-off-by: Sumit Gupta <sumitg-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index a018147..737b55e 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -162,6 +162,7 @@ properties:
> - nvidia,tegra132-denver
> - nvidia,tegra186-denver
> - nvidia,tegra194-carmel
> + - nvidia,tegra194-ccplex
> - qcom,krait
> - qcom,kryo
> - qcom,kryo260
> @@ -255,6 +256,14 @@ properties:
>
> where voltage is in V, frequency is in MHz.
>
> + nvidia,bpmp:
> + $ref: '/schemas/types.yaml#/definitions/phandle'
> + descrption: |
> + Specifies the bpmp node that needs to be queried to get
> + operating point data for all CPUs.
> +
> + Optional for NVIDIA Tegra194 Carmel CPUs
> +
> power-domains:
> $ref: '/schemas/types.yaml#/definitions/phandle-array'
> description:
> --
> 2.7.4
--
viresh
^ permalink raw reply
* Re: AMD IOMMU + SME + amdgpu regression
From: Joerg Roedel @ 2020-06-22 10:02 UTC (permalink / raw)
To: Alex Xu (Hello71)
Cc: Heiko Stuebner, Bjorn Andersson, linux-tegra, Thierry Reding,
Daniel Drake, Will Deacon, Christoph Hellwig, Marek Szyprowski,
Jean-Philippe Brucker, linux-samsung-soc, Joerg Roedel,
Krzysztof Kozlowski, Jonathan Hunter, linux-rockchip, Kukjin Kim,
Andy Gross, David Rientjes, linux-s390, Gerald Schaefer,
linux-arm-msm, linux-mediatek, Matthias Brugger, virtualization,
jonathan.derrick
In-Reply-To: <1591915710.rakbpzst8h.none@localhost>
Hi Alex,
On Thu, Jun 11, 2020 at 07:05:21PM -0400, Alex Xu (Hello71) wrote:
> I am using an ASRock B450 Pro4 with Ryzen 1600 and ASUS RX 480. I don't
> understand this code at all, but let me know what I can do to
> troubleshoot.
Does it boot without SME enabled?
Regards,
Joerg
^ permalink raw reply
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