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Date: Tue, 10 Jun 2025 09:25:23 -0400
From: Steven Rostedt <rostedt@goodmis.org>
To: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Cc: Naresh Kamboju <naresh.kamboju@linaro.org>, open list
 <linux-kernel@vger.kernel.org>, Linux trace kernel
 <linux-trace-kernel@vger.kernel.org>, lkft-triage@lists.linaro.org, Stephen
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 Carpenter <dan.carpenter@linaro.org>, Anders Roxell
 <anders.roxell@linaro.org>, Peter Zijlstra <peterz@infradead.org>, Ingo
 Molnar <mingo@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Borislav
 Petkov <bp@alien8.de>, Dave Hansen <dave.hansen@linux.intel.com>,
 x86@kernel.org
Subject: Re: next-20250605: Test regression: qemu-x86_64-compat mode ltp
 tracing Oops int3 kernel panic
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On Tue, 10 Jun 2025 17:41:36 +0900
Masami Hiramatsu (Google) <mhiramat@kernel.org> wrote:

> SERIALIZE instruction may flash pipeline, thus the processor needs
> to reload the instruction. But it is not ensured to reload it from
> memory because SERIALIZE does not invalidate the cache.

=46rom my understanding, an IPI on a CPU is equivalent to a smp_mb() on that
CPU. There shouldn't be any need for flushing the cache.

>=20
> If that hypotheses is correct, we need to invalidate the cache
> (flush TLB) in the third step, before the do_sync_core().

I'm not sure how the TLB would be affected.

-- Steve

>=20
> Or, if it is unsure, we can just evacuate the kernel from die("int3")
> by retrying the new instruction, when the INT3 is disappeared.