From: Masami Hiramatsu (Google) <mhiramat@kernel.org>
To: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, Naresh Kamboju <naresh.kamboju@linaro.org>,
open list <linux-kernel@vger.kernel.org>,
Linux trace kernel <linux-trace-kernel@vger.kernel.org>,
lkft-triage@lists.linaro.org,
Stephen Rothwell <sfr@canb.auug.org.au>,
Arnd Bergmann <arnd@arndb.de>,
Dan Carpenter <dan.carpenter@linaro.org>,
Anders Roxell <anders.roxell@linaro.org>
Subject: Re: [RFC PATCH 2/2] x86: alternative: Invalidate the cache for updated instructions
Date: Wed, 11 Jun 2025 19:26:10 +0900 [thread overview]
Message-ID: <20250611192610.6edf9713f6ee84c26f653ea5@kernel.org> (raw)
In-Reply-To: <20250610115030.0d60da65@gandalf.local.home>
On Tue, 10 Jun 2025 11:50:30 -0400
Steven Rostedt <rostedt@goodmis.org> wrote:
> On Tue, 10 Jun 2025 23:47:48 +0900
> "Masami Hiramatsu (Google)" <mhiramat@kernel.org> wrote:
>
> > Maybe one possible scenario is to hit the int3 after the third step
> > somehow (on I-cache).
> >
> > ------
> > <CPU0> <CPU1>
> > Start smp_text_poke_batch_finish().
> > Start the third step. (remove INT3)
> > on_each_cpu(do_sync_core)
> > do_sync_core(do SERIALIZE)
> > Finish the third step.
> > Hit INT3 (from I-cache)
> > Clear text_poke_array_refs[cpu0]
> > Start smp_text_poke_int3_handler()
>
> I believe your analysis is the issue here. The commit that changed the ref
> counter from a global to per cpu didn't cause the issue, it just made the
> race window bigger.
>
Ah, OK. It seems more easier to explain. Since we use the
trap gate for #BP, it does not clear the IF automatically.
Thus there is a time window between executing INT3 on icache
(or already in the pipeline) and its handler disables
interrupts. If the IPI is received in the time window,
this bug happens.
<CPU0> <CPU1>
Start smp_text_poke_batch_finish().
Start the third step. (remove INT3)
Hit INT3 (from icache/pipeline)
on_each_cpu(do_sync_core)
----
do_sync_core(do SERIALIZE)
----
Finish the third step.
Handle #BP including CLI
Clear text_poke_array_refs[cpu0]
preparing stack
Start smp_text_poke_int3_handler()
Failed to get text_poke_array_refs[cpu0]
In this case, per-cpu text_poke_array_refs will make a time
window bigger because clearing text_poke_array_refs is faster.
If this is correct, flushing cache does not matter (it
can make the window smaller.)
One possible solution is to send IPI again which ensures the
current #BP handler exits. It can make the window small enough.
Another solution is removing WARN_ONCE() from [1/2], which
means we accept this scenario, but avoid catastrophic result.
Thank you,
--
Masami Hiramatsu (Google) <mhiramat@kernel.org>
next prev parent reply other threads:[~2025-06-11 10:26 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-05 11:42 next-20250605: Test regression: qemu-x86_64-compat mode ltp tracing Oops int3 kernel panic Naresh Kamboju
2025-06-09 13:09 ` Masami Hiramatsu
2025-06-10 8:41 ` Masami Hiramatsu
2025-06-10 13:25 ` Steven Rostedt
2025-06-10 13:20 ` Naresh Kamboju
2025-06-10 14:43 ` Masami Hiramatsu
2025-06-10 14:47 ` [RFC PATCH 1/2] x86: Retry with new instruction if INT3 is disappaered Masami Hiramatsu (Google)
2025-06-10 14:47 ` [RFC PATCH 2/2] x86: alternative: Invalidate the cache for updated instructions Masami Hiramatsu (Google)
2025-06-10 15:50 ` Steven Rostedt
2025-06-11 0:21 ` Masami Hiramatsu
2025-06-11 10:26 ` Masami Hiramatsu [this message]
2025-06-11 14:20 ` Steven Rostedt
2025-06-11 15:42 ` Steven Rostedt
2025-06-12 0:04 ` Masami Hiramatsu
2025-06-11 11:30 ` Peter Zijlstra
2025-06-12 0:17 ` Masami Hiramatsu
2025-06-12 16:24 ` Naresh Kamboju
2025-06-13 3:09 ` Masami Hiramatsu
2025-06-10 14:53 ` next-20250605: Test regression: qemu-x86_64-compat mode ltp tracing Oops int3 kernel panic Steven Rostedt
2025-06-12 13:09 ` Naresh Kamboju
2025-06-13 8:27 ` Masami Hiramatsu
2025-06-13 12:01 ` Masami Hiramatsu
2025-06-16 7:36 ` Masami Hiramatsu
2025-06-17 10:41 ` Masami Hiramatsu
2025-06-17 12:10 ` Naresh Kamboju
2025-06-17 12:25 ` Steven Rostedt
2025-06-17 12:31 ` Naresh Kamboju
2025-06-17 14:29 ` Steven Rostedt
2025-06-17 23:40 ` Masami Hiramatsu
2025-06-19 14:00 ` Steven Rostedt
2025-06-17 16:45 ` Naresh Kamboju
2025-06-17 23:05 ` Masami Hiramatsu
2025-06-17 23:32 ` Steven Rostedt
2025-06-10 0:29 ` Steven Rostedt
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