* Re: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-12 1:20 ` [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support Shawn Lin
@ 2026-01-12 6:42 ` kernel test robot
2026-01-12 7:19 ` Shawn Lin
2026-01-12 9:31 ` kernel test robot
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: kernel test robot @ 2026-01-12 6:42 UTC (permalink / raw)
To: Shawn Lin, Manivannan Sadhasivam, Bjorn Helgaas
Cc: oe-kbuild-all, linux-rockchip, linux-pci, linux-trace-kernel,
linux-doc, Steven Rostedt, Masami Hiramatsu, Shawn Lin
Hi Shawn,
kernel test robot noticed the following build errors:
[auto build test ERROR on pci/next]
[also build test ERROR on next-20260109]
[cannot apply to pci/for-linus trace/for-next mani-mhi/mhi-next linus/master v6.19-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Lin/PCI-trace-Add-PCI-controller-LTSSM-transition-tracepoint/20260112-100141
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/1768180800-63364-4-git-send-email-shawn.lin%40rock-chips.com
patch subject: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
config: loongarch-randconfig-002-20260112 (https://download.01.org/0day-ci/archive/20260112/202601121428.WVvakywZ-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260112/202601121428.WVvakywZ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601121428.WVvakywZ-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/pci/controller/dwc/pcie-dw-rockchip.c: In function 'rockchip_pcie_ltssm_trace_work':
>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:264:41: error: implicit declaration of function 'dw_pcie_ltssm_status_string' [-Wimplicit-function-declaration]
264 | dw_pcie_ltssm_status_string(state),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:264:41: error: passing argument 2 of 'trace_pcie_ltssm_state_transition' makes pointer from integer without a cast [-Wint-conversion]
264 | dw_pcie_ltssm_status_string(state),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| int
In file included from include/trace/events/pci_controller.h:9,
from drivers/pci/controller/dwc/pcie-dw-rockchip.c:26:
include/trace/events/pci_controller.h:20:52: note: expected 'const char *' but argument is of type 'int'
20 | TP_PROTO(const char *dev_name, const char *state, u32 rate),
| ~~~~~~~~~~~~^~~~~
include/linux/tracepoint.h:288:41: note: in definition of macro '__DECLARE_TRACE'
288 | static inline void trace_##name(proto) \
| ^~~~~
include/linux/tracepoint.h:494:31: note: in expansion of macro 'PARAMS'
494 | __DECLARE_TRACE(name, PARAMS(proto), PARAMS(args), \
| ^~~~~~
include/linux/tracepoint.h:632:9: note: in expansion of macro 'DECLARE_TRACE_EVENT'
632 | DECLARE_TRACE_EVENT(name, PARAMS(proto), PARAMS(args))
| ^~~~~~~~~~~~~~~~~~~
include/linux/tracepoint.h:632:35: note: in expansion of macro 'PARAMS'
632 | DECLARE_TRACE_EVENT(name, PARAMS(proto), PARAMS(args))
| ^~~~~~
include/trace/events/pci_controller.h:19:1: note: in expansion of macro 'TRACE_EVENT'
19 | TRACE_EVENT(pcie_ltssm_state_transition,
| ^~~~~~~~~~~
include/trace/events/pci_controller.h:20:9: note: in expansion of macro 'TP_PROTO'
20 | TP_PROTO(const char *dev_name, const char *state, u32 rate),
| ^~~~~~~~
vim +/dw_pcie_ltssm_status_string +264 drivers/pci/controller/dwc/pcie-dw-rockchip.c
225
226 #ifdef CONFIG_TRACING
227 static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
228 {
229 struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
230 trace_work.work);
231 struct dw_pcie *pci = &rockchip->pci;
232 enum dw_pcie_ltssm state;
233 u32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val;
234
235 for (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) {
236 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
237 rate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val);
238 l1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val);
239 val = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val);
240
241 /*
242 * Hardware Mechanism: The ring FIFO employs two tracking counters:
243 * - 'last-read-point': maintains the user's last read position
244 * - 'last-valid-point': tracks the hardware's last state update
245 *
246 * Software Handling: When two consecutive LTSSM states are identical,
247 * it indicates invalid subsequent data in the FIFO. In this case, we
248 * skip the remaining entries. The dual-counter design ensures that on
249 * the next state transition, reading can resume from the last user
250 * position.
251 */
252 if ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
253 break;
254
255 state = prev_val = val;
256 if (val == DW_PCIE_LTSSM_L1_IDLE) {
257 if (l1ss == 2)
258 state = DW_PCIE_LTSSM_L1_2;
259 else if (l1ss == 1)
260 state = DW_PCIE_LTSSM_L1_1;
261 }
262
263 trace_pcie_ltssm_state_transition(dev_name(pci->dev),
> 264 dw_pcie_ltssm_status_string(state),
265 ((rate + 1) > pci->max_link_speed) ?
266 PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
267 }
268
269 schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
270 }
271
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-12 6:42 ` kernel test robot
@ 2026-01-12 7:19 ` Shawn Lin
0 siblings, 0 replies; 11+ messages in thread
From: Shawn Lin @ 2026-01-12 7:19 UTC (permalink / raw)
To: kernel test robot, Manivannan Sadhasivam, Bjorn Helgaas
Cc: shawn.lin, oe-kbuild-all, linux-rockchip, linux-pci,
linux-trace-kernel, linux-doc, Steven Rostedt, Masami Hiramatsu
在 2026/01/12 星期一 14:42, kernel test robot 写道:
> Hi Shawn,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on pci/next]
> [also build test ERROR on next-20260109]
> [cannot apply to pci/for-linus trace/for-next mani-mhi/mhi-next linus/master v6.19-rc5]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Lin/PCI-trace-Add-PCI-controller-LTSSM-transition-tracepoint/20260112-100141
> base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
> patch link: https://lore.kernel.org/r/1768180800-63364-4-git-send-email-shawn.lin%40rock-chips.com
> patch subject: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
> config: loongarch-randconfig-002-20260112 (https://download.01.org/0day-ci/archive/20260112/202601121428.WVvakywZ-lkp@intel.com/config)
> compiler: loongarch64-linux-gcc (GCC) 15.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260112/202601121428.WVvakywZ-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202601121428.WVvakywZ-lkp@intel.com/
>
> All errors (new ones prefixed by >>):
>
> drivers/pci/controller/dwc/pcie-dw-rockchip.c: In function 'rockchip_pcie_ltssm_trace_work':
>>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:264:41: error: implicit declaration of function 'dw_pcie_ltssm_status_string' [-Wimplicit-function-declaration]
> 264 | dw_pcie_ltssm_status_string(state),
Hi lkp,
It depends on another patch mentioned in the cover letter. So the
complie error is expected right now.
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:264:41: error: passing argument 2 of 'trace_pcie_ltssm_state_transition' makes pointer from integer without a cast [-Wint-conversion]
> 264 | dw_pcie_ltssm_status_string(state),
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> | |
> | int
> In file included from include/trace/events/pci_controller.h:9,
> from drivers/pci/controller/dwc/pcie-dw-rockchip.c:26:
> include/trace/events/pci_controller.h:20:52: note: expected 'const char *' but argument is of type 'int'
> 20 | TP_PROTO(const char *dev_name, const char *state, u32 rate),
> | ~~~~~~~~~~~~^~~~~
> include/linux/tracepoint.h:288:41: note: in definition of macro '__DECLARE_TRACE'
> 288 | static inline void trace_##name(proto) \
> | ^~~~~
> include/linux/tracepoint.h:494:31: note: in expansion of macro 'PARAMS'
> 494 | __DECLARE_TRACE(name, PARAMS(proto), PARAMS(args), \
> | ^~~~~~
> include/linux/tracepoint.h:632:9: note: in expansion of macro 'DECLARE_TRACE_EVENT'
> 632 | DECLARE_TRACE_EVENT(name, PARAMS(proto), PARAMS(args))
> | ^~~~~~~~~~~~~~~~~~~
> include/linux/tracepoint.h:632:35: note: in expansion of macro 'PARAMS'
> 632 | DECLARE_TRACE_EVENT(name, PARAMS(proto), PARAMS(args))
> | ^~~~~~
> include/trace/events/pci_controller.h:19:1: note: in expansion of macro 'TRACE_EVENT'
> 19 | TRACE_EVENT(pcie_ltssm_state_transition,
> | ^~~~~~~~~~~
> include/trace/events/pci_controller.h:20:9: note: in expansion of macro 'TP_PROTO'
> 20 | TP_PROTO(const char *dev_name, const char *state, u32 rate),
> | ^~~~~~~~
>
>
> vim +/dw_pcie_ltssm_status_string +264 drivers/pci/controller/dwc/pcie-dw-rockchip.c
>
> 225
> 226 #ifdef CONFIG_TRACING
> 227 static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
> 228 {
> 229 struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
> 230 trace_work.work);
> 231 struct dw_pcie *pci = &rockchip->pci;
> 232 enum dw_pcie_ltssm state;
> 233 u32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val;
> 234
> 235 for (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) {
> 236 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
> 237 rate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val);
> 238 l1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val);
> 239 val = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val);
> 240
> 241 /*
> 242 * Hardware Mechanism: The ring FIFO employs two tracking counters:
> 243 * - 'last-read-point': maintains the user's last read position
> 244 * - 'last-valid-point': tracks the hardware's last state update
> 245 *
> 246 * Software Handling: When two consecutive LTSSM states are identical,
> 247 * it indicates invalid subsequent data in the FIFO. In this case, we
> 248 * skip the remaining entries. The dual-counter design ensures that on
> 249 * the next state transition, reading can resume from the last user
> 250 * position.
> 251 */
> 252 if ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
> 253 break;
> 254
> 255 state = prev_val = val;
> 256 if (val == DW_PCIE_LTSSM_L1_IDLE) {
> 257 if (l1ss == 2)
> 258 state = DW_PCIE_LTSSM_L1_2;
> 259 else if (l1ss == 1)
> 260 state = DW_PCIE_LTSSM_L1_1;
> 261 }
> 262
> 263 trace_pcie_ltssm_state_transition(dev_name(pci->dev),
> > 264 dw_pcie_ltssm_status_string(state),
> 265 ((rate + 1) > pci->max_link_speed) ?
> 266 PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
> 267 }
> 268
> 269 schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
> 270 }
> 271
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-12 1:20 ` [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support Shawn Lin
2026-01-12 6:42 ` kernel test robot
@ 2026-01-12 9:31 ` kernel test robot
2026-01-12 10:15 ` kernel test robot
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: kernel test robot @ 2026-01-12 9:31 UTC (permalink / raw)
To: Shawn Lin, Manivannan Sadhasivam, Bjorn Helgaas
Cc: oe-kbuild-all, linux-rockchip, linux-pci, linux-trace-kernel,
linux-doc, Steven Rostedt, Masami Hiramatsu, Shawn Lin
Hi Shawn,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on next-20260109]
[cannot apply to pci/for-linus trace/for-next mani-mhi/mhi-next linus/master v6.19-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Lin/PCI-trace-Add-PCI-controller-LTSSM-transition-tracepoint/20260112-100141
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/1768180800-63364-4-git-send-email-shawn.lin%40rock-chips.com
patch subject: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
config: arm64-randconfig-002-20260112 (https://download.01.org/0day-ci/archive/20260112/202601121734.epct0ieX-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260112/202601121734.epct0ieX-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601121734.epct0ieX-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/pci/controller/dwc/pcie-dw-rockchip.c: In function 'rockchip_pcie_ltssm_trace_work':
drivers/pci/controller/dwc/pcie-dw-rockchip.c:264:6: error: implicit declaration of function 'dw_pcie_ltssm_status_string'; did you mean 'dw_pcie_start_link'? [-Werror=implicit-function-declaration]
dw_pcie_ltssm_status_string(state),
^~~~~~~~~~~~~~~~~~~~~~~~~~~
dw_pcie_start_link
>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:264:6: warning: passing argument 2 of 'trace_pcie_ltssm_state_transition' makes pointer from integer without a cast [-Wint-conversion]
dw_pcie_ltssm_status_string(state),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from include/trace/events/pci_controller.h:9,
from drivers/pci/controller/dwc/pcie-dw-rockchip.c:26:
include/trace/events/pci_controller.h:20:45: note: expected 'const char *' but argument is of type 'int'
TP_PROTO(const char *dev_name, const char *state, u32 rate),
~~~~~~~~~~~~^~~~~
include/linux/tracepoint.h:288:34: note: in definition of macro '__DECLARE_TRACE'
static inline void trace_##name(proto) \
^~~~~
include/linux/tracepoint.h:494:24: note: in expansion of macro 'PARAMS'
__DECLARE_TRACE(name, PARAMS(proto), PARAMS(args), \
^~~~~~
include/linux/tracepoint.h:632:2: note: in expansion of macro 'DECLARE_TRACE_EVENT'
DECLARE_TRACE_EVENT(name, PARAMS(proto), PARAMS(args))
^~~~~~~~~~~~~~~~~~~
include/linux/tracepoint.h:632:28: note: in expansion of macro 'PARAMS'
DECLARE_TRACE_EVENT(name, PARAMS(proto), PARAMS(args))
^~~~~~
include/trace/events/pci_controller.h:19:1: note: in expansion of macro 'TRACE_EVENT'
TRACE_EVENT(pcie_ltssm_state_transition,
^~~~~~~~~~~
include/trace/events/pci_controller.h:20:2: note: in expansion of macro 'TP_PROTO'
TP_PROTO(const char *dev_name, const char *state, u32 rate),
^~~~~~~~
cc1: some warnings being treated as errors
vim +/trace_pcie_ltssm_state_transition +264 drivers/pci/controller/dwc/pcie-dw-rockchip.c
225
226 #ifdef CONFIG_TRACING
227 static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
228 {
229 struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
230 trace_work.work);
231 struct dw_pcie *pci = &rockchip->pci;
232 enum dw_pcie_ltssm state;
233 u32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val;
234
235 for (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) {
236 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
237 rate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val);
238 l1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val);
239 val = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val);
240
241 /*
242 * Hardware Mechanism: The ring FIFO employs two tracking counters:
243 * - 'last-read-point': maintains the user's last read position
244 * - 'last-valid-point': tracks the hardware's last state update
245 *
246 * Software Handling: When two consecutive LTSSM states are identical,
247 * it indicates invalid subsequent data in the FIFO. In this case, we
248 * skip the remaining entries. The dual-counter design ensures that on
249 * the next state transition, reading can resume from the last user
250 * position.
251 */
252 if ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
253 break;
254
255 state = prev_val = val;
256 if (val == DW_PCIE_LTSSM_L1_IDLE) {
257 if (l1ss == 2)
258 state = DW_PCIE_LTSSM_L1_2;
259 else if (l1ss == 1)
260 state = DW_PCIE_LTSSM_L1_1;
261 }
262
263 trace_pcie_ltssm_state_transition(dev_name(pci->dev),
> 264 dw_pcie_ltssm_status_string(state),
265 ((rate + 1) > pci->max_link_speed) ?
266 PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
267 }
268
269 schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
270 }
271
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-12 1:20 ` [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support Shawn Lin
2026-01-12 6:42 ` kernel test robot
2026-01-12 9:31 ` kernel test robot
@ 2026-01-12 10:15 ` kernel test robot
2026-01-12 15:16 ` Steven Rostedt
2026-01-13 22:03 ` Bjorn Helgaas
4 siblings, 0 replies; 11+ messages in thread
From: kernel test robot @ 2026-01-12 10:15 UTC (permalink / raw)
To: Shawn Lin, Manivannan Sadhasivam, Bjorn Helgaas
Cc: llvm, oe-kbuild-all, linux-rockchip, linux-pci,
linux-trace-kernel, linux-doc, Steven Rostedt, Masami Hiramatsu,
Shawn Lin
Hi Shawn,
kernel test robot noticed the following build errors:
[auto build test ERROR on pci/next]
[also build test ERROR on next-20260109]
[cannot apply to pci/for-linus trace/for-next mani-mhi/mhi-next linus/master v6.19-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Lin/PCI-trace-Add-PCI-controller-LTSSM-transition-tracepoint/20260112-100141
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/1768180800-63364-4-git-send-email-shawn.lin%40rock-chips.com
patch subject: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
config: arm64-randconfig-004-20260112 (https://download.01.org/0day-ci/archive/20260112/202601121712.JbsMAjDZ-lkp@intel.com/config)
compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260112/202601121712.JbsMAjDZ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601121712.JbsMAjDZ-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:264:6: error: call to undeclared function 'dw_pcie_ltssm_status_string'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
264 | dw_pcie_ltssm_status_string(state),
| ^
>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:264:6: error: incompatible integer to pointer conversion passing 'int' to parameter of type 'const char *' [-Wint-conversion]
264 | dw_pcie_ltssm_status_string(state),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/trace/events/pci_controller.h:20:45: note: passing argument to parameter 'state' here
20 | TP_PROTO(const char *dev_name, const char *state, u32 rate),
| ^
2 errors generated.
vim +/dw_pcie_ltssm_status_string +264 drivers/pci/controller/dwc/pcie-dw-rockchip.c
225
226 #ifdef CONFIG_TRACING
227 static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
228 {
229 struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
230 trace_work.work);
231 struct dw_pcie *pci = &rockchip->pci;
232 enum dw_pcie_ltssm state;
233 u32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val;
234
235 for (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) {
236 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
237 rate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val);
238 l1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val);
239 val = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val);
240
241 /*
242 * Hardware Mechanism: The ring FIFO employs two tracking counters:
243 * - 'last-read-point': maintains the user's last read position
244 * - 'last-valid-point': tracks the hardware's last state update
245 *
246 * Software Handling: When two consecutive LTSSM states are identical,
247 * it indicates invalid subsequent data in the FIFO. In this case, we
248 * skip the remaining entries. The dual-counter design ensures that on
249 * the next state transition, reading can resume from the last user
250 * position.
251 */
252 if ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
253 break;
254
255 state = prev_val = val;
256 if (val == DW_PCIE_LTSSM_L1_IDLE) {
257 if (l1ss == 2)
258 state = DW_PCIE_LTSSM_L1_2;
259 else if (l1ss == 1)
260 state = DW_PCIE_LTSSM_L1_1;
261 }
262
263 trace_pcie_ltssm_state_transition(dev_name(pci->dev),
> 264 dw_pcie_ltssm_status_string(state),
265 ((rate + 1) > pci->max_link_speed) ?
266 PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
267 }
268
269 schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
270 }
271
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-12 1:20 ` [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support Shawn Lin
` (2 preceding siblings ...)
2026-01-12 10:15 ` kernel test robot
@ 2026-01-12 15:16 ` Steven Rostedt
2026-01-13 3:55 ` Shawn Lin
2026-01-13 22:03 ` Bjorn Helgaas
4 siblings, 1 reply; 11+ messages in thread
From: Steven Rostedt @ 2026-01-12 15:16 UTC (permalink / raw)
To: Shawn Lin
Cc: Manivannan Sadhasivam, Bjorn Helgaas, linux-rockchip, linux-pci,
linux-trace-kernel, linux-doc, Masami Hiramatsu
On Mon, 12 Jan 2026 09:20:00 +0800
Shawn Lin <shawn.lin@rock-chips.com> wrote:
> Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
> LTSSM history. Any LTSSM change will be recorded. It's userful
> for debug purpose, for example link failure, etc.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> Changes in v3:
> - reorder variables(Mani)
> - rename loop to i; rename en to enable(Mani)
> - use FIELD_GET(Mani)
> - add comment about how the FIFO works(Mani)
>
> Changes in v2:
> - use tracepoint
>
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 104 ++++++++++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 352f513..344e0b9 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -22,6 +22,8 @@
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> +#include <linux/workqueue.h>
> +#include <trace/events/pci_controller.h>
>
> #include "../../pci.h"
> #include "pcie-designware.h"
> @@ -73,6 +75,20 @@
> #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4)
> #define PCIE_CLIENT_CDM_RASDES_TBA_L1_2 BIT(5)
>
> +/* Debug FIFO information */
> +#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
> +#define PCIE_CLIENT_DBG_EN 0xffff0007
> +#define PCIE_CLIENT_DBG_DIS 0xffff0000
> +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
> +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
> +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
> +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
> +#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
> +#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
> +#define PCIE_DBG_FIFO_RATE_MASK GENMASK(22, 20)
> +#define PCIE_DBG_FIFO_L1SUB_MASK GENMASK(10, 8)
> +#define PCIE_DBG_LTSSM_HISTORY_CNT 64
> +
> /* Hot Reset Control Register */
> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
> #define PCIE_LTSSM_APP_DLY2_EN BIT(1)
> @@ -96,6 +112,7 @@ struct rockchip_pcie {
> struct irq_domain *irq_domain;
> const struct rockchip_pcie_of_data *data;
> bool supports_clkreq;
> + struct delayed_work trace_work;
> };
>
> struct rockchip_pcie_of_data {
> @@ -206,6 +223,89 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
> return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;
> }
>
> +#ifdef CONFIG_TRACING
> +static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
> +{
> + struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
> + trace_work.work);
> + struct dw_pcie *pci = &rockchip->pci;
> + enum dw_pcie_ltssm state;
> + u32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val;
> +
> + for (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) {
> + val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
> + rate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val);
> + l1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val);
> + val = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val);
> +
> + /*
> + * Hardware Mechanism: The ring FIFO employs two tracking counters:
> + * - 'last-read-point': maintains the user's last read position
> + * - 'last-valid-point': tracks the hardware's last state update
> + *
> + * Software Handling: When two consecutive LTSSM states are identical,
> + * it indicates invalid subsequent data in the FIFO. In this case, we
> + * skip the remaining entries. The dual-counter design ensures that on
> + * the next state transition, reading can resume from the last user
> + * position.
> + */
> + if ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
> + break;
> +
> + state = prev_val = val;
> + if (val == DW_PCIE_LTSSM_L1_IDLE) {
> + if (l1ss == 2)
> + state = DW_PCIE_LTSSM_L1_2;
> + else if (l1ss == 1)
> + state = DW_PCIE_LTSSM_L1_1;
> + }
> +
> + trace_pcie_ltssm_state_transition(dev_name(pci->dev),
> + dw_pcie_ltssm_status_string(state),
> + ((rate + 1) > pci->max_link_speed) ?
> + PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
> + }
Does it make sense to call this work function every 5 seconds when the
tracepoint isn't enabled?
You can add a function callback to when the tracepoint is enabled by defining:
TRACE_EVENT_FN(<name>
TP_PROTO(..)
TP_ARGS(..)
TP_STRUCT__entry(..)
TP_fast_assign(..)
TP_printk(..)
reg,
unreg)
reg() gets called when the tracepoint is first enabled. This could be where
you can start the work function. And unreg() would stop it.
You would likely need to also include state variables as I guess you don't
want to start it if the link is down. Also, if the tracepoint is enabled
when the link goes up you want to start the work queue.
I would recommend this so that you don't call this work function when it's
not doing anything useful.
-- Steve
> +
> + schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
> +}
> +
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-12 15:16 ` Steven Rostedt
@ 2026-01-13 3:55 ` Shawn Lin
0 siblings, 0 replies; 11+ messages in thread
From: Shawn Lin @ 2026-01-13 3:55 UTC (permalink / raw)
To: Steven Rostedt
Cc: shawn.lin, Manivannan Sadhasivam, Bjorn Helgaas, linux-rockchip,
linux-pci, linux-trace-kernel, linux-doc, Masami Hiramatsu
Hi Steven,
在 2026/01/12 星期一 23:16, Steven Rostedt 写道:
> On Mon, 12 Jan 2026 09:20:00 +0800
> Shawn Lin <shawn.lin@rock-chips.com> wrote:
>
>> Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
>> LTSSM history. Any LTSSM change will be recorded. It's userful
>> for debug purpose, for example link failure, etc.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> ---
>>
>> Changes in v3:
>> - reorder variables(Mani)
>> - rename loop to i; rename en to enable(Mani)
>> - use FIELD_GET(Mani)
>> - add comment about how the FIFO works(Mani)
>>
>> Changes in v2:
>> - use tracepoint
>>
>> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 104 ++++++++++++++++++++++++++
>> 1 file changed, 104 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> index 352f513..344e0b9 100644
>> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> @@ -22,6 +22,8 @@
>> #include <linux/platform_device.h>
>> #include <linux/regmap.h>
>> #include <linux/reset.h>
>> +#include <linux/workqueue.h>
>> +#include <trace/events/pci_controller.h>
>>
>> #include "../../pci.h"
>> #include "pcie-designware.h"
>> @@ -73,6 +75,20 @@
>> #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4)
>> #define PCIE_CLIENT_CDM_RASDES_TBA_L1_2 BIT(5)
>>
>> +/* Debug FIFO information */
>> +#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
>> +#define PCIE_CLIENT_DBG_EN 0xffff0007
>> +#define PCIE_CLIENT_DBG_DIS 0xffff0000
>> +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
>> +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
>> +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
>> +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
>> +#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
>> +#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
>> +#define PCIE_DBG_FIFO_RATE_MASK GENMASK(22, 20)
>> +#define PCIE_DBG_FIFO_L1SUB_MASK GENMASK(10, 8)
>> +#define PCIE_DBG_LTSSM_HISTORY_CNT 64
>> +
>> /* Hot Reset Control Register */
>> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
>> #define PCIE_LTSSM_APP_DLY2_EN BIT(1)
>> @@ -96,6 +112,7 @@ struct rockchip_pcie {
>> struct irq_domain *irq_domain;
>> const struct rockchip_pcie_of_data *data;
>> bool supports_clkreq;
>> + struct delayed_work trace_work;
>> };
>>
>> struct rockchip_pcie_of_data {
>> @@ -206,6 +223,89 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
>> return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;
>> }
>>
>> +#ifdef CONFIG_TRACING
>> +static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
>> +{
>> + struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
>> + trace_work.work);
>> + struct dw_pcie *pci = &rockchip->pci;
>> + enum dw_pcie_ltssm state;
>> + u32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val;
>> +
>> + for (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) {
>> + val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
>> + rate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val);
>> + l1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val);
>> + val = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val);
>> +
>> + /*
>> + * Hardware Mechanism: The ring FIFO employs two tracking counters:
>> + * - 'last-read-point': maintains the user's last read position
>> + * - 'last-valid-point': tracks the hardware's last state update
>> + *
>> + * Software Handling: When two consecutive LTSSM states are identical,
>> + * it indicates invalid subsequent data in the FIFO. In this case, we
>> + * skip the remaining entries. The dual-counter design ensures that on
>> + * the next state transition, reading can resume from the last user
>> + * position.
>> + */
>> + if ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
>> + break;
>> +
>> + state = prev_val = val;
>> + if (val == DW_PCIE_LTSSM_L1_IDLE) {
>> + if (l1ss == 2)
>> + state = DW_PCIE_LTSSM_L1_2;
>> + else if (l1ss == 1)
>> + state = DW_PCIE_LTSSM_L1_1;
>> + }
>> +
>> + trace_pcie_ltssm_state_transition(dev_name(pci->dev),
>> + dw_pcie_ltssm_status_string(state),
>> + ((rate + 1) > pci->max_link_speed) ?
>> + PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
>> + }
>
> Does it make sense to call this work function every 5 seconds when the
> tracepoint isn't enabled?
>
That's a good question. We don't need to read fifo and call
trace_pcie_ltssm_state_transition if tracepoint isn't enabled.
Will improve in v4.
> You can add a function callback to when the tracepoint is enabled by defining:
>
> TRACE_EVENT_FN(<name>
> TP_PROTO(..)
> TP_ARGS(..)
> TP_STRUCT__entry(..)
> TP_fast_assign(..)
> TP_printk(..)
>
> reg,
> unreg)
>
> reg() gets called when the tracepoint is first enabled. This could be where
> you can start the work function. And unreg() would stop it.
>
As how to start/stop it may vary from host to host, so I think we could
use reg()/unreg() to set a status to indicate whether this tracepoint is
enabled. Then the host drivers could decide how to implement trace work
based on it.
> You would likely need to also include state variables as I guess you don't
> want to start it if the link is down. Also, if the tracepoint is enabled
> when the link goes up you want to start the work queue.
Frankly, I do want to start it if the link is down as the link may come
up later and that will make us able to dump the transition in time.
>
> I would recommend this so that you don't call this work function when it's
> not doing anything useful.
Sure, very appreciate your suggestion.
Thanks.
>
> -- Steve
>
>
>
>> +
>> + schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
>> +}
>> +
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-12 1:20 ` [PATCH v3 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support Shawn Lin
` (3 preceding siblings ...)
2026-01-12 15:16 ` Steven Rostedt
@ 2026-01-13 22:03 ` Bjorn Helgaas
4 siblings, 0 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2026-01-13 22:03 UTC (permalink / raw)
To: Shawn Lin
Cc: Manivannan Sadhasivam, Bjorn Helgaas, linux-rockchip, linux-pci,
linux-trace-kernel, linux-doc, Steven Rostedt, Masami Hiramatsu
On Mon, Jan 12, 2026 at 09:20:00AM +0800, Shawn Lin wrote:
> Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
> LTSSM history. Any LTSSM change will be recorded. It's userful
> for debug purpose, for example link failure, etc.
s/userful/useful/
> + * Hardware Mechanism: The ring FIFO employs two tracking counters:
> + * - 'last-read-point': maintains the user's last read position
> + * - 'last-valid-point': tracks the hardware's last state update
> + *
> + * Software Handling: When two consecutive LTSSM states are identical,
> + * it indicates invalid subsequent data in the FIFO. In this case, we
> + * skip the remaining entries. The dual-counter design ensures that on
> + * the next state transition, reading can resume from the last user
> + * position.
Wrap this to fit in 80 columns like the rest of the file. Occasional
code lines that don't fit because of indentation or long meaningful
names are tolerable, but reading plain English text that doesn't fit
for no real reason is just annoying.
^ permalink raw reply [flat|nested] 11+ messages in thread