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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-34cf5639339sm4524609eec.18.2026.09.30.07.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 07:52:18 -0700 (PDT) From: Georgi Djakov To: andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, minchan@kernel.org, senozhatsky@chromium.org Cc: axboe@kernel.dk, rostedt@goodmis.org, mhiramat@kernel.org, mathieu.desnoyers@efficios.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-block@vger.kernel.org, linux-trace-kernel@vger.kernel.org, djakov@kernel.org Subject: [PATCH 0/6] soc: qcom: Add Qualcomm Page Compression Engine (QPaCE) driver Date: Wed, 30 Sep 2026 07:52:09 -0700 Message-Id: <20260930145215.3380977-1-georgi.djakov@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-trace-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDA1OSBTYWx0ZWRfX/ZUB5Cdu+7ms 9WWhUjKpmcUkm1YaQ/S55vqtwncvGc1k2nXhTsW6RXj6ce01KM4ABE2L5mJ4VGVZSVodzjfvNeq 84KCBJXrD3I+APjKu/K6Hkiz5U6FFD4= X-Proofpoint-GUID: C_vhAwuL4U_yLyURyloMJOMbVPj35Dpa X-Authority-Analysis: v=2.4 cv=W9GtxhWk c=1 sm=1 tr=0 ts=6abd2224 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=oM0TwoE6PClt58MffhQA:9 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDA1OSBTYWx0ZWRfX6ubgO8J/efVq 0Jspg4AQn0mPd2IJjQQPHOQMbNhdD+ArH4uoh5Yv54fhSmxGM/J1mGNzs12H22qDC7+N7mwsHFM Iy10MsaRKiHxdlUmKdixuB0WBMFicYsfY5jV6hgaQ0iBU7mPgK0+P2aleei5mU82YOtBRb8eTp6 E7wayt3plKteheSP5xYaIH6RCsKtX0redcJmmyE43sksb8AducpHKlzFB4T/w7YCpk/QmTPgJvA hYDN+8/0w3tElTXazpMphFUNsWMb4jPXTuB240zVlyGEG+YMnxj2rAjeE7icdPXQc9N1qtPEYEx Cdm1vhc2t3uyMpG6Nsvs0oB8RHT+mn1/mdZ5RSffL3VuSoPRVnQ2Sjg0pFMFvBBrtqQsu12OveF iRZzP3sCzf8dYOz1tcpI2nwqa/ifQfmbW75L8zZjl2fSXJ5ZVCSzjI+XAvkFi6Z5dTHQRwJ/0Nk vCKGJ+rVpqYtLKo7cPw== X-Proofpoint-ORIG-GUID: C_vhAwuL4U_yLyURyloMJOMbVPj35Dpa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-30_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1011 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300059 QPaCE (Qualcomm Page Compression Engine) is a hardware block found on Qualcomm SoCs that accelerates page compression and decompression for use with the zram block device. It is composed of multiple compression, decompression, and copy engines. This series uses QPaCE's "urgent" (synchronous) path, intended for low- latency single-page operations. A command is issued by writing the source and destination DMA addresses to one of several per-CPU urgent command registers with a single store; completion is then detected by polling the command's status register. The hardware also provides a ring-based (asynchronous) path for high- throughput batched compression, where transfer and event rings allow multiple descriptors to be queued and submitted with a single doorbell write, with completion signalled via an interrupt. This path is not implemented in this series. The driver integrates with zram through a new "qpace-lz4" zcomp backend. Both compression and decompression are performed by the QPaCE hardware via the urgent synchronous path: each request DMA-maps the source and destination buffers, issues a blocking hardware command, and returns the result size. The driver also integrates with the Qualcomm Last Level Cache Controller (LLCC) to activate dedicated cache slices for compression and decompression data. This is validated on next-20260929 with the following patch applied on top to allow booting completely to the serial console: https://lore.kernel.org/all/20260911-rsc_read-v2-1-98675c248278@oss.qualcomm.com/ Georgi Djakov (6): dt-bindings: soc: qcom: Add QPaCE binding soc: qcom: qpace: Add Qualcomm Page Compression Engine driver trace: qpace: Add tracepoints for QPaCE operations zram: Add QPaCE zcomp backend soc: qcom: qpace: Add LLCC slice support arm64: dts: qcom: hawi: Add QPaCE DT node .../bindings/soc/qcom/qcom,hawi-qpace.yaml | 94 ++ arch/arm64/boot/dts/qcom/hawi.dtsi | 17 + drivers/block/zram/Kconfig | 11 + drivers/block/zram/Makefile | 1 + drivers/block/zram/backend_qpace.c | 134 +++ drivers/block/zram/backend_qpace.h | 13 + drivers/block/zram/zcomp.c | 11 +- drivers/soc/qcom/Kconfig | 14 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qpace.c | 830 ++++++++++++++++++ drivers/soc/qcom/qpace_internal.h | 84 ++ include/linux/soc/qcom/llcc-qcom.h | 2 + include/linux/soc/qcom/qpace.h | 154 ++++ include/trace/events/qpace.h | 99 +++ 14 files changed, 1463 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,hawi-qpace.yaml create mode 100644 drivers/block/zram/backend_qpace.c create mode 100644 drivers/block/zram/backend_qpace.h create mode 100644 drivers/soc/qcom/qpace.c create mode 100644 drivers/soc/qcom/qpace_internal.h create mode 100644 include/linux/soc/qcom/qpace.h create mode 100644 include/trace/events/qpace.h