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Rozycki" Cc: "Masahiro Yamada" , "Nathan Chancellor" , "Nicolas Schier" , "Richard Weinberger" , "Anton Ivanov" , "Johannes Berg" , "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Dave Hansen" , x86@kernel.org, "H. Peter Anvin" , "Miguel Ojeda" , "Alex Gaynor" , "Wedson Almeida Filho" , "Boqun Feng" , "Gary Guo" , =?UTF-8?Q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Thomas Bogendoerfer" , "Steven Rostedt" , "Masami Hiramatsu" , "Mark Rutland" , "Jonathan Corbet" , "Alex Shi" , "Yanteng Si" , "Nick Desaulniers" , "Bill Wendling" , "Justin Stitt" , linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org, rust-for-linux@vger.kernel.org, "linux-mips@vger.kernel.org" , linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, llvm@lists.linux.dev Message-Id: <035ccfe5-c368-4cd9-8e0d-34e0e355cb05@app.fastmail.com> In-Reply-To: References: <20240905-mips-rust-v2-0-409d66819418@flygoat.com> <20240905-mips-rust-v2-3-409d66819418@flygoat.com> Subject: Re: [PATCH v2 3/3] rust: Enable for MIPS Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240908_190343_388628_EC714FEE X-CRM114-Status: UNSURE ( 9.37 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-um@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-um" Errors-To: linux-um-bounces+linux-um=archiver.kernel.org@lists.infradead.org =E5=9C=A82024=E5=B9=B49=E6=9C=888=E6=97=A5=E4=B9=9D=E6=9C=88 =E4=B8=8B=E5= =8D=889:43=EF=BC=8CMaciej W. Rozycki=E5=86=99=E9=81=93=EF=BC=9A > On Thu, 5 Sep 2024, Jiaxun Yang wrote: > >> diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_= target.rs >> index 863720777313..bbdf8a4dd169 100644 >> --- a/scripts/generate_rust_target.rs >> +++ b/scripts/generate_rust_target.rs > [...] >> + } else { >> + ts.push("arch", "mips"); >> + cfg.get("TARGET_ISA_REV").map(|isa_rev| { >> + let feature =3D match isa_rev.as_str() { >> + "1" =3D> ",+mips32", >> + "2" =3D> ",+mips32r2", >> + "5" =3D> ",+mips32r5", >> + "6" =3D> ",+mips32r6", >> + _ =3D> ",+mips2", > > What's the consequence of using `mips2' rather than `mips1' here? Ho= w=20 > about other ISA revisions, e.g. `mips4' (that also applies to the 64BI= T=20 > leg)? LLVM's mips1 backend is a little bit broken beyond repair, so I tried to= use mips2 as a baseline. I should probably let HAVE_RUST depend on !CPU_R3000 to g= et it covered. We have no good way to tell ISA reversion prior to R1 just from Kconfig = TARGET_ISA_REV, valid numbers for TARGET_ISA_REV are only 1, 2, 5, 6 from Kconfig. Given that mips 2 and 3 binaries (Rust object files) can link run flawle= ssly on all pre-R6 (despite R3000) hardware with matching bitness, they were chosen as fall= back here. Thanks > > Maciej --=20 - Jiaxun