* [PATCH v2 1/3] rust: Introduce HAVE_GENERATE_RUST_TARGET config option
2024-09-05 13:33 [PATCH v2 0/3] rust: Initial MIPS support Jiaxun Yang
@ 2024-09-05 13:33 ` Jiaxun Yang
2024-09-09 15:28 ` Gary Guo
2024-09-05 13:33 ` [PATCH v2 2/3] MIPS: Rename mips_instruction type to workaround bindgen issue Jiaxun Yang
2024-09-05 13:33 ` [PATCH v2 3/3] rust: Enable for MIPS Jiaxun Yang
2 siblings, 1 reply; 11+ messages in thread
From: Jiaxun Yang @ 2024-09-05 13:33 UTC (permalink / raw)
To: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt
Cc: linux-kbuild, linux-kernel, linux-um, rust-for-linux, linux-mips,
linux-trace-kernel, linux-doc, llvm, Jiaxun Yang
scripts/generate_rust_target.rs is used by several architectures
to generate target.json target spec file.
However the enablement of this feature was controlled by target
specific Makefile pieces spreading everywhere.
Introduce HAVE_GENERATE_RUST_TARGET config option as a centralized
switch to control the per-arch usage of generate_rust_target.rs.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2:
- Reword Kconfig help
- Remove x86 specific condition for UM
---
Makefile | 3 +++
arch/Kconfig | 8 ++++++++
arch/um/Kconfig | 1 +
arch/x86/Makefile | 1 -
arch/x86/Makefile.um | 1 -
rust/Makefile | 2 +-
scripts/Makefile | 4 +---
7 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/Makefile b/Makefile
index 2c1db7a6f793..b183855c34ea 100644
--- a/Makefile
+++ b/Makefile
@@ -807,6 +807,9 @@ KBUILD_CFLAGS += -Os
KBUILD_RUSTFLAGS += -Copt-level=s
endif
+ifdef CONFIG_HAVE_GENERATE_RUST_TARGET
+KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json
+endif
# Always set `debug-assertions` and `overflow-checks` because their default
# depends on `opt-level` and `debug-assertions`, respectively.
KBUILD_RUSTFLAGS += -Cdebug-assertions=$(if $(CONFIG_RUST_DEBUG_ASSERTIONS),y,n)
diff --git a/arch/Kconfig b/arch/Kconfig
index 4e2eaba9e305..0865ff4796e7 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -377,6 +377,14 @@ config HAVE_RUST
This symbol should be selected by an architecture if it
supports Rust.
+config HAVE_GENERATE_RUST_TARGET
+ bool
+ depends on HAVE_RUST
+ help
+ This symbol should be selected by an architecture if it
+ needs generating Rust target.json file with
+ scripts/generate_rust_target.rs.
+
config HAVE_FUNCTION_ARG_ACCESS_API
bool
help
diff --git a/arch/um/Kconfig b/arch/um/Kconfig
index dca84fd6d00a..6b1c8ae2422d 100644
--- a/arch/um/Kconfig
+++ b/arch/um/Kconfig
@@ -32,6 +32,7 @@ config UML
select TTY # Needed for line.c
select HAVE_ARCH_VMAP_STACK
select HAVE_RUST
+ select HAVE_GENERATE_RUST_TARGET
select ARCH_HAS_UBSAN
config MMU
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index a1883a30a5d8..cbd707f88a63 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -75,7 +75,6 @@ export BITS
# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53383
#
KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx
-KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json
KBUILD_RUSTFLAGS += -Ctarget-feature=-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2
#
diff --git a/arch/x86/Makefile.um b/arch/x86/Makefile.um
index a46b1397ad01..2106a2bd152b 100644
--- a/arch/x86/Makefile.um
+++ b/arch/x86/Makefile.um
@@ -9,7 +9,6 @@ core-y += arch/x86/crypto/
#
ifeq ($(CONFIG_CC_IS_CLANG),y)
KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx
-KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json
KBUILD_RUSTFLAGS += -Ctarget-feature=-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2
endif
diff --git a/rust/Makefile b/rust/Makefile
index 99204e33f1dd..fe3640b98011 100644
--- a/rust/Makefile
+++ b/rust/Makefile
@@ -378,7 +378,7 @@ $(obj)/core.o: private rustc_objcopy = $(foreach sym,$(redirect-intrinsics),--re
$(obj)/core.o: private rustc_target_flags = $(core-cfgs)
$(obj)/core.o: $(RUST_LIB_SRC)/core/src/lib.rs FORCE
+$(call if_changed_rule,rustc_library)
-ifneq ($(or $(CONFIG_X86_64),$(CONFIG_X86_32)),)
+ifdef CONFIG_HAVE_GENERATE_RUST_TARGET
$(obj)/core.o: scripts/target.json
endif
diff --git a/scripts/Makefile b/scripts/Makefile
index dccef663ca82..33258a856a1a 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -12,13 +12,11 @@ hostprogs-always-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE) += insert-sys-cert
hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_builder
hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_gen
-ifneq ($(or $(CONFIG_X86_64),$(CONFIG_X86_32)),)
-always-$(CONFIG_RUST) += target.json
+always-$(CONFIG_HAVE_GENERATE_RUST_TARGET) += target.json
filechk_rust_target = $< < include/config/auto.conf
$(obj)/target.json: scripts/generate_rust_target include/config/auto.conf FORCE
$(call filechk,rust_target)
-endif
hostprogs += generate_rust_target
generate_rust_target-rust := y
--
2.46.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] rust: Introduce HAVE_GENERATE_RUST_TARGET config option
2024-09-05 13:33 ` [PATCH v2 1/3] rust: Introduce HAVE_GENERATE_RUST_TARGET config option Jiaxun Yang
@ 2024-09-09 15:28 ` Gary Guo
0 siblings, 0 replies; 11+ messages in thread
From: Gary Guo @ 2024-09-09 15:28 UTC (permalink / raw)
To: Jiaxun Yang
Cc: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt, linux-kbuild,
linux-kernel, linux-um, rust-for-linux, linux-mips,
linux-trace-kernel, linux-doc, llvm
On Thu, 05 Sep 2024 14:33:05 +0100
Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> scripts/generate_rust_target.rs is used by several architectures
> to generate target.json target spec file.
>
> However the enablement of this feature was controlled by target
> specific Makefile pieces spreading everywhere.
>
> Introduce HAVE_GENERATE_RUST_TARGET config option as a centralized
> switch to control the per-arch usage of generate_rust_target.rs.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> v2:
> - Reword Kconfig help
> - Remove x86 specific condition for UM
> ---
> Makefile | 3 +++
> arch/Kconfig | 8 ++++++++
> arch/um/Kconfig | 1 +
> arch/x86/Makefile | 1 -
> arch/x86/Makefile.um | 1 -
> rust/Makefile | 2 +-
> scripts/Makefile | 4 +---
> 7 files changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 2c1db7a6f793..b183855c34ea 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -807,6 +807,9 @@ KBUILD_CFLAGS += -Os
> KBUILD_RUSTFLAGS += -Copt-level=s
> endif
>
> +ifdef CONFIG_HAVE_GENERATE_RUST_TARGET
> +KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json
> +endif
> # Always set `debug-assertions` and `overflow-checks` because their default
> # depends on `opt-level` and `debug-assertions`, respectively.
> KBUILD_RUSTFLAGS += -Cdebug-assertions=$(if $(CONFIG_RUST_DEBUG_ASSERTIONS),y,n)
> diff --git a/arch/Kconfig b/arch/Kconfig
> index 4e2eaba9e305..0865ff4796e7 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -377,6 +377,14 @@ config HAVE_RUST
> This symbol should be selected by an architecture if it
> supports Rust.
>
> +config HAVE_GENERATE_RUST_TARGET
> + bool
> + depends on HAVE_RUST
> + help
> + This symbol should be selected by an architecture if it
> + needs generating Rust target.json file with
> + scripts/generate_rust_target.rs.
> +
> config HAVE_FUNCTION_ARG_ACCESS_API
> bool
> help
> diff --git a/arch/um/Kconfig b/arch/um/Kconfig
> index dca84fd6d00a..6b1c8ae2422d 100644
> --- a/arch/um/Kconfig
> +++ b/arch/um/Kconfig
> @@ -32,6 +32,7 @@ config UML
> select TTY # Needed for line.c
> select HAVE_ARCH_VMAP_STACK
> select HAVE_RUST
> + select HAVE_GENERATE_RUST_TARGET
> select ARCH_HAS_UBSAN
>
> config MMU
> diff --git a/arch/x86/Makefile b/arch/x86/Makefile
> index a1883a30a5d8..cbd707f88a63 100644
> --- a/arch/x86/Makefile
> +++ b/arch/x86/Makefile
> @@ -75,7 +75,6 @@ export BITS
> # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53383
> #
> KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx
> -KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json
> KBUILD_RUSTFLAGS += -Ctarget-feature=-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2
>
> #
> diff --git a/arch/x86/Makefile.um b/arch/x86/Makefile.um
> index a46b1397ad01..2106a2bd152b 100644
> --- a/arch/x86/Makefile.um
> +++ b/arch/x86/Makefile.um
> @@ -9,7 +9,6 @@ core-y += arch/x86/crypto/
> #
> ifeq ($(CONFIG_CC_IS_CLANG),y)
> KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx
> -KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json
> KBUILD_RUSTFLAGS += -Ctarget-feature=-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2
> endif
>
> diff --git a/rust/Makefile b/rust/Makefile
> index 99204e33f1dd..fe3640b98011 100644
> --- a/rust/Makefile
> +++ b/rust/Makefile
> @@ -378,7 +378,7 @@ $(obj)/core.o: private rustc_objcopy = $(foreach sym,$(redirect-intrinsics),--re
> $(obj)/core.o: private rustc_target_flags = $(core-cfgs)
> $(obj)/core.o: $(RUST_LIB_SRC)/core/src/lib.rs FORCE
> +$(call if_changed_rule,rustc_library)
> -ifneq ($(or $(CONFIG_X86_64),$(CONFIG_X86_32)),)
> +ifdef CONFIG_HAVE_GENERATE_RUST_TARGET
> $(obj)/core.o: scripts/target.json
> endif
>
> diff --git a/scripts/Makefile b/scripts/Makefile
> index dccef663ca82..33258a856a1a 100644
> --- a/scripts/Makefile
> +++ b/scripts/Makefile
> @@ -12,13 +12,11 @@ hostprogs-always-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE) += insert-sys-cert
> hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_builder
> hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_gen
>
> -ifneq ($(or $(CONFIG_X86_64),$(CONFIG_X86_32)),)
> -always-$(CONFIG_RUST) += target.json
> +always-$(CONFIG_HAVE_GENERATE_RUST_TARGET) += target.json
> filechk_rust_target = $< < include/config/auto.conf
>
> $(obj)/target.json: scripts/generate_rust_target include/config/auto.conf FORCE
> $(call filechk,rust_target)
> -endif
Wouldn't this change cause target.json to be built when
CONFIG_HAVE_GENERATE_RUST_TARGET is selected by arch but CONFIG_RUST is
disabled?
Best,
Gary
>
> hostprogs += generate_rust_target
> generate_rust_target-rust := y
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/3] MIPS: Rename mips_instruction type to workaround bindgen issue
2024-09-05 13:33 [PATCH v2 0/3] rust: Initial MIPS support Jiaxun Yang
2024-09-05 13:33 ` [PATCH v2 1/3] rust: Introduce HAVE_GENERATE_RUST_TARGET config option Jiaxun Yang
@ 2024-09-05 13:33 ` Jiaxun Yang
2024-09-05 13:33 ` [PATCH v2 3/3] rust: Enable for MIPS Jiaxun Yang
2 siblings, 0 replies; 11+ messages in thread
From: Jiaxun Yang @ 2024-09-05 13:33 UTC (permalink / raw)
To: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt
Cc: linux-kbuild, linux-kernel, linux-um, rust-for-linux, linux-mips,
linux-trace-kernel, linux-doc, llvm, Jiaxun Yang
We have a union and a type both named after mips_instruction,
rust bindgen is not happy with this kind of naming alias.
Given that union mips_instruction is a part of UAPI, the best
thing we can do is to rename mips_instruction type.
Rename it as mips_insn, which is not conflicting with anything
and aligned with struct name here.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2:
Reword commit messsage
---
arch/mips/include/asm/dsemul.h | 2 +-
arch/mips/include/asm/inst.h | 6 +++---
arch/mips/kernel/ftrace.c | 2 +-
arch/mips/kernel/kprobes.c | 2 +-
arch/mips/math-emu/cp1emu.c | 18 +++++++++---------
arch/mips/math-emu/dsemul.c | 8 ++++----
6 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/mips/include/asm/dsemul.h b/arch/mips/include/asm/dsemul.h
index 08bfe8fa3b40..870597d6d1ad 100644
--- a/arch/mips/include/asm/dsemul.h
+++ b/arch/mips/include/asm/dsemul.h
@@ -34,7 +34,7 @@ struct task_struct;
*
* Return: Zero on success, negative if ir is a NOP, signal number on failure.
*/
-extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
+extern int mips_dsemul(struct pt_regs *regs, mips_insn ir,
unsigned long branch_pc, unsigned long cont_pc);
/**
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 2f98ced30263..0616b8eb7401 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -71,12 +71,12 @@
#define I_FMA_FFMT_SFT 0
#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000007)
-typedef unsigned int mips_instruction;
+typedef unsigned int mips_insn;
/* microMIPS instruction decode structure. Do NOT export!!! */
struct mm_decoded_insn {
- mips_instruction insn;
- mips_instruction next_insn;
+ mips_insn insn;
+ mips_insn next_insn;
int pc_inc;
int next_pc_inc;
int micro_mips_mode;
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 8c401e42301c..153c9666a77c 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -248,7 +248,7 @@ int ftrace_disable_ftrace_graph_caller(void)
#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */
#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */
-unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long
+static long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long
old_parent_ra, unsigned long parent_ra_addr, unsigned long fp)
{
unsigned long sp, ip, tmp;
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index dc39f5b3fb83..7a1b1c3674da 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -90,7 +90,7 @@ int arch_prepare_kprobe(struct kprobe *p)
}
if (copy_from_kernel_nofault(&prev_insn, p->addr - 1,
- sizeof(mips_instruction)) == 0 &&
+ sizeof(kprobe_opcode_t)) == 0 &&
insn_has_delayslot(prev_insn)) {
pr_notice("Kprobes for branch delayslot are not supported\n");
ret = -EINVAL;
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 265bc57819df..bcd6a6f0034c 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -43,10 +43,10 @@
/* Function which emulates a floating point instruction. */
static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
- mips_instruction);
+ mips_insn);
static int fpux_emu(struct pt_regs *,
- struct mips_fpu_struct *, mips_instruction, void __user **);
+ struct mips_fpu_struct *, mips_insn, void __user **);
/* Control registers */
@@ -846,7 +846,7 @@ do { \
* Emulate a CFC1 instruction.
*/
static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
- mips_instruction ir)
+ mips_insn ir)
{
u32 fcr31 = ctx->fcr31;
u32 value = 0;
@@ -903,7 +903,7 @@ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
* Emulate a CTC1 instruction.
*/
static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
- mips_instruction ir)
+ mips_insn ir)
{
u32 fcr31 = ctx->fcr31;
u32 value;
@@ -973,7 +973,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
{
unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
unsigned int cond, cbit, bit0;
- mips_instruction ir;
+ mips_insn ir;
int likely, pc_inc;
union fpureg *fpr;
u32 __user *wva;
@@ -1461,7 +1461,7 @@ DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
- mips_instruction ir, void __user **fault_addr)
+ mips_insn ir, void __user **fault_addr)
{
unsigned int rcsr = 0; /* resulting csr */
@@ -1680,7 +1680,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
* Emulate a single COP1 arithmetic instruction.
*/
static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
- mips_instruction ir)
+ mips_insn ir)
{
int rfmt; /* resulting format */
unsigned int rcsr = 0; /* resulting csr */
@@ -2899,9 +2899,9 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
dec_insn.micro_mips_mode = 1;
} else {
if ((get_user(dec_insn.insn,
- (mips_instruction __user *) xcp->cp0_epc)) ||
+ (mips_insn __user *) xcp->cp0_epc)) ||
(get_user(dec_insn.next_insn,
- (mips_instruction __user *)(xcp->cp0_epc+4)))) {
+ (mips_insn __user *)(xcp->cp0_epc+4)))) {
MIPS_FPU_EMU_INC_STATS(errors);
return SIGBUS;
}
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index e02bd20b60a6..d4ea2cf89006 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -61,8 +61,8 @@
* couldn't already.
*/
struct emuframe {
- mips_instruction emul;
- mips_instruction badinst;
+ mips_insn emul;
+ mips_insn badinst;
};
static const int emupage_frame_count = PAGE_SIZE / sizeof(struct emuframe);
@@ -206,11 +206,11 @@ void dsemul_mm_cleanup(struct mm_struct *mm)
bitmap_free(mm_ctx->bd_emupage_allocmap);
}
-int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
+int mips_dsemul(struct pt_regs *regs, mips_insn ir,
unsigned long branch_pc, unsigned long cont_pc)
{
int isa16 = get_isa16_mode(regs->cp0_epc);
- mips_instruction break_math;
+ mips_insn break_math;
unsigned long fr_uaddr;
struct emuframe fr;
int fr_idx, ret;
--
2.46.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 3/3] rust: Enable for MIPS
2024-09-05 13:33 [PATCH v2 0/3] rust: Initial MIPS support Jiaxun Yang
2024-09-05 13:33 ` [PATCH v2 1/3] rust: Introduce HAVE_GENERATE_RUST_TARGET config option Jiaxun Yang
2024-09-05 13:33 ` [PATCH v2 2/3] MIPS: Rename mips_instruction type to workaround bindgen issue Jiaxun Yang
@ 2024-09-05 13:33 ` Jiaxun Yang
2024-09-08 20:43 ` Maciej W. Rozycki
2024-09-09 15:34 ` Gary Guo
2 siblings, 2 replies; 11+ messages in thread
From: Jiaxun Yang @ 2024-09-05 13:33 UTC (permalink / raw)
To: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt
Cc: linux-kbuild, linux-kernel, linux-um, rust-for-linux, linux-mips,
linux-trace-kernel, linux-doc, llvm, Jiaxun Yang
Enable rust for linux by implement generate_rust_target.rs
and select relevant Kconfig options.
We don't use builtin target as there is no sutiable baremetal
target for us that can cover all ISA variants supported by kernel.
Link: https://github.com/Rust-for-Linux/linux/issues/107
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2:
- Add micromips flags
- Sync issues with upstream
---
Documentation/rust/arch-support.rst | 1 +
.../translations/zh_CN/rust/arch-support.rst | 1 +
arch/mips/Kconfig | 2 +
scripts/generate_rust_target.rs | 68 ++++++++++++++++++++++
4 files changed, 72 insertions(+)
diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst
index 750ff371570a..ab6c0ae5a407 100644
--- a/Documentation/rust/arch-support.rst
+++ b/Documentation/rust/arch-support.rst
@@ -17,6 +17,7 @@ Architecture Level of support Constraints
============= ================ ==============================================
``arm64`` Maintained Little Endian only.
``loongarch`` Maintained \-
+``mips`` Maintained \-
``riscv`` Maintained ``riscv64`` only.
``um`` Maintained \-
``x86`` Maintained ``x86_64`` only.
diff --git a/Documentation/translations/zh_CN/rust/arch-support.rst b/Documentation/translations/zh_CN/rust/arch-support.rst
index abd708d48f82..1eaa6c3297ac 100644
--- a/Documentation/translations/zh_CN/rust/arch-support.rst
+++ b/Documentation/translations/zh_CN/rust/arch-support.rst
@@ -21,6 +21,7 @@
============= ================ ==============================================
``arm64`` Maintained 只有小端序
``loongarch`` Maintained \-
+``mips`` Maintained \-
``riscv`` Maintained 只有 ``riscv64``
``um`` Maintained 只有 ``x86_64``
``x86`` Maintained 只有 ``x86_64``
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 43da6d596e2b..a91f0a4fd8e9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -90,6 +90,8 @@ config MIPS
select HAVE_PERF_USER_STACK_DUMP
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_RSEQ
+ select HAVE_RUST
+ select HAVE_GENERATE_RUST_TARGET
select HAVE_SPARSE_SYSCALL_NR
select HAVE_STACKPROTECTOR
select HAVE_SYSCALL_TRACEPOINTS
diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs
index 863720777313..bbdf8a4dd169 100644
--- a/scripts/generate_rust_target.rs
+++ b/scripts/generate_rust_target.rs
@@ -141,6 +141,13 @@ fn has(&self, option: &str) -> bool {
let option = "CONFIG_".to_owned() + option;
self.0.contains_key(&option)
}
+
+ /// Returns the value of the option in the configuration.
+ /// The argument must be passed without the `CONFIG_` prefix.
+ fn get(&self, option: &str) -> Option<&String> {
+ let option = "CONFIG_".to_owned() + option;
+ self.0.get(&option)
+ }
}
fn main() {
@@ -203,6 +210,67 @@ fn main() {
ts.push("target-pointer-width", "32");
} else if cfg.has("LOONGARCH") {
panic!("loongarch uses the builtin rustc loongarch64-unknown-none-softfloat target");
+ } else if cfg.has("MIPS") {
+ let mut features = "+soft-float,+noabicalls".to_string();
+
+ if cfg.has("CPU_MICROMIPS") {
+ features += ",+micromips";
+ }
+
+ if cfg.has("64BIT") {
+ ts.push("arch", "mips64");
+ ts.push("abi", "abi64");
+ cfg.get("TARGET_ISA_REV").map(|isa_rev| {
+ let feature = match isa_rev.as_str() {
+ "1" => ",+mips64",
+ "2" => ",+mips64r2",
+ "5" => ",+mips64r5",
+ "6" => ",+mips64r6",
+ _ => ",+mips3",
+ };
+ features += feature;
+ });
+
+ ts.push("features", features);
+ if cfg.has("CPU_BIG_ENDIAN") {
+ ts.push(
+ "data-layout",
+ "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128",
+ );
+ ts.push("llvm-target", "mips64-unknown-linux-gnuabi64");
+ } else {
+ ts.push(
+ "data-layout",
+ "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128",
+ );
+ ts.push("llvm-target", "mips64el-unknown-linux-gnuabi64");
+ }
+ ts.push("target-pointer-width", "64");
+ } else {
+ ts.push("arch", "mips");
+ cfg.get("TARGET_ISA_REV").map(|isa_rev| {
+ let feature = match isa_rev.as_str() {
+ "1" => ",+mips32",
+ "2" => ",+mips32r2",
+ "5" => ",+mips32r5",
+ "6" => ",+mips32r6",
+ _ => ",+mips2",
+ };
+ features += feature;
+ });
+
+ ts.push("features", features);
+ if cfg.has("CPU_BIG_ENDIAN") {
+ ts.push("data-layout",
+ "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64");
+ ts.push("llvm-target", "mips-unknown-linux-gnu");
+ } else {
+ ts.push("data-layout",
+ "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64");
+ ts.push("llvm-target", "mipsel-unknown-linux-gnu");
+ }
+ ts.push("target-pointer-width", "32");
+ }
} else {
panic!("Unsupported architecture");
}
--
2.46.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/3] rust: Enable for MIPS
2024-09-05 13:33 ` [PATCH v2 3/3] rust: Enable for MIPS Jiaxun Yang
@ 2024-09-08 20:43 ` Maciej W. Rozycki
2024-09-09 2:01 ` Jiaxun Yang
2024-09-09 15:34 ` Gary Guo
1 sibling, 1 reply; 11+ messages in thread
From: Maciej W. Rozycki @ 2024-09-08 20:43 UTC (permalink / raw)
To: Jiaxun Yang
Cc: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt, linux-kbuild,
linux-kernel, linux-um, rust-for-linux, linux-mips,
linux-trace-kernel, linux-doc, llvm
On Thu, 5 Sep 2024, Jiaxun Yang wrote:
> diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs
> index 863720777313..bbdf8a4dd169 100644
> --- a/scripts/generate_rust_target.rs
> +++ b/scripts/generate_rust_target.rs
[...]
> + } else {
> + ts.push("arch", "mips");
> + cfg.get("TARGET_ISA_REV").map(|isa_rev| {
> + let feature = match isa_rev.as_str() {
> + "1" => ",+mips32",
> + "2" => ",+mips32r2",
> + "5" => ",+mips32r5",
> + "6" => ",+mips32r6",
> + _ => ",+mips2",
What's the consequence of using `mips2' rather than `mips1' here? How
about other ISA revisions, e.g. `mips4' (that also applies to the 64BIT
leg)?
Maciej
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/3] rust: Enable for MIPS
2024-09-08 20:43 ` Maciej W. Rozycki
@ 2024-09-09 2:01 ` Jiaxun Yang
2024-09-10 16:03 ` Maciej W. Rozycki
0 siblings, 1 reply; 11+ messages in thread
From: Jiaxun Yang @ 2024-09-09 2:01 UTC (permalink / raw)
To: Maciej W. Rozycki
Cc: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt, linux-kbuild,
linux-kernel, linux-um, rust-for-linux,
linux-mips@vger.kernel.org, linux-trace-kernel, linux-doc, llvm
在2024年9月8日九月 下午9:43，Maciej W. Rozycki写道：
> On Thu, 5 Sep 2024, Jiaxun Yang wrote:
>
>> diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs
>> index 863720777313..bbdf8a4dd169 100644
>> --- a/scripts/generate_rust_target.rs
>> +++ b/scripts/generate_rust_target.rs
> [...]
>> + } else {
>> + ts.push("arch", "mips");
>> + cfg.get("TARGET_ISA_REV").map(|isa_rev| {
>> + let feature = match isa_rev.as_str() {
>> + "1" => ",+mips32",
>> + "2" => ",+mips32r2",
>> + "5" => ",+mips32r5",
>> + "6" => ",+mips32r6",
>> + _ => ",+mips2",
>
> What's the consequence of using `mips2' rather than `mips1' here? How
> about other ISA revisions, e.g. `mips4' (that also applies to the 64BIT
> leg)?
LLVM's mips1 backend is a little bit broken beyond repair, so I tried to use mips2
as a baseline. I should probably let HAVE_RUST depend on !CPU_R3000 to get it covered.
We have no good way to tell ISA reversion prior to R1 just from Kconfig TARGET_ISA_REV,
valid numbers for TARGET_ISA_REV are only 1, 2, 5, 6 from Kconfig.
Given that mips 2 and 3 binaries (Rust object files) can link run flawlessly on all pre-R6
(despite R3000) hardware with matching bitness, they were chosen as fallback here.
Thanks
>
> Maciej
--
- Jiaxun
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/3] rust: Enable for MIPS
2024-09-09 2:01 ` Jiaxun Yang
@ 2024-09-10 16:03 ` Maciej W. Rozycki
2024-09-10 19:10 ` Jiaxun Yang
0 siblings, 1 reply; 11+ messages in thread
From: Maciej W. Rozycki @ 2024-09-10 16:03 UTC (permalink / raw)
To: Jiaxun Yang
Cc: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt, linux-kbuild,
linux-kernel, linux-um, rust-for-linux,
linux-mips@vger.kernel.org, linux-trace-kernel, linux-doc, llvm
On Mon, 9 Sep 2024, Jiaxun Yang wrote:
> >> diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs
> >> index 863720777313..bbdf8a4dd169 100644
> >> --- a/scripts/generate_rust_target.rs
> >> +++ b/scripts/generate_rust_target.rs
> > [...]
> >> + } else {
> >> + ts.push("arch", "mips");
> >> + cfg.get("TARGET_ISA_REV").map(|isa_rev| {
> >> + let feature = match isa_rev.as_str() {
> >> + "1" => ",+mips32",
> >> + "2" => ",+mips32r2",
> >> + "5" => ",+mips32r5",
> >> + "6" => ",+mips32r6",
> >> + _ => ",+mips2",
> >
> > What's the consequence of using `mips2' rather than `mips1' here? How
> > about other ISA revisions, e.g. `mips4' (that also applies to the 64BIT
> > leg)?
>
> LLVM's mips1 backend is a little bit broken beyond repair, so I tried to use mips2
> as a baseline. I should probably let HAVE_RUST depend on !CPU_R3000 to get it covered.
GCC works just fine I suppose, just as with the other language frontends,
doesn't it?
> We have no good way to tell ISA reversion prior to R1 just from Kconfig TARGET_ISA_REV,
> valid numbers for TARGET_ISA_REV are only 1, 2, 5, 6 from Kconfig.
This approach doesn't work for some MIPS architecture processor configs
anyway, e.g. what ISA revision will CPU_P5600 imply here?
However if there's a need (and previously there wasn't), then I think it
can be sorted in a straightforward way. We have just a bunch of CPU_*
settings and we can define corresponding ISA_* settings to select, e.g.
ISA_MIPS1, ISA_MIPS3, ISA_MIPS32_R1, ISA_MIPS64_R6, and so on, based on
information extracted from per-CPU_* `-march=' compilation flags from
arch/mips/Makefile (possibly combined with ISA data obtained from
GCC/binutils for said flags).
It could be a bit tedious to write, but not a big challenge really, just
mechanical work.
> Given that mips 2 and 3 binaries (Rust object files) can link run flawlessly on all pre-R6
> (despite R3000) hardware with matching bitness, they were chosen as fallback here.
I'm fine with having a MIPS1/R3000 exception for broken LLVM, but I see
no reason to disable it for GCC.
Maciej
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/3] rust: Enable for MIPS
2024-09-10 16:03 ` Maciej W. Rozycki
@ 2024-09-10 19:10 ` Jiaxun Yang
2024-09-10 22:28 ` Maciej W. Rozycki
0 siblings, 1 reply; 11+ messages in thread
From: Jiaxun Yang @ 2024-09-10 19:10 UTC (permalink / raw)
To: Maciej W. Rozycki
Cc: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt, linux-kbuild,
linux-kernel, linux-um, rust-for-linux,
linux-mips@vger.kernel.org, linux-trace-kernel, linux-doc, llvm
在2024年9月10日九月 下午5:03，Maciej W. Rozycki写道：
> On Mon, 9 Sep 2024, Jiaxun Yang wrote:
>
>> > What's the consequence of using `mips2' rather than `mips1' here? How
>> > about other ISA revisions, e.g. `mips4' (that also applies to the 64BIT
>> > leg)?
>>
>> LLVM's mips1 backend is a little bit broken beyond repair, so I tried to use mips2
>> as a baseline. I should probably let HAVE_RUST depend on !CPU_R3000 to get it covered.
>
> GCC works just fine I suppose, just as with the other language frontends,
> doesn't it?
Nah, currently we can only use rustc with LLVM backend. target.json file
we are generating here is also LLVM backend only for rustc.
gccrs is not usable for kernel yet.
>
>> We have no good way to tell ISA reversion prior to R1 just from Kconfig TARGET_ISA_REV,
>> valid numbers for TARGET_ISA_REV are only 1, 2, 5, 6 from Kconfig.
>
> This approach doesn't work for some MIPS architecture processor configs
> anyway, e.g. what ISA revision will CPU_P5600 imply here?
TARGET_ISA_REV will be set to 5 for CPU_P5600 (CPU_MIPSR5 will default to y
on CPU_P5600, and CPU_MIPSR5 sets TARGET_ISA_REV to 5).
>
> However if there's a need (and previously there wasn't), then I think it
> can be sorted in a straightforward way. We have just a bunch of CPU_*
> settings and we can define corresponding ISA_* settings to select, e.g.
> ISA_MIPS1, ISA_MIPS3, ISA_MIPS32_R1, ISA_MIPS64_R6, and so on, based on
> information extracted from per-CPU_* `-march=' compilation flags from
> arch/mips/Makefile (possibly combined with ISA data obtained from
> GCC/binutils for said flags).
>
> It could be a bit tedious to write, but not a big challenge really, just
> mechanical work.
TARGET_ISA_REV is guaranteed to be aligned with CPU's supported ISA for now,
so I see no reason to invent another set of symbols....
>
>> Given that mips 2 and 3 binaries (Rust object files) can link run flawlessly on all pre-R6
>> (despite R3000) hardware with matching bitness, they were chosen as fallback here.
>
> I'm fine with having a MIPS1/R3000 exception for broken LLVM, but I see
> no reason to disable it for GCC.
It actually reminds me that LLVM lacks R4000 and some other workarounds as well.
I shall fix those in Kconfig as well.
Thanks
>
> Maciej
--
- Jiaxun
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] rust: Enable for MIPS
2024-09-10 19:10 ` Jiaxun Yang
@ 2024-09-10 22:28 ` Maciej W. Rozycki
0 siblings, 0 replies; 11+ messages in thread
From: Maciej W. Rozycki @ 2024-09-10 22:28 UTC (permalink / raw)
To: Jiaxun Yang
Cc: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt, linux-kbuild,
linux-kernel, linux-um, rust-for-linux,
linux-mips@vger.kernel.org, linux-trace-kernel, linux-doc, llvm
On Tue, 10 Sep 2024, Jiaxun Yang wrote:
> >> We have no good way to tell ISA reversion prior to R1 just from Kconfig TARGET_ISA_REV,
> >> valid numbers for TARGET_ISA_REV are only 1, 2, 5, 6 from Kconfig.
> >
> > This approach doesn't work for some MIPS architecture processor configs
> > anyway, e.g. what ISA revision will CPU_P5600 imply here?
>
> TARGET_ISA_REV will be set to 5 for CPU_P5600 (CPU_MIPSR5 will default to y
> on CPU_P5600, and CPU_MIPSR5 sets TARGET_ISA_REV to 5).
> >
> > However if there's a need (and previously there wasn't), then I think it
> > can be sorted in a straightforward way. We have just a bunch of CPU_*
> > settings and we can define corresponding ISA_* settings to select, e.g.
> > ISA_MIPS1, ISA_MIPS3, ISA_MIPS32_R1, ISA_MIPS64_R6, and so on, based on
> > information extracted from per-CPU_* `-march=' compilation flags from
> > arch/mips/Makefile (possibly combined with ISA data obtained from
> > GCC/binutils for said flags).
> >
> > It could be a bit tedious to write, but not a big challenge really, just
> > mechanical work.
>
> TARGET_ISA_REV is guaranteed to be aligned with CPU's supported ISA for now,
> so I see no reason to invent another set of symbols....
Ah, OK then, I missed these bits, thanks for pointing them out.
So we only need to define CPU_MIPS1, CPU_MIPS3, and CPU_MIPS4 settings
(we have no support for any MIPS II CPU; there was the R6000 only at that
ISA level, exeedingly rare and unreliable) analogously to and along with
the existing CPU_MIPSR1, CPU_MIPSR2, etc., which is even simpler. They
can then be used accordingly for TARGET_ISA_REV == 0, either directly or
perhaps via an additional TARGET_LEGACY_ISA_REV setting.
Maciej
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] rust: Enable for MIPS
2024-09-05 13:33 ` [PATCH v2 3/3] rust: Enable for MIPS Jiaxun Yang
2024-09-08 20:43 ` Maciej W. Rozycki
@ 2024-09-09 15:34 ` Gary Guo
1 sibling, 0 replies; 11+ messages in thread
From: Gary Guo @ 2024-09-09 15:34 UTC (permalink / raw)
To: Jiaxun Yang
Cc: Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Richard Weinberger, Anton Ivanov, Johannes Berg, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Boqun Feng,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Thomas Bogendoerfer, Steven Rostedt, Masami Hiramatsu,
Mark Rutland, Jonathan Corbet, Alex Shi, Yanteng Si,
Nick Desaulniers, Bill Wendling, Justin Stitt, linux-kbuild,
linux-kernel, linux-um, rust-for-linux, linux-mips,
linux-trace-kernel, linux-doc, llvm
On Thu, 05 Sep 2024 14:33:07 +0100
Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> Enable rust for linux by implement generate_rust_target.rs
> and select relevant Kconfig options.
>
> We don't use builtin target as there is no sutiable baremetal
> target for us that can cover all ISA variants supported by kernel.
>
> Link: https://github.com/Rust-for-Linux/linux/issues/107
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> v2:
> - Add micromips flags
> - Sync issues with upstream
> ---
> Documentation/rust/arch-support.rst | 1 +
> .../translations/zh_CN/rust/arch-support.rst | 1 +
> arch/mips/Kconfig | 2 +
> scripts/generate_rust_target.rs | 68 ++++++++++++++++++++++
> 4 files changed, 72 insertions(+)
>
> diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst
> index 750ff371570a..ab6c0ae5a407 100644
> --- a/Documentation/rust/arch-support.rst
> +++ b/Documentation/rust/arch-support.rst
> @@ -17,6 +17,7 @@ Architecture Level of support Constraints
> ============= ================ ==============================================
> ``arm64`` Maintained Little Endian only.
> ``loongarch`` Maintained \-
> +``mips`` Maintained \-
> ``riscv`` Maintained ``riscv64`` only.
> ``um`` Maintained \-
> ``x86`` Maintained ``x86_64`` only.
> diff --git a/Documentation/translations/zh_CN/rust/arch-support.rst b/Documentation/translations/zh_CN/rust/arch-support.rst
> index abd708d48f82..1eaa6c3297ac 100644
> --- a/Documentation/translations/zh_CN/rust/arch-support.rst
> +++ b/Documentation/translations/zh_CN/rust/arch-support.rst
> @@ -21,6 +21,7 @@
> ============= ================ ==============================================
> ``arm64`` Maintained 只有小端序
> ``loongarch`` Maintained \-
> +``mips`` Maintained \-
> ``riscv`` Maintained 只有 ``riscv64``
> ``um`` Maintained 只有 ``x86_64``
> ``x86`` Maintained 只有 ``x86_64``
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 43da6d596e2b..a91f0a4fd8e9 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -90,6 +90,8 @@ config MIPS
> select HAVE_PERF_USER_STACK_DUMP
> select HAVE_REGS_AND_STACK_ACCESS_API
> select HAVE_RSEQ
> + select HAVE_RUST
> + select HAVE_GENERATE_RUST_TARGET
> select HAVE_SPARSE_SYSCALL_NR
> select HAVE_STACKPROTECTOR
> select HAVE_SYSCALL_TRACEPOINTS
> diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs
> index 863720777313..bbdf8a4dd169 100644
> --- a/scripts/generate_rust_target.rs
> +++ b/scripts/generate_rust_target.rs
> @@ -141,6 +141,13 @@ fn has(&self, option: &str) -> bool {
> let option = "CONFIG_".to_owned() + option;
> self.0.contains_key(&option)
> }
> +
> + /// Returns the value of the option in the configuration.
> + /// The argument must be passed without the `CONFIG_` prefix.
> + fn get(&self, option: &str) -> Option<&String> {
> + let option = "CONFIG_".to_owned() + option;
> + self.0.get(&option)
I know you follow the code style above, but this should be
let option = format!("CONFIG_{option}");
> + }
> }
>
> fn main() {
> @@ -203,6 +210,67 @@ fn main() {
> ts.push("target-pointer-width", "32");
> } else if cfg.has("LOONGARCH") {
> panic!("loongarch uses the builtin rustc loongarch64-unknown-none-softfloat target");
> + } else if cfg.has("MIPS") {
> + let mut features = "+soft-float,+noabicalls".to_string();
> +
> + if cfg.has("CPU_MICROMIPS") {
> + features += ",+micromips";
> + }
> +
> + if cfg.has("64BIT") {
> + ts.push("arch", "mips64");
> + ts.push("abi", "abi64");
> + cfg.get("TARGET_ISA_REV").map(|isa_rev| {
if let Some(isa_rev) = cfg.get("TARGET_ISA_REV") {
...
}
> + let feature = match isa_rev.as_str() {
> + "1" => ",+mips64",
> + "2" => ",+mips64r2",
> + "5" => ",+mips64r5",
> + "6" => ",+mips64r6",
> + _ => ",+mips3",
> + };
> + features += feature;
> + });
> +
> + ts.push("features", features);
> + if cfg.has("CPU_BIG_ENDIAN") {
> + ts.push(
> + "data-layout",
> + "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128",
> + );
> + ts.push("llvm-target", "mips64-unknown-linux-gnuabi64");
> + } else {
> + ts.push(
> + "data-layout",
> + "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128",
> + );
> + ts.push("llvm-target", "mips64el-unknown-linux-gnuabi64");
> + }
> + ts.push("target-pointer-width", "64");
> + } else {
> + ts.push("arch", "mips");
> + cfg.get("TARGET_ISA_REV").map(|isa_rev| {
ditto
> + let feature = match isa_rev.as_str() {
> + "1" => ",+mips32",
> + "2" => ",+mips32r2",
> + "5" => ",+mips32r5",
> + "6" => ",+mips32r6",
> + _ => ",+mips2",
> + };
> + features += feature;
> + });
> +
> + ts.push("features", features);
> + if cfg.has("CPU_BIG_ENDIAN") {
> + ts.push("data-layout",
> + "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64");
> + ts.push("llvm-target", "mips-unknown-linux-gnu");
> + } else {
> + ts.push("data-layout",
> + "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64");
> + ts.push("llvm-target", "mipsel-unknown-linux-gnu");
> + }
> + ts.push("target-pointer-width", "32");
> + }
> } else {
> panic!("Unsupported architecture");
> }
>
Best,
Gary
^ permalink raw reply [flat|nested] 11+ messages in thread