From: Arnd Bergmann <arnd@kernel.org>
To: Ingo Molnar <mingo@redhat.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Richard Weinberger <richard@nod.at>,
Anton Ivanov <anton.ivanov@cambridgegreys.com>,
Johannes Berg <johannes@sipsolutions.net>,
Thomas Gleixner <tglx@kernel.org>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Peter Zijlstra <peterz@infradead.org>,
Will Deacon <will@kernel.org>, Boqun Feng <boqun@kernel.org>,
Gary Guo <gary@garyguo.net>, Yury Norov <yury.norov@gmail.com>,
Rasmus Villemoes <linux@rasmusvillemoes.dk>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Alexander Usyskin <alexander.usyskin@intel.com>,
Tony Nguyen <anthony.l.nguyen@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org,
linux-um@lists.infradead.org
Subject: [PATCH 4/8] x86: make CX8 usage unconditional
Date: Fri, 22 May 2026 16:19:55 +0200 [thread overview]
Message-ID: <20260522141959.1071595-5-arnd@kernel.org> (raw)
In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org>
From: Arnd Bergmann <arnd@arndb.de>
All supported CPUs now provide the cmpxchg8b instruction, so remove
all compile-time and runtime checks for its presence and the fallback
implementation, to assume it just works.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/um/include/asm/asm-prototypes.h | 4 -
arch/x86/Kconfig.cpu | 4 -
arch/x86/Kconfig.cpufeatures | 7 +-
arch/x86/include/asm/asm-prototypes.h | 4 -
arch/x86/include/asm/atomic64_32.h | 15 --
arch/x86/include/asm/cmpxchg_32.h | 76 +---------
arch/x86/include/asm/percpu.h | 14 +-
arch/x86/lib/Makefile | 4 -
arch/x86/lib/atomic64_386_32.S | 195 --------------------------
arch/x86/lib/cmpxchg8b_emu.S | 97 -------------
arch/x86/um/Kconfig | 2 +-
arch/x86/um/Makefile | 3 +-
lib/atomic64_test.c | 7 +-
13 files changed, 13 insertions(+), 419 deletions(-)
delete mode 100644 arch/x86/lib/atomic64_386_32.S
delete mode 100644 arch/x86/lib/cmpxchg8b_emu.S
diff --git a/arch/um/include/asm/asm-prototypes.h b/arch/um/include/asm/asm-prototypes.h
index 408b31d59127..b446eec98ed8 100644
--- a/arch/um/include/asm/asm-prototypes.h
+++ b/arch/um/include/asm/asm-prototypes.h
@@ -1,6 +1,2 @@
#include <asm-generic/asm-prototypes.h>
#include <asm/checksum.h>
-
-#ifdef CONFIG_UML_X86
-extern void cmpxchg8b_emu(void);
-#endif
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index fe0246477345..65d887274dd8 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -266,10 +266,6 @@ config X86_HAVE_PAE
def_bool y
depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64
-config X86_CX8
- def_bool y
- depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 || MGEODEGX1 || MGEODE_LX
-
# this should be set for all -march=.. options where the compiler
# generates cmov.
config X86_CMOV
diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
index 89cbf8f572ae..e0f2ff65377d 100644
--- a/arch/x86/Kconfig.cpufeatures
+++ b/arch/x86/Kconfig.cpufeatures
@@ -40,10 +40,6 @@ config X86_REQUIRED_FEATURE_NOPL
def_bool y
depends on X86_64
-config X86_REQUIRED_FEATURE_CX8
- def_bool y
- depends on X86_CX8
-
# this should be set for all -march=.. options where the compiler
# generates cmov.
config X86_REQUIRED_FEATURE_CMOV
@@ -60,6 +56,9 @@ config X86_REQUIRED_FEATURE_SYSFAST32
def_bool y
depends on X86_64 && !X86_FRED
+config X86_REQUIRED_FEATURE_CX8
+ def_bool y
+
config X86_REQUIRED_FEATURE_CPUID
def_bool y
depends on X86_64
diff --git a/arch/x86/include/asm/asm-prototypes.h b/arch/x86/include/asm/asm-prototypes.h
index 11c6fecc3ad7..6ec680a36dea 100644
--- a/arch/x86/include/asm/asm-prototypes.h
+++ b/arch/x86/include/asm/asm-prototypes.h
@@ -16,10 +16,6 @@
#include <asm/gsseg.h>
#include <asm/nospec-branch.h>
-#ifndef CONFIG_X86_CX8
-extern void cmpxchg8b_emu(void);
-#endif
-
#ifdef CONFIG_STACKPROTECTOR
extern unsigned long __ref_stack_chk_guard;
#endif
diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
index ab838205c1c6..e3da5d0094c4 100644
--- a/arch/x86/include/asm/atomic64_32.h
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -48,7 +48,6 @@ static __always_inline s64 arch_atomic64_read_nonatomic(const atomic64_t *v)
ATOMIC64_EXPORT(atomic64_##sym)
#endif
-#ifdef CONFIG_X86_CX8
#define __alternative_atomic64(f, g, out, in, clobbers...) \
asm volatile("call %c[func]" \
: ALT_OUTPUT_SP(out) \
@@ -57,20 +56,6 @@ static __always_inline s64 arch_atomic64_read_nonatomic(const atomic64_t *v)
: clobbers)
#define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8)
-#else
-#define __alternative_atomic64(f, g, out, in, clobbers...) \
- alternative_call(atomic64_##f##_386, atomic64_##g##_cx8, \
- X86_FEATURE_CX8, ASM_OUTPUT(out), \
- ASM_INPUT(in), clobbers)
-
-#define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8); \
- ATOMIC64_DECL_ONE(sym##_386)
-
-ATOMIC64_DECL_ONE(add_386);
-ATOMIC64_DECL_ONE(sub_386);
-ATOMIC64_DECL_ONE(inc_386);
-ATOMIC64_DECL_ONE(dec_386);
-#endif
#define alternative_atomic64(f, out, in, clobbers...) \
__alternative_atomic64(f, f, ASM_OUTPUT(out), ASM_INPUT(in), clobbers)
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index 1f80a62be969..1019c4bce620 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -68,8 +68,6 @@ static __always_inline bool __try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp,
return __arch_try_cmpxchg64(ptr, oldp, new,);
}
-#ifdef CONFIG_X86_CX8
-
#define arch_cmpxchg64 __cmpxchg64
#define arch_cmpxchg64_local __cmpxchg64_local
@@ -78,78 +76,6 @@ static __always_inline bool __try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp,
#define arch_try_cmpxchg64_local __try_cmpxchg64_local
-#else
-
-/*
- * Building a kernel capable running on 80386 and 80486. It may be necessary
- * to simulate the cmpxchg8b on the 80386 and 80486 CPU.
- */
-
-#define __arch_cmpxchg64_emu(_ptr, _old, _new, _lock_loc, _lock) \
-({ \
- union __u64_halves o = { .full = (_old), }, \
- n = { .full = (_new), }; \
- \
- asm_inline volatile( \
- ALTERNATIVE(_lock_loc \
- "call cmpxchg8b_emu", \
- _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \
- : ALT_OUTPUT_SP("+a" (o.low), "+d" (o.high)) \
- : "b" (n.low), "c" (n.high), \
- [ptr] "S" (_ptr) \
- : "memory"); \
- \
- o.full; \
-})
-
-static __always_inline u64 arch_cmpxchg64(volatile u64 *ptr, u64 old, u64 new)
-{
- return __arch_cmpxchg64_emu(ptr, old, new, LOCK_PREFIX_HERE, "lock ");
-}
-#define arch_cmpxchg64 arch_cmpxchg64
-
-static __always_inline u64 arch_cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
-{
- return __arch_cmpxchg64_emu(ptr, old, new, ,);
-}
-#define arch_cmpxchg64_local arch_cmpxchg64_local
-
-#define __arch_try_cmpxchg64_emu(_ptr, _oldp, _new, _lock_loc, _lock) \
-({ \
- union __u64_halves o = { .full = *(_oldp), }, \
- n = { .full = (_new), }; \
- bool ret; \
- \
- asm_inline volatile( \
- ALTERNATIVE(_lock_loc \
- "call cmpxchg8b_emu", \
- _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \
- : ALT_OUTPUT_SP("=@ccz" (ret), \
- "+a" (o.low), "+d" (o.high)) \
- : "b" (n.low), "c" (n.high), \
- [ptr] "S" (_ptr) \
- : "memory"); \
- \
- if (unlikely(!ret)) \
- *(_oldp) = o.full; \
- \
- likely(ret); \
-})
-
-static __always_inline bool arch_try_cmpxchg64(volatile u64 *ptr, u64 *oldp, u64 new)
-{
- return __arch_try_cmpxchg64_emu(ptr, oldp, new, LOCK_PREFIX_HERE, "lock ");
-}
-#define arch_try_cmpxchg64 arch_try_cmpxchg64
-
-static __always_inline bool arch_try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp, u64 new)
-{
- return __arch_try_cmpxchg64_emu(ptr, oldp, new, ,);
-}
-#define arch_try_cmpxchg64_local arch_try_cmpxchg64_local
-
-#endif
-
-#define system_has_cmpxchg64() boot_cpu_has(X86_FEATURE_CX8)
+#define system_has_cmpxchg64() true
#endif /* _ASM_X86_CMPXCHG_32_H */
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index 409981468cba..6f45358cb091 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -335,11 +335,9 @@ do { \
old__.var = _oval; \
new__.var = _nval; \
\
- asm_inline qual ( \
- ALTERNATIVE("call this_cpu_cmpxchg8b_emu", \
- "cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \
- : ALT_OUTPUT_SP([var] "+m" (__my_cpu_var(_var)), \
- "+a" (old__.low), "+d" (old__.high)) \
+ asm_inline qual ("cmpxchg8b " __percpu_arg([var]) \
+ : [var] "+m" (__my_cpu_var(_var)), \
+ "+a" (old__.low), "+d" (old__.high) \
: "b" (new__.low), "c" (new__.high), \
"S" (&(_var)) \
: "memory"); \
@@ -364,10 +362,8 @@ do { \
old__.var = *_oval; \
new__.var = _nval; \
\
- asm_inline qual ( \
- ALTERNATIVE("call this_cpu_cmpxchg8b_emu", \
- "cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \
- : ALT_OUTPUT_SP("=@ccz" (success), \
+ asm_inline qual ("cmpxchg8b " __percpu_arg([var]) \
+ : "=@ccz" (success), \
[var] "+m" (__my_cpu_var(_var)), \
"+a" (old__.low), "+d" (old__.high)) \
: "b" (new__.low), "c" (new__.high), \
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 2dba7f83ef97..210af275f468 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -48,10 +48,6 @@ ifeq ($(CONFIG_X86_32),y)
lib-y += strstr_32.o
lib-y += string_32.o
lib-y += memmove_32.o
- lib-y += cmpxchg8b_emu.o
-ifneq ($(CONFIG_X86_CX8),y)
- lib-y += atomic64_386_32.o
-endif
else
ifneq ($(CONFIG_GENERIC_CSUM),y)
lib-y += csum-partial_64.o csum-copy_64.o csum-wrappers_64.o
diff --git a/arch/x86/lib/atomic64_386_32.S b/arch/x86/lib/atomic64_386_32.S
deleted file mode 100644
index e768815e58ae..000000000000
--- a/arch/x86/lib/atomic64_386_32.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * atomic64_t for 386/486
- *
- * Copyright © 2010 Luca Barbieri
- */
-
-#include <linux/linkage.h>
-#include <asm/alternative.h>
-
-/* if you want SMP support, implement these with real spinlocks */
-.macro IRQ_SAVE reg
- pushfl
- cli
-.endm
-
-.macro IRQ_RESTORE reg
- popfl
-.endm
-
-#define BEGIN_IRQ_SAVE(op) \
-.macro endp; \
-SYM_FUNC_END(atomic64_##op##_386); \
-.purgem endp; \
-.endm; \
-SYM_FUNC_START(atomic64_##op##_386); \
- IRQ_SAVE v;
-
-#define ENDP endp
-
-#define RET_IRQ_RESTORE \
- IRQ_RESTORE v; \
- RET
-
-#define v %ecx
-BEGIN_IRQ_SAVE(read)
- movl (v), %eax
- movl 4(v), %edx
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(set)
- movl %ebx, (v)
- movl %ecx, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(xchg)
- movl (v), %eax
- movl 4(v), %edx
- movl %ebx, (v)
- movl %ecx, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %ecx
-BEGIN_IRQ_SAVE(add)
- addl %eax, (v)
- adcl %edx, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %ecx
-BEGIN_IRQ_SAVE(add_return)
- addl (v), %eax
- adcl 4(v), %edx
- movl %eax, (v)
- movl %edx, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %ecx
-BEGIN_IRQ_SAVE(sub)
- subl %eax, (v)
- sbbl %edx, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %ecx
-BEGIN_IRQ_SAVE(sub_return)
- negl %edx
- negl %eax
- sbbl $0, %edx
- addl (v), %eax
- adcl 4(v), %edx
- movl %eax, (v)
- movl %edx, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(inc)
- addl $1, (v)
- adcl $0, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(inc_return)
- movl (v), %eax
- movl 4(v), %edx
- addl $1, %eax
- adcl $0, %edx
- movl %eax, (v)
- movl %edx, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(dec)
- subl $1, (v)
- sbbl $0, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(dec_return)
- movl (v), %eax
- movl 4(v), %edx
- subl $1, %eax
- sbbl $0, %edx
- movl %eax, (v)
- movl %edx, 4(v)
- RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(add_unless)
- addl %eax, %ecx
- adcl %edx, %edi
- addl (v), %eax
- adcl 4(v), %edx
- cmpl %eax, %ecx
- je 3f
-1:
- movl %eax, (v)
- movl %edx, 4(v)
- movl $1, %eax
-2:
- RET_IRQ_RESTORE
-3:
- cmpl %edx, %edi
- jne 1b
- xorl %eax, %eax
- jmp 2b
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(inc_not_zero)
- movl (v), %eax
- movl 4(v), %edx
- testl %eax, %eax
- je 3f
-1:
- addl $1, %eax
- adcl $0, %edx
- movl %eax, (v)
- movl %edx, 4(v)
- movl $1, %eax
-2:
- RET_IRQ_RESTORE
-3:
- testl %edx, %edx
- jne 1b
- jmp 2b
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(dec_if_positive)
- movl (v), %eax
- movl 4(v), %edx
- subl $1, %eax
- sbbl $0, %edx
- js 1f
- movl %eax, (v)
- movl %edx, 4(v)
-1:
- RET_IRQ_RESTORE
-ENDP
-#undef v
diff --git a/arch/x86/lib/cmpxchg8b_emu.S b/arch/x86/lib/cmpxchg8b_emu.S
deleted file mode 100644
index d4bb24347ff8..000000000000
--- a/arch/x86/lib/cmpxchg8b_emu.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <linux/export.h>
-#include <linux/linkage.h>
-#include <asm/percpu.h>
-#include <asm/processor-flags.h>
-
-.text
-
-#ifndef CONFIG_X86_CX8
-
-/*
- * Emulate 'cmpxchg8b (%esi)' on UP
- *
- * Inputs:
- * %esi : memory location to compare
- * %eax : low 32 bits of old value
- * %edx : high 32 bits of old value
- * %ebx : low 32 bits of new value
- * %ecx : high 32 bits of new value
- */
-SYM_FUNC_START(cmpxchg8b_emu)
-
- pushfl
- cli
-
- cmpl (%esi), %eax
- jne .Lnot_same
- cmpl 4(%esi), %edx
- jne .Lnot_same
-
- movl %ebx, (%esi)
- movl %ecx, 4(%esi)
-
- orl $X86_EFLAGS_ZF, (%esp)
-
- popfl
- RET
-
-.Lnot_same:
- movl (%esi), %eax
- movl 4(%esi), %edx
-
- andl $(~X86_EFLAGS_ZF), (%esp)
-
- popfl
- RET
-
-SYM_FUNC_END(cmpxchg8b_emu)
-EXPORT_SYMBOL(cmpxchg8b_emu)
-
-#endif
-
-#ifndef CONFIG_UML
-
-/*
- * Emulate 'cmpxchg8b %fs:(%rsi)'
- *
- * Inputs:
- * %esi : memory location to compare
- * %eax : low 32 bits of old value
- * %edx : high 32 bits of old value
- * %ebx : low 32 bits of new value
- * %ecx : high 32 bits of new value
- *
- * Notably this is not LOCK prefixed and is not safe against NMIs
- */
-SYM_FUNC_START(this_cpu_cmpxchg8b_emu)
-
- pushfl
- cli
-
- cmpl __percpu (%esi), %eax
- jne .Lnot_same2
- cmpl __percpu 4(%esi), %edx
- jne .Lnot_same2
-
- movl %ebx, __percpu (%esi)
- movl %ecx, __percpu 4(%esi)
-
- orl $X86_EFLAGS_ZF, (%esp)
-
- popfl
- RET
-
-.Lnot_same2:
- movl __percpu (%esi), %eax
- movl __percpu 4(%esi), %edx
-
- andl $(~X86_EFLAGS_ZF), (%esp)
-
- popfl
- RET
-
-SYM_FUNC_END(this_cpu_cmpxchg8b_emu)
-
-#endif
diff --git a/arch/x86/um/Kconfig b/arch/x86/um/Kconfig
index 44b12e45f9a0..5b78440a78b9 100644
--- a/arch/x86/um/Kconfig
+++ b/arch/x86/um/Kconfig
@@ -13,7 +13,7 @@ config UML_X86
select ARCH_USE_QUEUED_SPINLOCKS
select DCACHE_WORD_ACCESS
select HAVE_EFFICIENT_UNALIGNED_ACCESS
- select UML_SUBARCH_SUPPORTS_SMP if X86_CX8
+ select UML_SUBARCH_SUPPORTS_SMP
config 64BIT
bool "64-bit kernel" if "$(SUBARCH)" = "x86"
diff --git a/arch/x86/um/Makefile b/arch/x86/um/Makefile
index f9ea75bf43ac..b89936fe503a 100644
--- a/arch/x86/um/Makefile
+++ b/arch/x86/um/Makefile
@@ -19,8 +19,7 @@ ifeq ($(CONFIG_X86_32),y)
obj-y += syscalls_32.o
-subarch-y = ../lib/string_32.o ../lib/atomic64_32.o ../lib/atomic64_cx8_32.o
-subarch-y += ../lib/cmpxchg8b_emu.o ../lib/atomic64_386_32.o
+subarch-y = ../lib/string_32.o ../lib/atomic64_32.o
subarch-y += ../lib/checksum_32.o
subarch-y += ../kernel/sys_ia32.o
diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c
index d726068358c7..37af41df3e6a 100644
--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -251,15 +251,12 @@ static __init int test_atomics_init(void)
test_atomic64();
#ifdef CONFIG_X86
- pr_info("passed for %s platform %s CX8 and %s SSE\n",
+ pr_info("passed for %s platform %s SSE\n",
#ifdef CONFIG_X86_64
"x86-64",
-#elif defined(CONFIG_X86_CX8)
- "i586+",
#else
- "i386+",
+ "i586+",
#endif
- boot_cpu_has(X86_FEATURE_CX8) ? "with" : "without",
boot_cpu_has(X86_FEATURE_XMM) ? "with" : "without");
#else
pr_info("passed\n");
--
2.39.5
next prev parent reply other threads:[~2026-05-22 14:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-22 14:19 [PATCH 0/8] x86-32 CPU configuration cleanups Arnd Bergmann
2026-05-22 14:19 ` [PATCH 1/8] x86: remove ts5500 platforms support Arnd Bergmann
2026-06-01 8:31 ` Geert Uytterhoeven
2026-06-01 12:27 ` Arnd Bergmann
2026-05-22 14:19 ` [PATCH 2/8] x86: remove AMD Élan remnants Arnd Bergmann
2026-05-22 14:19 ` [PATCH 3/8] x86: make TSC usage unconditional Arnd Bergmann
2026-05-22 16:11 ` Brian Gerst
2026-05-22 14:19 ` Arnd Bergmann [this message]
2026-05-22 14:19 ` [PATCH 5/8] x86: remove dependencies on CONFIG_M... CPU options Arnd Bergmann
2026-05-22 15:46 ` Juergen Gross
2026-05-22 18:54 ` Arnd Bergmann
2026-05-22 19:00 ` Jürgen Groß
2026-05-22 21:22 ` David Laight
2026-05-22 14:19 ` [PATCH 6/8] x86: require minimum 64 byte cache lines Arnd Bergmann
2026-05-22 14:19 ` [PATCH 7/8] x86: remove dependencies on per-CPU options Arnd Bergmann
2026-05-22 14:19 ` [PATCH 8/8] x86: simplify 32-bit instruction set selection Arnd Bergmann
2026-05-22 21:33 ` David Laight
2026-05-23 8:51 ` Arnd Bergmann
2026-05-23 10:02 ` David Laight
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260522141959.1071595-5-arnd@kernel.org \
--to=arnd@kernel.org \
--cc=alexander.usyskin@intel.com \
--cc=anthony.l.nguyen@intel.com \
--cc=anton.ivanov@cambridgegreys.com \
--cc=arnd@arndb.de \
--cc=boqun@kernel.org \
--cc=boris.ostrovsky@oracle.com \
--cc=bp@alien8.de \
--cc=dave.hansen@linux.intel.com \
--cc=gary@garyguo.net \
--cc=hpa@zytor.com \
--cc=johannes@sipsolutions.net \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-um@lists.infradead.org \
--cc=linux@rasmusvillemoes.dk \
--cc=mingo@redhat.com \
--cc=peterz@infradead.org \
--cc=przemyslaw.kitszel@intel.com \
--cc=richard@nod.at \
--cc=tglx@kernel.org \
--cc=will@kernel.org \
--cc=x86@kernel.org \
--cc=yury.norov@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox