From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: References: <20170208080917.24320-1-khuey@kylehuey.com> <20170208080917.24320-9-khuey@kylehuey.com> From: Jim Mattson Date: Fri, 27 Jul 2018 13:28:41 -0700 Message-ID: Subject: Re: [PATCH v14 8/9] KVM: x86: virtualize cpuid faulting Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org To: Andy Lutomirski Cc: Kyle Huey , Robert O'Callahan , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , X86 ML , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , "Rafael J. Wysocki" , Dmitry Safonov , David Matlack , Nadav Amit , Andi Kleen , LKML , user-mode-linux-devel@lists.sourceforge.net, "open list:USER-MODE LINUX (UML)" , Linux FS Devel , "open list:KERNEL SELFTEST FRAMEWORK" , kvm list List-ID: On Fri, Jul 27, 2018 at 12:41 PM, Andy Lutomirski wrote: > On Wed, Feb 8, 2017 at 12:09 AM, Kyle Huey wrote: >> Hardware support for faulting on the cpuid instruction is not required to >> emulate it, because cpuid triggers a VM exit anyways. KVM handles the relevant >> MSRs (MSR_PLATFORM_INFO and MSR_MISC_FEATURES_ENABLE) and upon a >> cpuid-induced VM exit checks the cpuid faulting state and the CPL. >> kvm_require_cpl is even kind enough to inject the GP fault for us. >> >> Signed-off-by: Kyle Huey >> Reviewed-by: David Matlack >> --- >> ... >> @@ -7613,16 +7636,19 @@ void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) >> >> kvm_clear_async_pf_completion_queue(vcpu); >> kvm_async_pf_hash_reset(vcpu); >> vcpu->arch.apf.halted = false; >> >> if (!init_event) { >> kvm_pmu_reset(vcpu); >> vcpu->arch.smbase = 0x30000; >> + >> + vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; >> + vcpu->arch.msr_misc_features_enables = 0; > > Jim, I assume you're worried about this bit? It seems like > msr_platform_info should maybe be initialized to zero to avoid causing > an unintended migration issue. Initializing this bit to zero helps with migration, but then if the CPUID faulting bits in both MSRs are set, userspace has to take pains to ensure that MSR_PLATFORM_INFO is restored first, or the MSR_MISC_FEATURES_ENABLES value will be rejected. I'm also concerned about the 0 in the "Maximum Non-Turbo Ratio" field feeding into someone's calculated TSC frequency.