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[103.168.172.201]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8c37f540650sm62900285a.47.2026.01.05.16.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jan 2026 16:49:08 -0800 (PST) Received: from phl-compute-03.internal (phl-compute-03.internal [10.202.2.43]) by mailfauth.phl.internal (Postfix) with ESMTP id 45B0CF4006A; Mon, 5 Jan 2026 19:49:08 -0500 (EST) Received: from phl-frontend-03 ([10.202.2.162]) by phl-compute-03.internal (MEProxy); Mon, 05 Jan 2026 19:49:08 -0500 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeefgedrtddtgdelkeejkecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpuffrtefokffrpgfnqfghnecuuegr ihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjug hrpeffhffvvefukfhfgggtuggjsehttdertddttddvnecuhfhrohhmpeeuohhquhhnucfh vghnghcuoegsohhquhhnrdhfvghnghesghhmrghilhdrtghomheqnecuggftrfgrthhtvg hrnhepfeffudehveduteeuffeutdetieeftdelfeelveffffevteeffedtteehteegkeeg necuffhomhgrihhnpehkvghrnhgvlhdrohhrghdptddurdhorhhgpdhgihhthhhusgdrtg homhenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegs ohhquhhnodhmvghsmhhtphgruhhthhhpvghrshhonhgrlhhithihqdeiledvgeehtdeige dqudejjeekheehhedvqdgsohhquhhnrdhfvghngheppehgmhgrihhlrdgtohhmsehfihig mhgvrdhnrghmvgdpnhgspghrtghpthhtohepudeipdhmohguvgepshhmthhpohhuthdprh gtphhtthhopehlkhhpsehinhhtvghlrdgtohhmpdhrtghpthhtohepfhhujhhithgrrdht ohhmohhnohhrihesghhmrghilhdrtghomhdprhgtphhtthhopehllhhvmheslhhishhtsh drlhhinhhugidruggvvhdprhgtphhtthhopehovgdqkhgsuhhilhguqdgrlhhlsehlihhs thhsrdhlihhnuhigrdguvghvpdhrtghpthhtoheprhhitghhrghrugesnhhougdrrghtpd hrtghpthhtoheprghnthhonhdrihhvrghnohhvsegtrghmsghrihgughgvghhrvgihshdr tghomhdprhgtphhtthhopehjohhhrghnnhgvshesshhiphhsohhluhhtihhonhhsrdhnvg htpdhrtghpthhtohepthhglhigsehlihhnuhhtrhhonhhigidruggvpdhrtghpthhtohep mhhinhhgohesrhgvughhrghtrdgtohhm X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 5 Jan 2026 19:49:07 -0500 (EST) Date: Tue, 6 Jan 2026 08:49:05 +0800 From: Boqun Feng To: kernel test robot Cc: FUJITA Tomonori , llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , linux-um@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [boqun:rust-sync.20260105a 18/22] error[E0277]: the trait bound `i8: AtomicImpl` is not satisfied Message-ID: References: <202601060041.k0JkAkUD-lkp@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <202601060041.k0JkAkUD-lkp@intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260105_183346_710981_3BA7B172 X-CRM114-Status: GOOD ( 17.83 ) X-BeenThere: linux-um@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-um" Errors-To: linux-um-bounces+linux-um=archiver.kernel.org@lists.infradead.org [Cc UML] On Tue, Jan 06, 2026 at 12:25:24AM +0800, kernel test robot wrote: > tree: https://git.kernel.org/pub/scm/linux/kernel/git/boqun/linux.git rust-sync.20260105a > head: 243aa6a057d46d3a4de9297422e480d469eddaf7 > commit: 06ed7e7e7aa656f7054af7d3d3387a07244d85b1 [18/22] rust: sync: atomic: Add i8/i16 xchg and cmpxchg support > config: um-randconfig-001-20260105 (https://download.01.org/0day-ci/archive/20260106/202601060041.k0JkAkUD-lkp@intel.com/config) > compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710) > rustc: rustc 1.88.0 (6b00bc388 2025-06-23) > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260106/202601060041.k0JkAkUD-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot > | Closes: https://lore.kernel.org/oe-kbuild-all/202601060041.k0JkAkUD-lkp@intel.com/ > > All errors (new ones prefixed by >>): > > In file included from kernel/sched/rq-offsets.c:5: > In file included from kernel/sched/sched.h:28: > In file included from include/linux/cgroup_api.h:1: > In file included from include/linux/cgroup.h:27: > In file included from include/linux/kernel_stat.h:8: > In file included from include/linux/interrupt.h:11: > In file included from include/linux/hardirq.h:11: > In file included from arch/um/include/asm/hardirq.h:24: > In file included from include/linux/irq.h:20: > In file included from include/linux/io.h:12: > In file included from arch/um/include/asm/io.h:24: > include/asm-generic/io.h:1209:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] > 1209 | return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port; > | ~~~~~~~~~~ ^ > 1 warning generated. > llvm-nm: error: rust/helpers/helpers.o: No such file or directory > clang diag: include/asm-generic/io.h:1209:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] > clang diag: include/asm-generic/io.h:1209:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] > clang diag: include/asm-generic/io.h:1209:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] > >> error[E0277]: the trait bound `i8: AtomicImpl` is not satisfied > --> rust/kernel/sync/atomic/internal.rs:265:7 > | > 265 | [ i8 => atomic_i8, i16 => atomic_i16, i32 => atomic, i64 => atomic64 ] > | ^^ the trait `AtomicImpl` is not implemented for `i8` > | > = help: the following other types implement trait `AtomicImpl`: > i32 > i64 UML_X86 is using the atomics of x86 kernel (defined in arch/x86/include/asm/atomic*), right? If so, I think we need this: diff --git a/arch/x86/um/Kconfig b/arch/x86/um/Kconfig index bdd7c8e39b01..44b12e45f9a0 100644 --- a/arch/x86/um/Kconfig +++ b/arch/x86/um/Kconfig @@ -9,6 +9,7 @@ endmenu config UML_X86 def_bool y select ARCH_USE_QUEUED_RWLOCKS + select ARCH_SUPPORTS_ATOMIC_RMW select ARCH_USE_QUEUED_SPINLOCKS select DCACHE_WORD_ACCESS select HAVE_EFFICIENT_UNALIGNED_ACCESS Regards, Boqun [...]