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Wed, 07 Oct 2026 17:06:18 -0700 (PDT) X-Received: by 2002:a05:7022:4381:b0:149:1feb:6da4 with SMTP id a92af1059eb24-16206f07244mr6679616c88.32.1791417978106; Wed, 07 Oct 2026 17:06:18 -0700 (PDT) Received: from [192.168.1.133] ([172.88.17.160]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-16166216f39sm11898472c88.6.2026.10.07.17.06.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Oct 2026 17:06:16 -0700 (PDT) Message-ID: <0f4b331a-0c5c-41ca-ba8c-d3a4cb89900b@oss.qualcomm.com> Date: Wed, 7 Oct 2026 17:06:15 -0700 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 1/1] usb: dwc3: Clear SUSPHY before issuing core soft reset To: Thinh Nguyen Cc: "gregkh@linuxfoundation.org" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <20261002000741.450793-1-elson.serrao@oss.qualcomm.com> <20261002000741.450793-2-elson.serrao@oss.qualcomm.com> Content-Language: en-US From: Elson Serrao In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=NchzRGD4 c=1 sm=1 tr=0 ts=6ac6de7c cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=p3NwzfejtmCMKWTc25r7/Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=XizZcgsUtJyPTJarKMYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDAwMCBTYWx0ZWRfX9FrS5eS84CDR DJjfg82my18g2KoCavCjr+PxIVYNe5gFt/2Xoax/Gu/TGvs8ymVmZZsoys7IzBH/uQAWqkxq55s xhhd9ia4ieDFL9hTyD/qvpzqX0FJYts= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDAwMCBTYWx0ZWRfX1Bt3hURvgpyh 5g7PO62c2S1z9KYpB4DrHCsjn9JvOSchFproYsxcBvcZz+4q/JY0sCtz6UW5UBS4HVNBzkGVQ59 VcC/YhGWt86L94DnC1go3wr2fHtIKsmlC2beHodkkXPMM7EjFF2rhgIRxvcZk7li7T1PQtyCGBT Qu7ids29pot9/8+NdaohAfMDqbRHpP2aMeM05ddXYEzvrRDbfTqfaoeC3lHpbBN7RrYpyToQfbg tsqloav3rAxZg4HqhqNBWjNg35+1vauVd0GytkSq/q7Bqt4xKGQg+JkVeof7qL60shO1FE14/bM ngOWcyPrhsvkTAKQcsDVy5LTcsKxvdgzUAn2J82UUasOataYM0GQI+VW9TbE0Lx4pg7Ij2v8S8V 9DRk1pk7eLLr9sBfOsLrlXJdrd0LnH/QhtOat5V1MvRSOOzNLqxKHCw2guuwkJlrVWQi2M3Rhp0 R5l6AQT8c7a1qWNQqVQ== X-Proofpoint-ORIG-GUID: 3YXpPFPkLPUX-YpwbUJEHg0odR5YpgBs X-Proofpoint-GUID: 3YXpPFPkLPUX-YpwbUJEHg0odR5YpgBs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_07,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080000 On 10/1/2026 5:48 PM, Thinh Nguyen wrote: > On Thu, Oct 01, 2026, Elson Serrao wrote: >> The controller clears DCTL.CSFTRST only after all required logic has >> been reset and all PHY clocks are active. If SUSPHY remains set, the PHY >> may not be fully active during the reset sequence, causing the core soft >> reset to fail to complete. >>   >> Clear SUSPHY before asserting DCTL.CSFTRST to ensure the PHY remains >> active while the reset is in progress. >> >> Fixes: cc5bfc4e16fc ("usb: dwc3: Set SUSPENDENABLE soon after phy init") >> Signed-off-by: Elson Serrao >> --- >> drivers/usb/dwc3/core.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >> index fd5c2cd36c59..282a853c364e 100644 >> --- a/drivers/usb/dwc3/core.c >> +++ b/drivers/usb/dwc3/core.c >> @@ -332,6 +332,13 @@ int dwc3_core_soft_reset(struct dwc3 *dwc) >> if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) >> return 0; >> >> + /* >> + * The core clears DCTL.CSFTRST only after all necessary logic is >> + * reset and all PHY clocks are active/running. Clear SUSPHY before >> + * issuing the reset so that the PHY is active. >> + */ >> + dwc3_enable_susphy(dwc, false); >> + >> reg = dwc3_readl(dwc, DWC3_DCTL); >> reg |= DWC3_DCTL_CSFTRST; >> reg &= ~DWC3_DCTL_RUN_STOP; >> -- >> 2.34.1 >> > > Most platforms require SUSPHY to be set before soft reset. Can you > handle this via a pre_soft_reset() glue_ops for the affected platform > instead? > Hi Thinh,   Thank you for the feedback and suggestion. I will explore that approach further and evaluate whether a pre_soft_reset() glue_ops hook can be used.   One point I'm still trying to understand is that the programming guide states that DCTL.CSFTRST is cleared only after all PHY clocks are active/running. Based on that description, suspending the PHY during the core soft reset sequence seems somewhat counterintuitive, as reset completion appears to depend on an active PHY clock.   Am I missing something in how SUSPHY is expected to interact with the PHY clocking requirements during core soft reset?   Thanks, Elson