* [v2,3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
@ 2018-03-12 5:25 Chunfeng Yun
0 siblings, 0 replies; 5+ messages in thread
From: Chunfeng Yun @ 2018-03-12 5:25 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Matthias Brugger, Rob Herring, Mark Rutland, Ian Campbell,
Ryder Lee, Chunfeng Yun, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
Add two properties of ref_clk and coefficient used by U2 slew rate
calibrate which may vary on different SoCs
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
index 41e09ed..0d34b2b 100644
--- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
@@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
- reg : offset and length of register shared by multiple ports,
exclude port's private register. It is needed on mt2701
and mt8173, but not on mt2712.
+ - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
+ calibrate
+ - mediatek,src-coef : coefficient for slew rate calibrate, depends on
+ SoC process
Required properties (port (child) node):
- reg : address and length of the register set for the port.
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [v2,3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
@ 2018-03-13 23:21 Matthias Brugger
0 siblings, 0 replies; 5+ messages in thread
From: Matthias Brugger @ 2018-03-13 23:21 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I
Cc: Rob Herring, Mark Rutland, Ian Campbell, Ryder Lee, linux-kernel,
linux-arm-kernel, linux-usb, linux-mediatek, devicetree
On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> Add two properties of ref_clk and coefficient used by U2 slew rate
> calibrate which may vary on different SoCs
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> index 41e09ed..0d34b2b 100644
> --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> @@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
> - reg : offset and length of register shared by multiple ports,
> exclude port's private register. It is needed on mt2701
> and mt8173, but not on mt2712.
> + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
> + calibrate
> + - mediatek,src-coef : coefficient for slew rate calibrate, depends on
> + SoC process
>
> Required properties (port (child) node):
> - reg : address and length of the register set for the port.
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [v2,3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
@ 2018-03-14 6:09 Chunfeng Yun
0 siblings, 0 replies; 5+ messages in thread
From: Chunfeng Yun @ 2018-03-14 6:09 UTC (permalink / raw)
To: Matthias Brugger
Cc: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Ian Campbell,
Ryder Lee, linux-kernel, linux-arm-kernel, linux-usb,
linux-mediatek, devicetree
On Wed, 2018-03-14 at 00:21 +0100, Matthias Brugger wrote:
>
> On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> > Add two properties of ref_clk and coefficient used by U2 slew rate
> > calibrate which may vary on different SoCs
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
>
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
>
Thanks again
> > ---
> > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > index 41e09ed..0d34b2b 100644
> > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
> > - reg : offset and length of register shared by multiple ports,
> > exclude port's private register. It is needed on mt2701
> > and mt8173, but not on mt2712.
> > + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
> > + calibrate
> > + - mediatek,src-coef : coefficient for slew rate calibrate, depends on
> > + SoC process
> >
> > Required properties (port (child) node):
> > - reg : address and length of the register set for the port.
> >
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [v2,3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
@ 2018-03-18 12:48 Rob Herring
0 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2018-03-18 12:48 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Kishon Vijay Abraham I, Matthias Brugger, Mark Rutland,
Ian Campbell, Ryder Lee, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
On Mon, Mar 12, 2018 at 01:25:40PM +0800, Chunfeng Yun wrote:
> Add two properties of ref_clk and coefficient used by U2 slew rate
> calibrate which may vary on different SoCs
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> index 41e09ed..0d34b2b 100644
> --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> @@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
> - reg : offset and length of register shared by multiple ports,
> exclude port's private register. It is needed on mt2701
> and mt8173, but not on mt2712.
> + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
> + calibrate
> + - mediatek,src-coef : coefficient for slew rate calibrate, depends on
> + SoC process
What are valid values? This is one cell?
>
> Required properties (port (child) node):
> - reg : address and length of the register set for the port.
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [v2,3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
@ 2018-03-19 3:21 Chunfeng Yun
0 siblings, 0 replies; 5+ messages in thread
From: Chunfeng Yun @ 2018-03-19 3:21 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Matthias Brugger, Mark Rutland,
Ian Campbell, Ryder Lee, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
On Sun, 2018-03-18 at 07:48 -0500, Rob Herring wrote:
> On Mon, Mar 12, 2018 at 01:25:40PM +0800, Chunfeng Yun wrote:
> > Add two properties of ref_clk and coefficient used by U2 slew rate
> > calibrate which may vary on different SoCs
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > index 41e09ed..0d34b2b 100644
> > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
> > - reg : offset and length of register shared by multiple ports,
> > exclude port's private register. It is needed on mt2701
> > and mt8173, but not on mt2712.
> > + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
> > + calibrate
> > + - mediatek,src-coef : coefficient for slew rate calibrate, depends on
> > + SoC process
>
> What are valid values? This is one cell?
Yes, one cell, integer type. If need, I'll send a new patch
Thanks
>
> >
> > Required properties (port (child) node):
> > - reg : address and length of the register set for the port.
> > --
> > 1.9.1
> >
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