[v5,1/7] clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk

[v5,1/7] clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk

[Manu Gautam]

The USB and PCIE pipe clocks are sourced from external clocks
inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG
clocks is dependent on PHY initialization sequence hence
update halt_check to BRANCH_HALT_SKIP for these clocks so
that clock status bit is not polled when enabling or disabling
the clocks. It allows to simplify PHY client driver code which
is both user and source of the pipe_clk and avoid error logging
related status check on clk_disable/enable.

Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
---
 drivers/clk/qcom/gcc-msm8996.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 3d64529..b73e7f1 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -1418,6 +1418,7 @@ enum {
 
 static struct clk_branch gcc_usb3_phy_pipe_clk = {
 	.halt_reg = 0x50004,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x50004,
 		.enable_mask = BIT(0),
@@ -2472,6 +2473,7 @@ enum {
 
 static struct clk_branch gcc_pcie_0_pipe_clk = {
 	.halt_reg = 0x6b018,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x6b018,
 		.enable_mask = BIT(0),
@@ -2547,6 +2549,7 @@ enum {
 
 static struct clk_branch gcc_pcie_1_pipe_clk = {
 	.halt_reg = 0x6d018,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x6d018,
 		.enable_mask = BIT(0),
@@ -2622,6 +2625,7 @@ enum {
 
 static struct clk_branch gcc_pcie_2_pipe_clk = {
 	.halt_reg = 0x6e018,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x6e018,
 		.enable_mask = BIT(0),

[v5,1/7] clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk

[kbuild test robot]

Hi Manu,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on phy/next]
[also build test ERROR on v4.17-rc3 next-20180503]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Manu-Gautam/phy-qcom-Updates-for-USB-PHYs-on-SDM845/20180503-163006
base:   https://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

>> drivers/clk//qcom/gcc-msm8996.c:1421:16: error: 'BRANCH_HALT_SKIP' undeclared here (not in a function); did you mean 'BRANCH_HALT_VOTED'?
     .halt_check = BRANCH_HALT_SKIP,
                   ^~~~~~~~~~~~~~~~
                   BRANCH_HALT_VOTED

vim +1421 drivers/clk//qcom/gcc-msm8996.c

  1418	
  1419	static struct clk_branch gcc_usb3_phy_pipe_clk = {
  1420		.halt_reg = 0x50004,
> 1421		.halt_check = BRANCH_HALT_SKIP,
  1422		.clkr = {
  1423			.enable_reg = 0x50004,
  1424			.enable_mask = BIT(0),
  1425			.hw.init = &(struct clk_init_data){
  1426				.name = "gcc_usb3_phy_pipe_clk",
  1427				.parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
  1428				.num_parents = 1,
  1429				.flags = CLK_SET_RATE_PARENT,
  1430				.ops = &clk_branch2_ops,
  1431			},
  1432		},
  1433	};
  1434
---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[v5,1/7] clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk

[Doug Anderson]

Hi,

On Wed, May 2, 2018 at 2:06 PM, Manu Gautam <mgautam@codeaurora.org> wrote:
> The USB and PCIE pipe clocks are sourced from external clocks
> inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG
> clocks is dependent on PHY initialization sequence hence
> update halt_check to BRANCH_HALT_SKIP for these clocks so
> that clock status bit is not polled when enabling or disabling
> the clocks. It allows to simplify PHY client driver code which
> is both user and source of the pipe_clk and avoid error logging
> related status check on clk_disable/enable.
>
> Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
> ---
>  drivers/clk/qcom/gcc-msm8996.c | 4 ++++
>  1 file changed, 4 insertions(+)

FWIW this matches my understanding of what Stephen and you agreed upon.  Thus:

Reviewed-by: Douglas Anderson <dianders@chromium.org>
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[v5,1/7] clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk

[Stephen Boyd]

Quoting Manu Gautam (2018-05-02 14:06:08)
> The USB and PCIE pipe clocks are sourced from external clocks
> inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG
> clocks is dependent on PHY initialization sequence hence
> update halt_check to BRANCH_HALT_SKIP for these clocks so
> that clock status bit is not polled when enabling or disabling
> the clocks. It allows to simplify PHY client driver code which
> is both user and source of the pipe_clk and avoid error logging
> related status check on clk_disable/enable.
> 
> Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
> ---

Applied to clk-next
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