From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8534189910; Tue, 8 Oct 2024 12:59:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728392374; cv=none; b=lFn7MAxtoG5LTgdRuSbMRoYo/yqGXJlT1h38YOXsZqxB5vPOq4ebVG9wuYN7g6+Bs2x4Yx5nIrFVR/DRcL2uA3uuNWuahEzaCgumZxNjaLQDMgS0sMg5a/EduyLPQDS0SupRADZmURJL+ApoGk1tycBIl6wl1ST/unHvBOMxYAY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728392374; c=relaxed/simple; bh=S56vPNMgcKpiszKMqZFy08jLIhyiOgKXegYXxUqdUv0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=LE7vHxarIB4xGov06Wkn45nOD02gkLd9pZAwL94PKjFgU4trgVnOz38HKYm9JJ0ClCWswx9wJbr6NEStBSOj/o/nLfg/HrnqoOaJOYgK59m4DTCVIbmhc2ZtoXhfu4GYBpxe3aOU7FS+IcQ6x6BQ0Tf0CiMMiiVEujDdI3zgP5w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DGQvqiYn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DGQvqiYn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 36146C4CECC; Tue, 8 Oct 2024 12:59:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728392374; bh=S56vPNMgcKpiszKMqZFy08jLIhyiOgKXegYXxUqdUv0=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=DGQvqiYnUQqm1++vTmmeOYOgYX4yh8/Yd9XnPeelfDlbep6b6ttPpzowX8PPnjQU0 1eJDis+2dieb2WfhD9oxtXjlPnTYPsyiWfO4k1k0aHQwO3E4WqcXcYyjUKrJ4L5tb3 ezA1fOIwLMq8wP1ACqq8sdSpEonhOeZiqco1yY7p/zWOhnS+COCAE5KmXwp7n8l+ty esBIr+RP8TFK8AL0XUJzmsEFu2FYslCKpkliYQw15Zct0H7CpTSbuGiKzqXPBCYlNb wMtR4q08yzk8VprrJz/XGVNs4b04HLtTaFFD4kmKP3c5kJ/osRfDgN+9jaRM+YESmh IEXkhxhUOw8nA== Message-ID: <19bdc074-7f48-4df4-87c0-117f4cff54f0@kernel.org> Date: Tue, 8 Oct 2024 14:59:28 +0200 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: usb: dwc3: Add binding for USB Gen2 de-emphasis To: Joy Chakraborty Cc: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thinh Nguyen , Felipe Balbi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241007135508.3143756-1-joychakr@google.com> <20241007135508.3143756-2-joychakr@google.com> <1bc2c476-9d7b-4c87-924b-ecaed0f721de@kernel.org> <502d7a1f-0bac-496f-8fbe-b8924cd0ce31@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 08/10/2024 14:40, Joy Chakraborty wrote: > On Tue, Oct 8, 2024 at 5:40 PM Krzysztof Kozlowski wrote: >> >> On 08/10/2024 13:59, Joy Chakraborty wrote: >>>>> >>>>>> >>>>>>> + description: When set core will set Tx de-emphasis for USB Gen2 >>>>>> >>>>>> And why it cannot be implied by compatible? >>>>> >>>>> As per my understanding these are tuning coefficients for de-emphasis >>>>> particular to a platform and not the dwc3 controller, hence should not >>>>> be a controller compatible. >>>> >>>> Platforms must have specific compatible, so this should be implied by >>>> compatible. >>> >>> Maybe I am using the word "platform" incorrectly here, what I >>> understand is that the same controller(in a chip) when used on 2 >>> different physical form factors might need different deemphasis >> >> You mean boards? This is board-level property? > > Yes, the USB controller can be paired with different phys in a SoC and That's not board specific, but SoC. > used on different board layouts where we should be able to drive > different de-emphasis coefficients to the phy as per the link > equalization requirements is my understanding. You keep mixing different stories, so I am not convinced. > >> >>> coefficient values to be passed to its Phy. Someone could correct me >>> from the USB link stand point if I am mistaken here. >>> >> >> Then please point me to the upstream DTS boards using these properties. >> Lore link is enough, if board or DTS change is being upstreamed. >> > > The DTS change is not being upstreamed currently. Why do we want code without any user? > But this change would help bring up a new or development board where > USB compliance is being run and this parameter needs tuning, hence > being able to upstream this would help. To me whatever Google or any other vendor is doing downstream does not matter, just "does not exist". Upstream the DTS so we can verify how this is exactly used. To me it looks so far as SoC specific and your earlier comment about pairing USB controller with phy is confirming this. That's a common practice from Google (but not Chromium folks, they are awesome!) and few other vendors to upstream whatever they have in their GKI downstream, regardless whether it is right or not, whether it follows rules or not, whether there is any user or not (and again: users are upstream). Rationale for all this is the same - "we have downstream some crap thus we want it". Nah, upstream your stuff to be considered as a user. That's a NAK, sorry. Best regards, Krzysztof