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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ed1bf8e281sm1158944eec.9.2026.04.29.00.29.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Apr 2026 00:29:01 -0700 (PDT) Message-ID: <1f803f25-5f90-4f09-8634-5f27946eb295@oss.qualcomm.com> Date: Wed, 29 Apr 2026 00:28:59 -0700 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC To: Dmitry Baryshkov Cc: vkoul@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robh@kernel.org, neil.armstrong@linaro.org, gregkh@linuxfoundation.org, konrad.dybcio@oss.qualcomm.com, abel.vesa@oss.qualcomm.com, wesley.cheng@oss.qualcomm.com, krzysztof.kozlowski@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260427214217.2735240-1-ronak.raheja@oss.qualcomm.com> <20260427214217.2735240-5-ronak.raheja@oss.qualcomm.com> Content-Language: en-US From: Ronak Raheja In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=arGCzyZV c=1 sm=1 tr=0 ts=69f1b33f cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=XcaHRVNlpVRLYJM2DHQA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDA3MyBTYWx0ZWRfX4MCdYd+iG1TY IHFwveBWGAWy13R8hEy5B0ye9qk3txuQp6LFqbdzP6KSE2mRXJ5N8bny2VQYCkTfJ2mIBKduI2p J/MQE8xSUn3LifxMcjU4M5DRipzUIYvfL75Z5dsRfe4/+JzjTdUeO9oPmwBulUxguLnlxM3IVBw cdNXRKdLfI7nQ4sJI/kwiyaXxJNTbcnFYHIfwsAXPb0me8CWvD/P2BC2CTAfOyBJWDOVwdyQsXi Gu1KCKFhMtqOA9MQ9tFH3BYzpqOKXeYaoiYQkmfF28KTrhBHhMUVHUSbsQIdCdU5neMvmXiHzxf U8DPGGQKX3CmMqFZ3WWWzAnsou5XMupdxviQCTPLsc32LtoJ+weyQdz2nbbiHyqQ2giiuDWWLCV cFeLpA5f3YR+smNQi+UMSjfV8j9JWM8DPuYzOR/ysMcrq2W65d9BuwOYmskdEggApMpcd08D+F3 SEImEAg0rHWNyZfAPvw== X-Proofpoint-GUID: h7wxqeMb9TqYKeMzkmIDnu-JNfy3qFYK X-Proofpoint-ORIG-GUID: h7wxqeMb9TqYKeMzkmIDnu-JNfy3qFYK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 spamscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290073 On 4/28/2026 4:40 AM, Dmitry Baryshkov wrote: > On Mon, Apr 27, 2026 at 02:42:17PM -0700, Ronak Raheja wrote: >> Add support for the USB3-DP combo PHY found on Hawi platform. >> >> The QMP PHY for Hawi uses QSERDES V10 register layouts. Add the required >> PHY sequences from the hardware programming guide and new V10 register >> header files. Also add a new v10 offset structure to incorporate the new >> COM AON register module. > > Was this tested with the DP too or did you test only the USB part? > Only USB was tested. DP support will be added in a follow-up patch once the MDSS nodes are ready for Hawi. >> >> Signed-off-by: Ronak Raheja >> Reviewed-by: Konrad Dybcio >> --- >> .../phy/qualcomm/phy-qcom-qmp-com-aon-v10.h | 15 ++ >> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 231 +++++++++++++++++- >> .../phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h | 15 ++ >> .../phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h | 13 + >> .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h | 19 ++ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 34 +++ >> .../qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 89 +++++++ >> .../qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 89 +++++++ >> drivers/phy/qualcomm/phy-qcom-qmp.h | 5 + >> 9 files changed, 506 insertions(+), 4 deletions(-) >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h >> >> @@ -2198,6 +2368,7 @@ struct qmp_combo_offsets { >> u16 dp_txa; >> u16 dp_txb; >> u16 dp_dp_phy; >> + u16 aon_toggle; > > Are there (or will there) be any other regs? Is it just one-register > space? > The COM AON block has 3 registers: USB3_AON_TOGGLE_ENABLE (0x00), DP_AON_TOGGLE_ENABLE (0x04), and DUMMY_STATUS (0x08). Only the first two are currently used. >> }; >> >> struct qmp_phy_cfg { >> @@ -2705,6 +2895,27 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { >> .regs = qmp_v6_n4_usb3phy_regs_layout, >> }; >> >> +static const struct qmp_phy_cfg hawi_usb3dpphy_cfg = { >> + .offsets = &qmp_combo_offsets_v10, >> + >> + .serdes_tbl = hawi_usb3_serdes_tbl, >> + .serdes_tbl_num = ARRAY_SIZE(hawi_usb3_serdes_tbl), >> + .tx_tbl = hawi_usb3_tx_tbl, >> + .tx_tbl_num = ARRAY_SIZE(hawi_usb3_tx_tbl), >> + .rx_tbl = hawi_usb3_rx_tbl, >> + .rx_tbl_num = ARRAY_SIZE(hawi_usb3_rx_tbl), >> + .pcs_tbl = hawi_usb3_pcs_tbl, >> + .pcs_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_tbl), >> + .pcs_usb_tbl = hawi_usb3_pcs_usb_tbl, >> + .pcs_usb_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_usb_tbl), >> + >> + .regs = qmp_v10_usb3phy_regs_layout, >> + .reset_list = msm8996_usb3phy_reset_l, >> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), >> + .vreg_list = qmp_phy_vreg_l, >> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > > No DP counterpart and no mention of it in the commit message. > The DP configuration will be added in a follow-up patch once the MDSS nodes are ready for Hawi. Thanks, Ronak >> +}; >> + >> static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { >> .offsets = &qmp_combo_offsets_v3, >> >