* [4/4] arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs
@ 2018-09-18 8:16 Marek Szyprowski
0 siblings, 0 replies; 3+ messages in thread
From: Marek Szyprowski @ 2018-09-18 8:16 UTC (permalink / raw)
To: linux-usb, linux-samsung-soc
Cc: Marek Szyprowski, Greg Kroah-Hartman, Felipe Balbi,
Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz
Update DWC3 hardware modules to Exynos5433 specific variant: change
compatible name and add all required clocks (both to the glue node and
DWC3 core node).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 24 ++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 162653b538bc..77297d66642c 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1608,10 +1608,12 @@
};
usbdrd30: usbdrd {
- compatible = "samsung,exynos5250-dwusb3";
+ compatible = "samsung,exynos5433-dwusb3";
clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
- <&cmu_fsys CLK_SCLK_USBDRD30>;
- clock-names = "usbdrd30", "usbdrd30_susp_clk";
+ <&cmu_fsys CLK_SCLK_USBDRD30>,
+ <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
+ <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
+ clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -1619,6 +1621,10 @@
usbdrd_dwc3: dwc3@15400000 {
compatible = "snps,dwc3";
+ clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
+ <&cmu_fsys CLK_ACLK_USBDRD30>,
+ <&cmu_fsys CLK_SCLK_USBDRD30>;
+ clock-names = "ref", "bus_early", "suspend";
reg = <0x15400000 0x10000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
@@ -1655,10 +1661,12 @@
};
usbhost30: usbhost {
- compatible = "samsung,exynos5250-dwusb3";
+ compatible = "samsung,exynos5433-dwusb3";
clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
- <&cmu_fsys CLK_SCLK_USBHOST30>;
- clock-names = "usbdrd30", "usbdrd30_susp_clk";
+ <&cmu_fsys CLK_SCLK_USBHOST30>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
+ clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -1666,6 +1674,10 @@
usbhost_dwc3: dwc3@15a00000 {
compatible = "snps,dwc3";
+ clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
+ <&cmu_fsys CLK_ACLK_USBHOST30>,
+ <&cmu_fsys CLK_SCLK_USBHOST30>;
+ clock-names = "ref", "bus_early", "suspend";
reg = <0x15a00000 0x10000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [4/4] arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs
@ 2018-09-19 17:14 Krzysztof Kozlowski
0 siblings, 0 replies; 3+ messages in thread
From: Krzysztof Kozlowski @ 2018-09-19 17:14 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-usb, linux-samsung-soc, Greg Kroah-Hartman, Felipe Balbi,
Bartlomiej Zolnierkiewicz
On Tue, Sep 18, 2018 at 10:16:53AM +0200, Marek Szyprowski wrote:
> Update DWC3 hardware modules to Exynos5433 specific variant: change
> compatible name and add all required clocks (both to the glue node and
> DWC3 core node).
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 24 ++++++++++++++++------
> 1 file changed, 18 insertions(+), 6 deletions(-)
Looks okay. I understand this depends on driver changes so I will take
it for next release.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
* [4/4] arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs
@ 2018-11-13 19:25 Krzysztof Kozlowski
0 siblings, 0 replies; 3+ messages in thread
From: Krzysztof Kozlowski @ 2018-11-13 19:25 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-usb, linux-samsung-soc, Greg Kroah-Hartman, Felipe Balbi,
Bartlomiej Zolnierkiewicz
On Tue, Sep 18, 2018 at 10:16:53AM +0200, Marek Szyprowski wrote:
> Update DWC3 hardware modules to Exynos5433 specific variant: change
> compatible name and add all required clocks (both to the glue node and
> DWC3 core node).
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 24 ++++++++++++++++------
Thanks, applied.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
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