From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [V2,7/8] usb: gadget: Add UDC driver for tegra XUSB device mode controller From: Thierry Reding Message-Id: <20190503142238.GA3300@ulmo> Date: Fri, 3 May 2019 16:22:38 +0200 To: Nagarjuna Kristam Cc: balbi@kernel.org, gregkh@linuxfoundation.org, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org List-ID: T24gTW9uLCBNYXIgMTEsIDIwMTkgYXQgMDQ6NDE6NTVQTSArMDUzMCwgTmFnYXJqdW5hIEtyaXN0 YW0gd3JvdGU6Cj4gVGhpcyBwYXRjaCBhZGRzIFVEQyBkcml2ZXIgZm9yIHRlZ3JhIFhVU0IgMy4w IGRldmljZSBtb2RlIGNvbnRyb2xsZXIuCgpzL3RlZ3JhL1RlZ3JhLwoKPiBYVVNCIGRldmljZSBt b2RlIGNvbnRyb2xsZXIgc3VwcG9ydCBTUywgSFMgYW5kIEZTIG1vZGVzCgpzL3N1cHBvcnQvc3Vw cG9ydHMvIGFuZCB0ZXJtaW5hdGUgdGhlIHNlbnRlbmNlIHdpdGggYSBmdWxsLXN0b3AuCgo+IAo+ IEJhc2VkIG9uIHdvcmsgYnk6Cj4gICBNYXJrIEt1byA8bWt1b0BudmlkaWEuY29tPgo+ICAgQW5k cmV3IEJyZXN0aWNrZXIgPGFicmVzdGljQGNocm9taXVtLm9yZz4KPiAKPiBTaWduZWQtb2ZmLWJ5 OiBOYWdhcmp1bmEgS3Jpc3RhbSA8bmtyaXN0YW1AbnZpZGlhLmNvbT4KPiAtLS0KPiAgZHJpdmVy cy91c2IvZ2FkZ2V0L3VkYy9LY29uZmlnICAgICAgfCAgIDEwICsKPiAgZHJpdmVycy91c2IvZ2Fk Z2V0L3VkYy9NYWtlZmlsZSAgICAgfCAgICAxICsKPiAgZHJpdmVycy91c2IvZ2FkZ2V0L3VkYy90 ZWdyYV94dWRjLmMgfCAzNzAyICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4g IDMgZmlsZXMgY2hhbmdlZCwgMzcxMyBpbnNlcnRpb25zKCspCj4gIGNyZWF0ZSBtb2RlIDEwMDY0 NCBkcml2ZXJzL3VzYi9nYWRnZXQvdWRjL3RlZ3JhX3h1ZGMuYwo+IAo+IGRpZmYgLS1naXQgYS9k cml2ZXJzL3VzYi9nYWRnZXQvdWRjL0tjb25maWcgYi9kcml2ZXJzL3VzYi9nYWRnZXQvdWRjL0tj b25maWcKPiBpbmRleCAwYTE2Y2JkLi5mNmY0NjljIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvdXNi L2dhZGdldC91ZGMvS2NvbmZpZwo+ICsrKyBiL2RyaXZlcnMvdXNiL2dhZGdldC91ZGMvS2NvbmZp Zwo+IEBAIC00MzksNiArNDM5LDE2IEBAIGNvbmZpZyBVU0JfR0FER0VUX1hJTElOWAo+ICAJICBk eW5hbWljYWxseSBsaW5rZWQgbW9kdWxlIGNhbGxlZCAidWRjLXhpbGlueCIgYW5kIGZvcmNlIGFs bAo+ICAJICBnYWRnZXQgZHJpdmVycyB0byBhbHNvIGJlIGR5bmFtaWNhbGx5IGxpbmtlZC4KPiAg Cj4gK2NvbmZpZyBVU0JfVEVHUkFfWFVEQwo+ICsJdHJpc3RhdGUgIk5WSURJQSBTdXBlcnNwZWVk IFVTQiAzLjAgRGV2aWNlIENvbnRyb2xsZXIiCgpOVklESUEgVGVncmE/IE5vdCBzdXJlIGlmIHRo aXMgaXMgYXZhaWxhYmxlIGFueXdoZXJlIGVsc2UuCgo+ICsJZGVwZW5kcyBvbiBBUkNIX1RFR1JB Cj4gKwloZWxwCj4gKwkgRW5hYmxlcyBURUdSQSBVU0IgMy4wIGRldmljZSBtb2RlIGNvbnRyb2xs ZXIgZHJpdmVyLgoKTlZJRElBIFRlZ3JhIGhlcmUsIHRvby4KCj4gKwo+ICsJIFNheSAieSIgdG8g bGluayB0aGUgZHJpdmVyIHN0YXRpY2FsbHksIG9yICJtIiB0byBidWlsZCBhCj4gKwkgZHluYW1p Y2FsbHkgbGlua2VkIG1vZHVsZSBjYWxsZWQgInRlZ3JhX3h1ZGMiIGFuZCBmb3JjZSBhbGwKPiAr CSBnYWRnZXQgZHJpdmVycyB0byBhbHNvIGJlIGR5bmFtaWNhbGx5IGxpbmtlZC4KPiArCj4gIHNv dXJjZSAiZHJpdmVycy91c2IvZ2FkZ2V0L3VkYy9hc3BlZWQtdmh1Yi9LY29uZmlnIgo+ICAKPiAg Iwo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3VzYi9nYWRnZXQvdWRjL01ha2VmaWxlIGIvZHJpdmVy cy91c2IvZ2FkZ2V0L3VkYy9NYWtlZmlsZQo+IGluZGV4IDg5N2Y2NDguLjFjNTVjOTYgMTAwNjQ0 Cj4gLS0tIGEvZHJpdmVycy91c2IvZ2FkZ2V0L3VkYy9NYWtlZmlsZQo+ICsrKyBiL2RyaXZlcnMv dXNiL2dhZGdldC91ZGMvTWFrZWZpbGUKPiBAQCAtMjQsNiArMjQsNyBAQCBvYmotJChDT05GSUdf VVNCX0JDTTYzWFhfVURDKQkrPSBiY202M3h4X3VkYy5vCj4gIG9iai0kKENPTkZJR19VU0JfRlNM X1VTQjIpCSs9IGZzbF91c2IyX3VkYy5vCj4gIGZzbF91c2IyX3VkYy15CQkJOj0gZnNsX3VkY19j b3JlLm8KPiAgZnNsX3VzYjJfdWRjLSQoQ09ORklHX0FSQ0hfTVhDKQkrPSBmc2xfbXhjX3VkYy5v Cj4gK29iai0kKENPTkZJR19VU0JfVEVHUkFfWFVEQykJKz0gdGVncmFfeHVkYy5vCj4gIG9iai0k KENPTkZJR19VU0JfTTY2NTkyKQkrPSBtNjY1OTItdWRjLm8KPiAgb2JqLSQoQ09ORklHX1VTQl9S OEE2NjU5NykJKz0gcjhhNjY1OTctdWRjLm8KPiAgb2JqLSQoQ09ORklHX1VTQl9SRU5FU0FTX1VT QjMpCSs9IHJlbmVzYXNfdXNiMy5vCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvdXNiL2dhZGdldC91 ZGMvdGVncmFfeHVkYy5jIGIvZHJpdmVycy91c2IvZ2FkZ2V0L3VkYy90ZWdyYV94dWRjLmMKPiBu ZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAuLjcwYmVkYTAKPiAtLS0gL2Rldi9u dWxsCj4gKysrIGIvZHJpdmVycy91c2IvZ2FkZ2V0L3VkYy90ZWdyYV94dWRjLmMKPiBAQCAtMCww ICsxLDM3MDIgQEAKPiArLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjArCj4gKy8q Cj4gKyAqIE5WSURJQSBYVVNCIGRldmljZSBtb2RlIGNvbnRyb2xsZXIKCkFnYWluLCBwZXJoYXBz IG1lbnRpb24gdGhhdCB0aGlzIGlzIGZvciBUZWdyYS4KCkkgZGlkbid0IGZpbmQgYW55dGhpbmcg dGhhdCBzdG9vZCBvdXQgaW4gbW9zdCBvZiB0aGUgZHJpdmVyLiBCZWxvdyBhcmUgYQpjb3VwbGUg b2YgdGhpbmdzIHRvd2FyZHMgdGhlIGVuZCB0aGF0IEkgdGhpbmsgeW91IHNob3VsZCBsb29rIGF0 LgoKR2VuZXJhbGx5IEkgdGhvdWdodCBpdCB3YXMgZmFpcmx5IGRpZmZpY3VsdCB0byByZWFkLiBZ b3UgbWF5IHdhbnQgdG8gc2VlCmlmIHlvdSBjYW4gaW1wcm92ZSByZWFkYWJpbGl0eSBieSBhZGRp bmcgYSBiaXQgb2Ygd2hpdGVzcGFjZSB3aGVyZQphcHByb3ByaWF0ZS4gRm9yIGV4YW1wbGUsIHRy eSB0byBsZWF2ZSBhIGJsYW5rIGxpbmUgYWJvdmUgYW5kIGJlbG93CmJsb2NrIGVsZW1lbnRzLCBz dWNoIGFzIGNvbmRpdGlvbmFscyBvciBsb29wcy4gSSBmaW5kIHRoYXQgdGhhdCBoZWxwcyBhCmxv dCBpbiBtYWtpbmcgdGhlIGNvZGUgZWFzaWVyIHRvIHJlYWQuCgpTZWUgYmVsb3cgZm9yIGFuIGV4 YW1wbGUuCgpbLi4uXQo+ICtzdGF0aWMgaW50IHRlZ3JhX3h1ZGNfcHJvYmUoc3RydWN0IHBsYXRm b3JtX2RldmljZSAqcGRldikKPiArewo+ICsJc3RydWN0IHRlZ3JhX3h1ZGMgKnh1ZGM7Cj4gKwlz dHJ1Y3QgcmVzb3VyY2UgKnJlczsKPiArCXVuc2lnbmVkIGludCBpOwo+ICsJaW50IGVycjsKPiAr Cj4gKwl4dWRjID0gZGV2bV9remFsbG9jKCZwZGV2LT5kZXYsIHNpemVvZigqeHVkYyksIEdGUF9B VE9NSUMpOwo+ICsJaWYgKCF4dWRjKQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsJeHVkYy0+ZGV2 ID0gJnBkZXYtPmRldjsKPiArCXBsYXRmb3JtX3NldF9kcnZkYXRhKHBkZXYsIHh1ZGMpOwoKVGhp cywgZm9yIGV4YW1wbGUsIHdvdWxkIGJlIGVhc2llciB0byByZWFkIGFzOgoKCXh1ZGMgPSBkZXZt X2t6YWxsb2MoJnBkZXYtPmRldiwgc2l6ZW9mKCp4dWRjKSwgR0ZQX0FUT01JQyk7CglpZiAoIXh1 ZGMpCgkJcmV0dXJuIC1FTk9NRU07CgoJcGxhdGZvcm1fc2V0X2RydmRhdGEocGRldiwgeHVkYyk7 Cgl4dWRjLT5kZXYgPSAmcGRldi0+ZGV2OwoKPiArCj4gKwl4dWRjLT5zb2MgPSBvZl9kZXZpY2Vf Z2V0X21hdGNoX2RhdGEoJnBkZXYtPmRldik7Cj4gKwlpZiAoIXh1ZGMtPnNvYykKPiArCQlyZXR1 cm4gLUVOT0RFVjsKClRoaXMgc2l0dWF0aW9uIGNhbiBuZXZlciBoYXBwZW4uIFRoZSBkcml2ZXIg aXMgb25seSBldmVyIGluc3RhbnRpYXRlZApmcm9tIGRldmljZSB0cmVlLCBpbiB3aGljaCBjYXNl IHh1ZGMtPnNvYyB3aWxsIGJlIGEgdmFsaWQgcG9pbnRlciB0byB0aGUKY29ycmVjdCBTb0MgZGF0 YSBzdHJ1Y3R1cmUuCgo+ICsKPiArCXJlcyA9IHBsYXRmb3JtX2dldF9yZXNvdXJjZShwZGV2LCBJ T1JFU09VUkNFX01FTSwgMCk7Cj4gKwl4dWRjLT5iYXNlID0gZGV2bV9pb3JlbWFwX3Jlc291cmNl KCZwZGV2LT5kZXYsIHJlcyk7Cj4gKwlpZiAoSVNfRVJSKHh1ZGMtPmJhc2UpKQo+ICsJCXJldHVy biBQVFJfRVJSKHh1ZGMtPmJhc2UpOwo+ICsJeHVkYy0+cGh5c19iYXNlID0gcmVzLT5zdGFydDsK PiArCj4gKwlyZXMgPSBwbGF0Zm9ybV9nZXRfcmVzb3VyY2UocGRldiwgSU9SRVNPVVJDRV9NRU0s IDEpOwo+ICsJeHVkYy0+ZnBjaSA9IGRldm1faW9yZW1hcF9yZXNvdXJjZSgmcGRldi0+ZGV2LCBy ZXMpOwo+ICsJaWYgKElTX0VSUih4dWRjLT5mcGNpKSkKPiArCQlyZXR1cm4gUFRSX0VSUih4dWRj LT5mcGNpKTsKPiArCj4gKwlpZiAoeHVkYy0+c29jLT5oYXNfaXBmcykgewo+ICsJCXJlcyA9IHBs YXRmb3JtX2dldF9yZXNvdXJjZShwZGV2LCBJT1JFU09VUkNFX01FTSwgMik7Cj4gKwkJeHVkYy0+ aXBmcyA9IGRldm1faW9yZW1hcF9yZXNvdXJjZSgmcGRldi0+ZGV2LCByZXMpOwo+ICsJCWlmIChJ U19FUlIoeHVkYy0+aXBmcykpCj4gKwkJCXJldHVybiBQVFJfRVJSKHh1ZGMtPmlwZnMpOwo+ICsJ fQo+ICsKPiArCXh1ZGMtPmlycSA9IHBsYXRmb3JtX2dldF9pcnEocGRldiwgMCk7Cj4gKwlpZiAo eHVkYy0+aXJxIDwgMCkgewo+ICsJCWRldl9lcnIoeHVkYy0+ZGV2LCAiZmFpbGVkIHRvIGdldCBJ UlE6ICVkXG4iLAo+ICsJCQkJeHVkYy0+aXJxKTsKPiArCQlyZXR1cm4geHVkYy0+aXJxOwo+ICsJ fQo+ICsJZXJyID0gZGV2bV9yZXF1ZXN0X2lycSgmcGRldi0+ZGV2LCB4dWRjLT5pcnEsIHRlZ3Jh X3h1ZGNfaXJxLCAwLAo+ICsJCQkgICAgICAgZGV2X25hbWUoJnBkZXYtPmRldiksIHh1ZGMpOwo+ ICsJaWYgKGVyciA8IDApIHsKPiArCQlkZXZfZXJyKHh1ZGMtPmRldiwgImZhaWxlZCB0byBjbGFp bSBJUlEjJXU6ICVkXG4iLCB4dWRjLT5pcnEsCj4gKwkJCWVycik7Cj4gKwkJcmV0dXJuIGVycjsK PiArCX0KPiArCj4gKwl4dWRjLT5jbGtzID0gZGV2bV9rY2FsbG9jKCZwZGV2LT5kZXYsIHh1ZGMt PnNvYy0+bnVtX2Nsa3MsCj4gKwkJCQkgICAgICBzaXplb2YoKnh1ZGMtPmNsa3MpLCBHRlBfS0VS TkVMKTsKPiArCWlmICgheHVkYy0+Y2xrcykKPiArCQlyZXR1cm4gLUVOT01FTTsKPiArCWZvciAo aSA9IDA7IGkgPCB4dWRjLT5zb2MtPm51bV9jbGtzOyBpKyspCj4gKwkJeHVkYy0+Y2xrc1tpXS5p ZCA9IHh1ZGMtPnNvYy0+Y2xvY2tfbmFtZXNbaV07Cj4gKwllcnIgPSBkZXZtX2Nsa19idWxrX2dl dCgmcGRldi0+ZGV2LCB4dWRjLT5zb2MtPm51bV9jbGtzLAo+ICsJCQkJICAgICAgeHVkYy0+Y2xr cyk7Cj4gKwlpZiAoZXJyKSB7Cj4gKwkJZGV2X2Vycih4dWRjLT5kZXYsICJmYWlsZWQgdG8gcmVx dWVzdCBjbGtzICVkXG4iLCBlcnIpOwo+ICsJCXJldHVybiBlcnI7Cj4gKwl9Cj4gKwo+ICsJeHVk Yy0+c3VwcGxpZXMgPSBkZXZtX2tjYWxsb2MoJnBkZXYtPmRldiwgeHVkYy0+c29jLT5udW1fc3Vw cGxpZXMsCj4gKwkJCQkgICAgICBzaXplb2YoKnh1ZGMtPnN1cHBsaWVzKSwgR0ZQX0tFUk5FTCk7 Cj4gKwlpZiAoIXh1ZGMtPnN1cHBsaWVzKQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsJZm9yIChp ID0gMDsgaSA8IHh1ZGMtPnNvYy0+bnVtX3N1cHBsaWVzOyBpKyspCj4gKwkJeHVkYy0+c3VwcGxp ZXNbaV0uc3VwcGx5ID0geHVkYy0+c29jLT5zdXBwbHlfbmFtZXNbaV07Cj4gKwllcnIgPSBkZXZt X3JlZ3VsYXRvcl9idWxrX2dldCgmcGRldi0+ZGV2LCB4dWRjLT5zb2MtPm51bV9zdXBwbGllcywK PiArCQkJCSAgICAgIHh1ZGMtPnN1cHBsaWVzKTsKPiArCWlmIChlcnIpIHsKPiArCQlkZXZfZXJy KHh1ZGMtPmRldiwgImZhaWxlZCB0byByZXF1ZXN0IHJlZ3VsYXRvcnMgJWRcbiIsIGVycik7Cj4g KwkJcmV0dXJuIGVycjsKPiArCX0KPiArCj4gKwl4dWRjLT5wYWRjdGwgPSB0ZWdyYV94dXNiX3Bh ZGN0bF9nZXQoJnBkZXYtPmRldik7Cj4gKwlpZiAoSVNfRVJSKHh1ZGMtPnBhZGN0bCkpCj4gKwkJ cmV0dXJuIFBUUl9FUlIoeHVkYy0+cGFkY3RsKTsKPiArCj4gKwllcnIgPSByZWd1bGF0b3JfYnVs a19lbmFibGUoeHVkYy0+c29jLT5udW1fc3VwcGxpZXMsIHh1ZGMtPnN1cHBsaWVzKTsKPiArCWlm IChlcnIpIHsKPiArCQlkZXZfZXJyKHh1ZGMtPmRldiwgImZhaWxlZCB0byBlbmFibGUgcmVndWxh dG9ycyAlZFxuIiwgZXJyKTsKPiArCQlnb3RvIHB1dF9wYWRjdGw7Cj4gKwl9Cj4gKwo+ICsJeHVk Yy0+dXNiM19waHkgPSBkZXZtX3BoeV9vcHRpb25hbF9nZXQoJnBkZXYtPmRldiwgInVzYjMiKTsK PiArCWlmIChJU19FUlIoeHVkYy0+dXNiM19waHkpKSB7Cj4gKwkJZXJyID0gUFRSX0VSUih4dWRj LT51c2IzX3BoeSk7Cj4gKwkJZGV2X2Vycih4dWRjLT5kZXYsICJmYWlsZWQgdG8gZ2V0IHVzYjMg cGh5OiAlZFxuIiwgZXJyKTsKPiArCQlnb3RvIGRpc2FibGVfcmVndWxhdG9yOwo+ICsJfQo+ICsJ eHVkYy0+dXRtaV9waHkgPSBkZXZtX3BoeV9vcHRpb25hbF9nZXQoJnBkZXYtPmRldiwgInVzYjIi KTsKPiArCWlmIChJU19FUlIoeHVkYy0+dXRtaV9waHkpKSB7Cj4gKwkJZXJyID0gUFRSX0VSUih4 dWRjLT51dG1pX3BoeSk7Cj4gKwkJZGV2X2Vycih4dWRjLT5kZXYsICJmYWlsZWQgdG8gZ2V0IHVz YjIgcGh5OiAlZFxuIiwgZXJyKTsKPiArCQlnb3RvIGRpc2FibGVfcmVndWxhdG9yOwo+ICsJfQo+ ICsKPiArCXh1ZGMtPmRhdGFfcm9sZV9leHRjb24gPSBleHRjb25fZ2V0X2VkZXZfYnlfcGhhbmRs ZSgmcGRldi0+ZGV2LCAwKTsKPiArCWlmIChJU19FUlIoeHVkYy0+ZGF0YV9yb2xlX2V4dGNvbikp IHsKPiArCQllcnIgPSBQVFJfRVJSKHh1ZGMtPmRhdGFfcm9sZV9leHRjb24pOwo+ICsJCWRldl9l cnIoeHVkYy0+ZGV2LCAiZXh0Y29uX2dldF9lZGV2X2J5X3BoYW5kbGUgZmFpbGVkICVkXG4iLAo+ ICsJCQkJZXJyKTsKPiArCQlnb3RvIGRpc2FibGVfcmVndWxhdG9yOwo+ICsJfQo+ICsKPiArCWVy ciA9IHRlZ3JhX3h1ZGNfcG93ZXJkb21haW5faW5pdCh4dWRjKTsKPiArCWlmIChlcnIpCj4gKwkJ Z290byBwdXRfcG93ZXJkb21haW5zOwo+ICsKPiArCWVyciA9IHRlZ3JhX3h1ZGNfcGh5X2luaXQo eHVkYyk7Cj4gKwlpZiAoZXJyKQo+ICsJCWdvdG8gcHV0X3Bvd2VyZG9tYWluczsKPiArCj4gKwll cnIgPSB0ZWdyYV94dWRjX2FsbG9jX2V2ZW50X3JpbmcoeHVkYyk7Cj4gKwlpZiAoZXJyKQo+ICsJ CWdvdG8gZGlzYWJsZV9waHk7Cj4gKwo+ICsJZXJyID0gdGVncmFfeHVkY19hbGxvY19lcHMoeHVk Yyk7Cj4gKwlpZiAoZXJyKQo+ICsJCWdvdG8gZnJlZV9ldmVudF9yaW5nOwo+ICsKPiArCXNwaW5f bG9ja19pbml0KCZ4dWRjLT5sb2NrKTsKPiArCWluaXRfY29tcGxldGlvbigmeHVkYy0+ZGlzY29u bmVjdF9jb21wbGV0ZSk7Cj4gKwo+ICsJSU5JVF9XT1JLKCZ4dWRjLT5kYXRhX3JvbGVfd29yaywg dGVncmFfeHVkY19kYXRhX3JvbGVfd29yayk7Cj4gKwl4dWRjLT5kYXRhX3JvbGVfbmIubm90aWZp ZXJfY2FsbCA9IHRlZ3JhX3h1ZGNfZGF0YV9yb2xlX25vdGlmaWVyOwo+ICsJZXh0Y29uX3JlZ2lz dGVyX25vdGlmaWVyKHh1ZGMtPmRhdGFfcm9sZV9leHRjb24sIEVYVENPTl9VU0IsCj4gKwkJCQkg Jnh1ZGMtPmRhdGFfcm9sZV9uYik7Cj4gKwo+ICsJSU5JVF9ERUxBWUVEX1dPUksoJnh1ZGMtPnBs Y19yZXNldF93b3JrLCB0ZWdyYV94dWRjX3BsY19yZXNldF93b3JrKTsKPiArCj4gKwlJTklUX0RF TEFZRURfV09SSygmeHVkYy0+cG9ydF9yZXNldF93YXJfd29yaywKPiArCQkJCXRlZ3JhX3h1ZGNf cG9ydF9yZXNldF93YXJfd29yayk7Cj4gKwo+ICsJcG1fcnVudGltZV9lbmFibGUoJnBkZXYtPmRl dik7Cj4gKwo+ICsJeHVkYy0+Z2FkZ2V0Lm9wcyA9ICZ0ZWdyYV94dWRjX2dhZGdldF9vcHM7Cj4g Kwl4dWRjLT5nYWRnZXQuZXAwID0gJnh1ZGMtPmVwWzBdLnVzYl9lcDsKPiArCXh1ZGMtPmdhZGdl dC5uYW1lID0gInRlZ3JhLXh1ZGMiOwo+ICsJeHVkYy0+Z2FkZ2V0Lm1heF9zcGVlZCA9IFVTQl9T UEVFRF9TVVBFUjsKPiArCj4gKwllcnIgPSB1c2JfYWRkX2dhZGdldF91ZGMoJnBkZXYtPmRldiwg Jnh1ZGMtPmdhZGdldCk7Cj4gKwlpZiAoZXJyKSB7Cj4gKwkJZGV2X2VycigmcGRldi0+ZGV2LCAi ZmFpbGVkIHRvIGFkZCBVU0IgZ2FkZ2V0OiAlZFxuIiwgZXJyKTsKPiArCQlnb3RvIGZyZWVfZXBz Owo+ICsJfQo+ICsKPiArCXRlZ3JhX3h1ZGNfdXBkYXRlX2RhdGFfcm9sZSh4dWRjKTsKPiArCj4g KwlyZXR1cm4gMDsKPiArCj4gK2ZyZWVfZXBzOgo+ICsJdGVncmFfeHVkY19mcmVlX2Vwcyh4dWRj KTsKPiArZnJlZV9ldmVudF9yaW5nOgo+ICsJdGVncmFfeHVkY19mcmVlX2V2ZW50X3JpbmcoeHVk Yyk7Cj4gK2Rpc2FibGVfcGh5Ogo+ICsJdGVncmFfeHVkY19waHlfZXhpdCh4dWRjKTsKPiArcHV0 X3Bvd2VyZG9tYWluczoKPiArCXRlZ3JhX3h1ZGNfcG93ZXJkb21haW5fcmVtb3ZlKHh1ZGMpOwo+ ICtkaXNhYmxlX3JlZ3VsYXRvcjoKPiArCXJlZ3VsYXRvcl9idWxrX2Rpc2FibGUoeHVkYy0+c29j LT5udW1fc3VwcGxpZXMsIHh1ZGMtPnN1cHBsaWVzKTsKPiArcHV0X3BhZGN0bDoKPiArCXRlZ3Jh X3h1c2JfcGFkY3RsX3B1dCh4dWRjLT5wYWRjdGwpOwo+ICsKPiArCXJldHVybiBlcnI7Cj4gK30K PiArCj4gK3N0YXRpYyBpbnQgdGVncmFfeHVkY19yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2Rldmlj ZSAqcGRldikKPiArewo+ICsJc3RydWN0IHRlZ3JhX3h1ZGMgKnh1ZGMgPSBwbGF0Zm9ybV9nZXRf ZHJ2ZGF0YShwZGV2KTsKPiArCj4gKwlwbV9ydW50aW1lX2dldF9zeW5jKHh1ZGMtPmRldik7Cj4g Kwo+ICsJY2FuY2VsX2RlbGF5ZWRfd29yaygmeHVkYy0+cGxjX3Jlc2V0X3dvcmspOwo+ICsJaWYg KHh1ZGMtPmRhdGFfcm9sZV9leHRjb24pIHsKPiArCQlleHRjb25fdW5yZWdpc3Rlcl9ub3RpZmll cih4dWRjLT5kYXRhX3JvbGVfZXh0Y29uLCBFWFRDT05fVVNCLAo+ICsJCQkJJnh1ZGMtPmRhdGFf cm9sZV9uYik7Cj4gKwkJY2FuY2VsX3dvcmtfc3luYygmeHVkYy0+ZGF0YV9yb2xlX3dvcmspOwo+ ICsJfQo+ICsJdXNiX2RlbF9nYWRnZXRfdWRjKCZ4dWRjLT5nYWRnZXQpOwo+ICsJdGVncmFfeHVk Y19mcmVlX2Vwcyh4dWRjKTsKPiArCXRlZ3JhX3h1ZGNfZnJlZV9ldmVudF9yaW5nKHh1ZGMpOwo+ ICsJdGVncmFfeHVkY19wb3dlcmRvbWFpbl9yZW1vdmUoeHVkYyk7Cj4gKwo+ICsJcmVndWxhdG9y X2J1bGtfZGlzYWJsZSh4dWRjLT5zb2MtPm51bV9zdXBwbGllcywgeHVkYy0+c3VwcGxpZXMpOwo+ ICsKPiArCXBoeV9wb3dlcl9vZmYoeHVkYy0+dXRtaV9waHkpOwo+ICsJcGh5X3Bvd2VyX29mZih4 dWRjLT51c2IzX3BoeSk7Cj4gKwl0ZWdyYV94dWRjX3BoeV9leGl0KHh1ZGMpOwo+ICsJcG1fcnVu dGltZV9kaXNhYmxlKHh1ZGMtPmRldik7Cj4gKwlwbV9ydW50aW1lX3B1dCh4dWRjLT5kZXYpOwo+ ICsKPiArCXRlZ3JhX3h1c2JfcGFkY3RsX3B1dCh4dWRjLT5wYWRjdGwpOwo+ICsKPiArCXJldHVy biAwOwo+ICt9Cj4gKwo+ICsjaWYgSVNfRU5BQkxFRChDT05GSUdfUE1fU0xFRVApIHx8IElTX0VO QUJMRUQoQ09ORklHX1BNKQoKSSdkIGRyb3AgdGhlc2UgYW5kIGluc3RlYWQgYW5ub3RhdGUgd2l0 aCBfX21heWJlX3VudXNlZC4gV2Ugbm8gbG9uZ2VyCnN1cHBvcnQgYnVpbGRpbmcgVGVncmEgd2l0 aG91dCBQTSwgc28gdGhpcyBpcyBtb3N0bHkgYWNhZGVtaWMgYW55d2F5LgoKPiArc3RhdGljIGlu dCB0ZWdyYV94dWRjX3Bvd2VyZ2F0ZShzdHJ1Y3QgdGVncmFfeHVkYyAqeHVkYykKPiArewo+ICsJ dW5zaWduZWQgbG9uZyBmbGFnczsKPiArCj4gKwlkZXZfaW5mbyh4dWRjLT5kZXYsICJlbnRlcmlu ZyBFTFBHXG4iKTsKClRoZXJlJ3MgYSBjb3VwbGUgb2YgZGV2X2luZm8oKSBjYWxscyB0aHJvdWdo b3V0IHRoZSBkcml2ZXIgdGhhdCBJIHRoaW5rCmFyZSB0b28gbm9pc3kuIEkgdGhpbmsgbW9zdCBv ZiB0aG9zZSBzaG91bGQgYmUgZGV2X2RiZygpIHNvIHRoYXQgdXNlcnMKYXJlbid0IGJvdGhlcmVk IHdpdGggdGhlbS4gSW4gY2FzZXMgd2hlcmUgeW91IHJlYWxseSB3YW50IHRvIGhpZ2hsaWdodAph biBlcnJvciBvciBzb21ldGhpbmcsIG1ha2UgdGhlbSBkZXZfZXJyKCkgb3IgZGV2X3dhcm4oKS4K Cj4gKwlzcGluX2xvY2tfaXJxc2F2ZSgmeHVkYy0+bG9jaywgZmxhZ3MpOwo+ICsJeHVkYy0+cG93 ZXJnYXRlZCA9IHRydWU7Cj4gKwl4dWRjLT5zYXZlZF9yZWdzLmN0cmwgPSB4dWRjX3JlYWRsKHh1 ZGMsIENUUkwpOwo+ICsJeHVkYy0+c2F2ZWRfcmVncy5wb3J0cG0gPSB4dWRjX3JlYWRsKHh1ZGMs IFBPUlRQTSk7Cj4gKwl4dWRjX3dyaXRlbCh4dWRjLCAwLCBDVFJMKTsKPiArCXNwaW5fdW5sb2Nr X2lycXJlc3RvcmUoJnh1ZGMtPmxvY2ssIGZsYWdzKTsKPiArCj4gKwljbGtfYnVsa19kaXNhYmxl X3VucHJlcGFyZSh4dWRjLT5zb2MtPm51bV9jbGtzLCB4dWRjLT5jbGtzKTsKPiArCXJlZ3VsYXRv cl9idWxrX2Rpc2FibGUoeHVkYy0+c29jLT5udW1fc3VwcGxpZXMsIHh1ZGMtPnN1cHBsaWVzKTsK PiArCj4gKwlkZXZfaW5mbyh4dWRjLT5kZXYsICJlbnRlcmluZyBFTFBHIGRvbmVcbiIpOwo+ICsJ cmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgdGVncmFfeHVkY191bnBvd2VyZ2F0ZShz dHJ1Y3QgdGVncmFfeHVkYyAqeHVkYykKPiArewo+ICsJdW5zaWduZWQgbG9uZyBmbGFnczsKPiAr CWludCBlcnI7Cj4gKwo+ICsJZGV2X2luZm8oeHVkYy0+ZGV2LCAiZXhpdGluZyBFTFBHXG4iKTsK PiArCj4gKwllcnIgPSByZWd1bGF0b3JfYnVsa19lbmFibGUoeHVkYy0+c29jLT5udW1fc3VwcGxp ZXMsCj4gKwkJCXh1ZGMtPnN1cHBsaWVzKTsKPiArCWlmIChlcnIgPCAwKQo+ICsJCXJldHVybiBl cnI7Cj4gKwo+ICsKCkdyYXR1aXR1b3VzIGJsYW5rIGxpbmUuCgo+ICsJZXJyID0gY2xrX2J1bGtf cHJlcGFyZV9lbmFibGUoeHVkYy0+c29jLT5udW1fY2xrcywgeHVkYy0+Y2xrcyk7Cj4gKwlpZiAo ZXJyIDwgMCkKPiArCQlyZXR1cm4gZXJyOwo+ICsKPiArCXRlZ3JhX3h1ZGNfZnBjaV9pcGZzX2lu aXQoeHVkYyk7Cj4gKwl0ZWdyYV94dWRjX2RldmljZV9wYXJhbXNfaW5pdCh4dWRjKTsKPiArCj4g Kwl0ZWdyYV94dWRjX2luaXRfZXZlbnRfcmluZyh4dWRjKTsKPiArCXRlZ3JhX3h1ZGNfaW5pdF9l cHMoeHVkYyk7Cj4gKwo+ICsJeHVkY193cml0ZWwoeHVkYywgeHVkYy0+c2F2ZWRfcmVncy5wb3J0 cG0sIFBPUlRQTSk7Cj4gKwl4dWRjX3dyaXRlbCh4dWRjLCB4dWRjLT5zYXZlZF9yZWdzLmN0cmws IENUUkwpOwo+ICsKPiArCXNwaW5fbG9ja19pcnFzYXZlKCZ4dWRjLT5sb2NrLCBmbGFncyk7Cj4g Kwl4dWRjLT5wb3dlcmdhdGVkID0gZmFsc2U7Cj4gKwlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4 dWRjLT5sb2NrLCBmbGFncyk7Cj4gKwo+ICsJZGV2X2luZm8oeHVkYy0+ZGV2LCAiZXhpdGluZyBF TFBHIGRvbmVcbiIpOwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArI2VuZGlmCj4gKwo+ICsjaWZkZWYg Q09ORklHX1BNX1NMRUVQCj4gK3N0YXRpYyBpbnQgdGVncmFfeHVkY19zdXNwZW5kKHN0cnVjdCBk ZXZpY2UgKmRldikKPiArewo+ICsJc3RydWN0IHRlZ3JhX3h1ZGMgKnh1ZGMgPSBkZXZfZ2V0X2Ry dmRhdGEoZGV2KTsKPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gKwo+ICsJc3Bpbl9sb2NrX2ly cXNhdmUoJnh1ZGMtPmxvY2ssIGZsYWdzKTsKPiArCXh1ZGMtPnN1c3BlbmRlZCA9IHRydWU7Cj4g KwlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4dWRjLT5sb2NrLCBmbGFncyk7Cj4gKwo+ICsJaWYg KHh1ZGMtPmRhdGFfcm9sZV9leHRjb24pCj4gKwkJZmx1c2hfd29yaygmeHVkYy0+ZGF0YV9yb2xl X3dvcmspOwo+ICsKPiArCS8qIEZvcmNpYmx5IGRpc2Nvbm5lY3QgYmVmb3JlIHBvd2VyZ2F0aW5n LiAqLwo+ICsJdGVncmFfeHVkY19kZXZpY2VfbW9kZV9vZmYoeHVkYyk7Cj4gKwo+ICsJaWYgKCFw bV9ydW50aW1lX3N0YXR1c19zdXNwZW5kZWQoZGV2KSkKPiArCQl0ZWdyYV94dWRjX3Bvd2VyZ2F0 ZSh4dWRjKTsKPiArCj4gKwlwbV9ydW50aW1lX2Rpc2FibGUoZGV2KTsKPiArCj4gKwlyZXR1cm4g MDsKPiArfQo+ICsKPiArc3RhdGljIGludCB0ZWdyYV94dWRjX3Jlc3VtZShzdHJ1Y3QgZGV2aWNl ICpkZXYpCj4gK3sKPiArCXN0cnVjdCB0ZWdyYV94dWRjICp4dWRjID0gZGV2X2dldF9kcnZkYXRh KGRldik7Cj4gKwl1bnNpZ25lZCBsb25nIGZsYWdzOwo+ICsJaW50IGVycjsKPiArCj4gKwllcnIg PSB0ZWdyYV94dWRjX3VucG93ZXJnYXRlKHh1ZGMpOwo+ICsJaWYgKGVyciA8IDApCj4gKwkJcmV0 dXJuIGVycjsKPiArCj4gKwlzcGluX2xvY2tfaXJxc2F2ZSgmeHVkYy0+bG9jaywgZmxhZ3MpOwo+ ICsJeHVkYy0+c3VzcGVuZGVkID0gZmFsc2U7Cj4gKwlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4 dWRjLT5sb2NrLCBmbGFncyk7Cj4gKwo+ICsJdGVncmFfeHVkY191cGRhdGVfZGF0YV9yb2xlKHh1 ZGMpOwo+ICsKPiArCXBtX3J1bnRpbWVfZW5hYmxlKGRldik7Cj4gKwo+ICsJcmV0dXJuIDA7Cj4g K30KPiArI2VuZGlmCj4gKwo+ICsjaWZkZWYgQ09ORklHX1BNCj4gK3N0YXRpYyBpbnQgdGVncmFf eHVkY19ydW50aW1lX3N1c3BlbmQoc3RydWN0IGRldmljZSAqZGV2KQo+ICt7Cj4gKwlzdHJ1Y3Qg dGVncmFfeHVkYyAqeHVkYyA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOwo+ICsKPiArCXJldHVybiB0 ZWdyYV94dWRjX3Bvd2VyZ2F0ZSh4dWRjKTsKPiArfQo+ICsKPiArc3RhdGljIGludCB0ZWdyYV94 dWRjX3J1bnRpbWVfcmVzdW1lKHN0cnVjdCBkZXZpY2UgKmRldikKPiArewo+ICsJc3RydWN0IHRl Z3JhX3h1ZGMgKnh1ZGMgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsKPiArCj4gKwlyZXR1cm4gdGVn cmFfeHVkY191bnBvd2VyZ2F0ZSh4dWRjKTsKPiArfQo+ICsjZW5kaWYKCl9fbWF5YmVfdW51c2Vk IGZvciB0aGVzZSBhcyB3ZWxsLgoKVGhpZXJyeQoKPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg ZGV2X3BtX29wcyB0ZWdyYV94dWRjX3BtX29wcyA9IHsKPiArCVNFVF9TWVNURU1fU0xFRVBfUE1f T1BTKHRlZ3JhX3h1ZGNfc3VzcGVuZCwgdGVncmFfeHVkY19yZXN1bWUpCj4gKwlTRVRfUlVOVElN RV9QTV9PUFModGVncmFfeHVkY19ydW50aW1lX3N1c3BlbmQsCj4gKwkJCSAgIHRlZ3JhX3h1ZGNf cnVudGltZV9yZXN1bWUsIE5VTEwpCj4gK307Cj4gKwo+ICtzdGF0aWMgc3RydWN0IHBsYXRmb3Jt X2RyaXZlciB0ZWdyYV94dWRjX2RyaXZlciA9IHsKPiArCS5wcm9iZSA9IHRlZ3JhX3h1ZGNfcHJv YmUsCj4gKwkucmVtb3ZlID0gdGVncmFfeHVkY19yZW1vdmUsCj4gKwkuZHJpdmVyID0gewo+ICsJ CS5uYW1lID0gInRlZ3JhLXh1ZGMiLAo+ICsJCS5wbSA9ICZ0ZWdyYV94dWRjX3BtX29wcywKPiAr CQkub2ZfbWF0Y2hfdGFibGUgPSB0ZWdyYV94dWRjX29mX21hdGNoLAo+ICsJfSwKPiArfTsKPiAr bW9kdWxlX3BsYXRmb3JtX2RyaXZlcih0ZWdyYV94dWRjX2RyaXZlcik7Cj4gKwo+ICtNT0RVTEVf REVTQ1JJUFRJT04oIk5WSURJQSBUZWdyYSBYVVNCIERldmljZSBDb250cm9sbGVyIik7Cj4gK01P RFVMRV9BVVRIT1IoIkFuZHJldyBCcmVzdGlja2VyIDxhYnJlc3RpY0BjaHJvbWl1bS5vcmc+Iik7 Cj4gK01PRFVMRV9BVVRIT1IoIkh1aSBGdSIpOwo+ICtNT0RVTEVfTElDRU5TRSgiR1BMIHYyIik7 Cj4gLS0gCj4gMi43LjQKPgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F25C7C43219 for ; Fri, 3 May 2019 14:22:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A364B20645 for ; Fri, 3 May 2019 14:22:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i6Y49Fnq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728123AbfECOWo (ORCPT ); Fri, 3 May 2019 10:22:44 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:39266 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728099AbfECOWo (ORCPT ); Fri, 3 May 2019 10:22:44 -0400 Received: by mail-wr1-f68.google.com with SMTP id a9so8126090wrp.6; Fri, 03 May 2019 07:22:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ogKdnEbe/pHEFglrVmOM28+6NpAciAimAJdOSbWYr44=; b=i6Y49Fnq89nnXBxogUBSZpAMgz3oDyRYb0FG+mPoWqvfQeYmkWGV6/SN/VmYQX64Rq YEXkH6THBZfyApY+3v82hepkyz1dIaZxtmx84poyC5E0Dp+GyZMCQ924lDotXbCT9Xgd mikct6ZCNg5s2ziW7dmRigaYlMeUXfmEmq0De2SQR+zFoRPabUYez5/OZEnJmorHT8dN x0+lb+wBomHRl2MEcGr2/9IkiPO7INfDqDFEBXNuNCsc7naW/kaLS8Fp2VmgRjbB1Wbt D483+CLhQkM8dO3WIr5lY/uA1oOixkr2V6rqE/KApwD2x0TtEk2t6TEuxCcNUxBB6qlM km0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ogKdnEbe/pHEFglrVmOM28+6NpAciAimAJdOSbWYr44=; b=Vk4UJc/KaYapFuJI9fF1sujBhy6dlSbRaZQo+vHUAjLQLMTgdCLHByaFhNeVOqqQaE Mc2yAigTj9DGg8EjswBPLzAbYGPFT1mexVgayzlD/ggHwlJ4Y/0hovWU4HGI0EYiEJ0w gUPpIBkZWVBPpMfeAdpnmZIZ17RChc2Dccd5lvxzO6Wv+oxXjO/Il1HgbHlvtX6Xkaof tH0GiMHrQtJ0FcQzQINmvOu2vK3PEfU1Y2RhWM+WwRlyKhXX61/1JcsypySJiYBLXvnk akUtD2LKHhCMJh2+AFB0Wau2jr9OSE6j5hDIb3WGhnqWfDZhYV7bKjQNz51c2UOWiGBR WVJQ== X-Gm-Message-State: APjAAAUdI/KmPRoJcl9z5bTt7iDqBtwCUkixIW4K5werGLCUWvmKHvRg Trrmw9RZXLrlZLL25VDlDZI= X-Google-Smtp-Source: APXvYqxTkhc5AqEJXUIeP9z8fy01Ql2lWDTkqWSGbbR3va6ZVfaU/zP6v21NkCDx3PNrkpVVSrDMdg== X-Received: by 2002:a5d:6341:: with SMTP id b1mr7291477wrw.28.1556893361488; Fri, 03 May 2019 07:22:41 -0700 (PDT) Received: from localhost (p2E5BEF36.dip0.t-ipconnect.de. [46.91.239.54]) by smtp.gmail.com with ESMTPSA id o16sm2806808wro.63.2019.05.03.07.22.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 May 2019 07:22:40 -0700 (PDT) Date: Fri, 3 May 2019 16:22:38 +0200 From: Thierry Reding To: Nagarjuna Kristam Cc: balbi@kernel.org, gregkh@linuxfoundation.org, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org Subject: Re: [PATCH V2 7/8] usb: gadget: Add UDC driver for tegra XUSB device mode controller Message-ID: <20190503142238.GA3300@ulmo> References: <1552302716-18554-1-git-send-email-nkristam@nvidia.com> <1552302716-18554-8-git-send-email-nkristam@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ZGiS0Q5IWpPtfppv" Content-Disposition: inline In-Reply-To: <1552302716-18554-8-git-send-email-nkristam@nvidia.com> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Message-ID: <20190503142238.1eci08R--JLCiRVUz1SI3HvIjfL97FT3tetXipRApoI@z> --ZGiS0Q5IWpPtfppv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Mar 11, 2019 at 04:41:55PM +0530, Nagarjuna Kristam wrote: > This patch adds UDC driver for tegra XUSB 3.0 device mode controller. s/tegra/Tegra/ > XUSB device mode controller support SS, HS and FS modes s/support/supports/ and terminate the sentence with a full-stop. >=20 > Based on work by: > Mark Kuo > Andrew Bresticker >=20 > Signed-off-by: Nagarjuna Kristam > --- > drivers/usb/gadget/udc/Kconfig | 10 + > drivers/usb/gadget/udc/Makefile | 1 + > drivers/usb/gadget/udc/tegra_xudc.c | 3702 +++++++++++++++++++++++++++++= ++++++ > 3 files changed, 3713 insertions(+) > create mode 100644 drivers/usb/gadget/udc/tegra_xudc.c >=20 > diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kcon= fig > index 0a16cbd..f6f469c 100644 > --- a/drivers/usb/gadget/udc/Kconfig > +++ b/drivers/usb/gadget/udc/Kconfig > @@ -439,6 +439,16 @@ config USB_GADGET_XILINX > dynamically linked module called "udc-xilinx" and force all > gadget drivers to also be dynamically linked. > =20 > +config USB_TEGRA_XUDC > + tristate "NVIDIA Superspeed USB 3.0 Device Controller" NVIDIA Tegra? Not sure if this is available anywhere else. > + depends on ARCH_TEGRA > + help > + Enables TEGRA USB 3.0 device mode controller driver. NVIDIA Tegra here, too. > + > + Say "y" to link the driver statically, or "m" to build a > + dynamically linked module called "tegra_xudc" and force all > + gadget drivers to also be dynamically linked. > + > source "drivers/usb/gadget/udc/aspeed-vhub/Kconfig" > =20 > # > diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Mak= efile > index 897f648..1c55c96 100644 > --- a/drivers/usb/gadget/udc/Makefile > +++ b/drivers/usb/gadget/udc/Makefile > @@ -24,6 +24,7 @@ obj-$(CONFIG_USB_BCM63XX_UDC) +=3D bcm63xx_udc.o > obj-$(CONFIG_USB_FSL_USB2) +=3D fsl_usb2_udc.o > fsl_usb2_udc-y :=3D fsl_udc_core.o > fsl_usb2_udc-$(CONFIG_ARCH_MXC) +=3D fsl_mxc_udc.o > +obj-$(CONFIG_USB_TEGRA_XUDC) +=3D tegra_xudc.o > obj-$(CONFIG_USB_M66592) +=3D m66592-udc.o > obj-$(CONFIG_USB_R8A66597) +=3D r8a66597-udc.o > obj-$(CONFIG_USB_RENESAS_USB3) +=3D renesas_usb3.o > diff --git a/drivers/usb/gadget/udc/tegra_xudc.c b/drivers/usb/gadget/udc= /tegra_xudc.c > new file mode 100644 > index 0000000..70beda0 > --- /dev/null > +++ b/drivers/usb/gadget/udc/tegra_xudc.c > @@ -0,0 +1,3702 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * NVIDIA XUSB device mode controller Again, perhaps mention that this is for Tegra. I didn't find anything that stood out in most of the driver. Below are a couple of things towards the end that I think you should look at. Generally I thought it was fairly difficult to read. You may want to see if you can improve readability by adding a bit of whitespace where appropriate. For example, try to leave a blank line above and below block elements, such as conditionals or loops. I find that that helps a lot in making the code easier to read. See below for an example. [...] > +static int tegra_xudc_probe(struct platform_device *pdev) > +{ > + struct tegra_xudc *xudc; > + struct resource *res; > + unsigned int i; > + int err; > + > + xudc =3D devm_kzalloc(&pdev->dev, sizeof(*xudc), GFP_ATOMIC); > + if (!xudc) > + return -ENOMEM; > + xudc->dev =3D &pdev->dev; > + platform_set_drvdata(pdev, xudc); This, for example, would be easier to read as: xudc =3D devm_kzalloc(&pdev->dev, sizeof(*xudc), GFP_ATOMIC); if (!xudc) return -ENOMEM; platform_set_drvdata(pdev, xudc); xudc->dev =3D &pdev->dev; > + > + xudc->soc =3D of_device_get_match_data(&pdev->dev); > + if (!xudc->soc) > + return -ENODEV; This situation can never happen. The driver is only ever instantiated =66rom device tree, in which case xudc->soc will be a valid pointer to the correct SoC data structure. > + > + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > + xudc->base =3D devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(xudc->base)) > + return PTR_ERR(xudc->base); > + xudc->phys_base =3D res->start; > + > + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 1); > + xudc->fpci =3D devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(xudc->fpci)) > + return PTR_ERR(xudc->fpci); > + > + if (xudc->soc->has_ipfs) { > + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 2); > + xudc->ipfs =3D devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(xudc->ipfs)) > + return PTR_ERR(xudc->ipfs); > + } > + > + xudc->irq =3D platform_get_irq(pdev, 0); > + if (xudc->irq < 0) { > + dev_err(xudc->dev, "failed to get IRQ: %d\n", > + xudc->irq); > + return xudc->irq; > + } > + err =3D devm_request_irq(&pdev->dev, xudc->irq, tegra_xudc_irq, 0, > + dev_name(&pdev->dev), xudc); > + if (err < 0) { > + dev_err(xudc->dev, "failed to claim IRQ#%u: %d\n", xudc->irq, > + err); > + return err; > + } > + > + xudc->clks =3D devm_kcalloc(&pdev->dev, xudc->soc->num_clks, > + sizeof(*xudc->clks), GFP_KERNEL); > + if (!xudc->clks) > + return -ENOMEM; > + for (i =3D 0; i < xudc->soc->num_clks; i++) > + xudc->clks[i].id =3D xudc->soc->clock_names[i]; > + err =3D devm_clk_bulk_get(&pdev->dev, xudc->soc->num_clks, > + xudc->clks); > + if (err) { > + dev_err(xudc->dev, "failed to request clks %d\n", err); > + return err; > + } > + > + xudc->supplies =3D devm_kcalloc(&pdev->dev, xudc->soc->num_supplies, > + sizeof(*xudc->supplies), GFP_KERNEL); > + if (!xudc->supplies) > + return -ENOMEM; > + for (i =3D 0; i < xudc->soc->num_supplies; i++) > + xudc->supplies[i].supply =3D xudc->soc->supply_names[i]; > + err =3D devm_regulator_bulk_get(&pdev->dev, xudc->soc->num_supplies, > + xudc->supplies); > + if (err) { > + dev_err(xudc->dev, "failed to request regulators %d\n", err); > + return err; > + } > + > + xudc->padctl =3D tegra_xusb_padctl_get(&pdev->dev); > + if (IS_ERR(xudc->padctl)) > + return PTR_ERR(xudc->padctl); > + > + err =3D regulator_bulk_enable(xudc->soc->num_supplies, xudc->supplies); > + if (err) { > + dev_err(xudc->dev, "failed to enable regulators %d\n", err); > + goto put_padctl; > + } > + > + xudc->usb3_phy =3D devm_phy_optional_get(&pdev->dev, "usb3"); > + if (IS_ERR(xudc->usb3_phy)) { > + err =3D PTR_ERR(xudc->usb3_phy); > + dev_err(xudc->dev, "failed to get usb3 phy: %d\n", err); > + goto disable_regulator; > + } > + xudc->utmi_phy =3D devm_phy_optional_get(&pdev->dev, "usb2"); > + if (IS_ERR(xudc->utmi_phy)) { > + err =3D PTR_ERR(xudc->utmi_phy); > + dev_err(xudc->dev, "failed to get usb2 phy: %d\n", err); > + goto disable_regulator; > + } > + > + xudc->data_role_extcon =3D extcon_get_edev_by_phandle(&pdev->dev, 0); > + if (IS_ERR(xudc->data_role_extcon)) { > + err =3D PTR_ERR(xudc->data_role_extcon); > + dev_err(xudc->dev, "extcon_get_edev_by_phandle failed %d\n", > + err); > + goto disable_regulator; > + } > + > + err =3D tegra_xudc_powerdomain_init(xudc); > + if (err) > + goto put_powerdomains; > + > + err =3D tegra_xudc_phy_init(xudc); > + if (err) > + goto put_powerdomains; > + > + err =3D tegra_xudc_alloc_event_ring(xudc); > + if (err) > + goto disable_phy; > + > + err =3D tegra_xudc_alloc_eps(xudc); > + if (err) > + goto free_event_ring; > + > + spin_lock_init(&xudc->lock); > + init_completion(&xudc->disconnect_complete); > + > + INIT_WORK(&xudc->data_role_work, tegra_xudc_data_role_work); > + xudc->data_role_nb.notifier_call =3D tegra_xudc_data_role_notifier; > + extcon_register_notifier(xudc->data_role_extcon, EXTCON_USB, > + &xudc->data_role_nb); > + > + INIT_DELAYED_WORK(&xudc->plc_reset_work, tegra_xudc_plc_reset_work); > + > + INIT_DELAYED_WORK(&xudc->port_reset_war_work, > + tegra_xudc_port_reset_war_work); > + > + pm_runtime_enable(&pdev->dev); > + > + xudc->gadget.ops =3D &tegra_xudc_gadget_ops; > + xudc->gadget.ep0 =3D &xudc->ep[0].usb_ep; > + xudc->gadget.name =3D "tegra-xudc"; > + xudc->gadget.max_speed =3D USB_SPEED_SUPER; > + > + err =3D usb_add_gadget_udc(&pdev->dev, &xudc->gadget); > + if (err) { > + dev_err(&pdev->dev, "failed to add USB gadget: %d\n", err); > + goto free_eps; > + } > + > + tegra_xudc_update_data_role(xudc); > + > + return 0; > + > +free_eps: > + tegra_xudc_free_eps(xudc); > +free_event_ring: > + tegra_xudc_free_event_ring(xudc); > +disable_phy: > + tegra_xudc_phy_exit(xudc); > +put_powerdomains: > + tegra_xudc_powerdomain_remove(xudc); > +disable_regulator: > + regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies); > +put_padctl: > + tegra_xusb_padctl_put(xudc->padctl); > + > + return err; > +} > + > +static int tegra_xudc_remove(struct platform_device *pdev) > +{ > + struct tegra_xudc *xudc =3D platform_get_drvdata(pdev); > + > + pm_runtime_get_sync(xudc->dev); > + > + cancel_delayed_work(&xudc->plc_reset_work); > + if (xudc->data_role_extcon) { > + extcon_unregister_notifier(xudc->data_role_extcon, EXTCON_USB, > + &xudc->data_role_nb); > + cancel_work_sync(&xudc->data_role_work); > + } > + usb_del_gadget_udc(&xudc->gadget); > + tegra_xudc_free_eps(xudc); > + tegra_xudc_free_event_ring(xudc); > + tegra_xudc_powerdomain_remove(xudc); > + > + regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies); > + > + phy_power_off(xudc->utmi_phy); > + phy_power_off(xudc->usb3_phy); > + tegra_xudc_phy_exit(xudc); > + pm_runtime_disable(xudc->dev); > + pm_runtime_put(xudc->dev); > + > + tegra_xusb_padctl_put(xudc->padctl); > + > + return 0; > +} > + > +#if IS_ENABLED(CONFIG_PM_SLEEP) || IS_ENABLED(CONFIG_PM) I'd drop these and instead annotate with __maybe_unused. We no longer support building Tegra without PM, so this is mostly academic anyway. > +static int tegra_xudc_powergate(struct tegra_xudc *xudc) > +{ > + unsigned long flags; > + > + dev_info(xudc->dev, "entering ELPG\n"); There's a couple of dev_info() calls throughout the driver that I think are too noisy. I think most of those should be dev_dbg() so that users aren't bothered with them. In cases where you really want to highlight an error or something, make them dev_err() or dev_warn(). > + spin_lock_irqsave(&xudc->lock, flags); > + xudc->powergated =3D true; > + xudc->saved_regs.ctrl =3D xudc_readl(xudc, CTRL); > + xudc->saved_regs.portpm =3D xudc_readl(xudc, PORTPM); > + xudc_writel(xudc, 0, CTRL); > + spin_unlock_irqrestore(&xudc->lock, flags); > + > + clk_bulk_disable_unprepare(xudc->soc->num_clks, xudc->clks); > + regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies); > + > + dev_info(xudc->dev, "entering ELPG done\n"); > + return 0; > +} > + > +static int tegra_xudc_unpowergate(struct tegra_xudc *xudc) > +{ > + unsigned long flags; > + int err; > + > + dev_info(xudc->dev, "exiting ELPG\n"); > + > + err =3D regulator_bulk_enable(xudc->soc->num_supplies, > + xudc->supplies); > + if (err < 0) > + return err; > + > + Gratuituous blank line. > + err =3D clk_bulk_prepare_enable(xudc->soc->num_clks, xudc->clks); > + if (err < 0) > + return err; > + > + tegra_xudc_fpci_ipfs_init(xudc); > + tegra_xudc_device_params_init(xudc); > + > + tegra_xudc_init_event_ring(xudc); > + tegra_xudc_init_eps(xudc); > + > + xudc_writel(xudc, xudc->saved_regs.portpm, PORTPM); > + xudc_writel(xudc, xudc->saved_regs.ctrl, CTRL); > + > + spin_lock_irqsave(&xudc->lock, flags); > + xudc->powergated =3D false; > + spin_unlock_irqrestore(&xudc->lock, flags); > + > + dev_info(xudc->dev, "exiting ELPG done\n"); > + return 0; > +} > +#endif > + > +#ifdef CONFIG_PM_SLEEP > +static int tegra_xudc_suspend(struct device *dev) > +{ > + struct tegra_xudc *xudc =3D dev_get_drvdata(dev); > + unsigned long flags; > + > + spin_lock_irqsave(&xudc->lock, flags); > + xudc->suspended =3D true; > + spin_unlock_irqrestore(&xudc->lock, flags); > + > + if (xudc->data_role_extcon) > + flush_work(&xudc->data_role_work); > + > + /* Forcibly disconnect before powergating. */ > + tegra_xudc_device_mode_off(xudc); > + > + if (!pm_runtime_status_suspended(dev)) > + tegra_xudc_powergate(xudc); > + > + pm_runtime_disable(dev); > + > + return 0; > +} > + > +static int tegra_xudc_resume(struct device *dev) > +{ > + struct tegra_xudc *xudc =3D dev_get_drvdata(dev); > + unsigned long flags; > + int err; > + > + err =3D tegra_xudc_unpowergate(xudc); > + if (err < 0) > + return err; > + > + spin_lock_irqsave(&xudc->lock, flags); > + xudc->suspended =3D false; > + spin_unlock_irqrestore(&xudc->lock, flags); > + > + tegra_xudc_update_data_role(xudc); > + > + pm_runtime_enable(dev); > + > + return 0; > +} > +#endif > + > +#ifdef CONFIG_PM > +static int tegra_xudc_runtime_suspend(struct device *dev) > +{ > + struct tegra_xudc *xudc =3D dev_get_drvdata(dev); > + > + return tegra_xudc_powergate(xudc); > +} > + > +static int tegra_xudc_runtime_resume(struct device *dev) > +{ > + struct tegra_xudc *xudc =3D dev_get_drvdata(dev); > + > + return tegra_xudc_unpowergate(xudc); > +} > +#endif __maybe_unused for these as well. Thierry > + > +static const struct dev_pm_ops tegra_xudc_pm_ops =3D { > + SET_SYSTEM_SLEEP_PM_OPS(tegra_xudc_suspend, tegra_xudc_resume) > + SET_RUNTIME_PM_OPS(tegra_xudc_runtime_suspend, > + tegra_xudc_runtime_resume, NULL) > +}; > + > +static struct platform_driver tegra_xudc_driver =3D { > + .probe =3D tegra_xudc_probe, > + .remove =3D tegra_xudc_remove, > + .driver =3D { > + .name =3D "tegra-xudc", > + .pm =3D &tegra_xudc_pm_ops, > + .of_match_table =3D tegra_xudc_of_match, > + }, > +}; > +module_platform_driver(tegra_xudc_driver); > + > +MODULE_DESCRIPTION("NVIDIA Tegra XUSB Device Controller"); > +MODULE_AUTHOR("Andrew Bresticker "); > +MODULE_AUTHOR("Hui Fu"); > +MODULE_LICENSE("GPL v2"); > --=20 > 2.7.4 >=20 --ZGiS0Q5IWpPtfppv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlzMTqsACgkQ3SOs138+ s6FLTxAAmZTAyHmU3BK8Hr2P5Iu8+hKx2TEH1GK8Iz0HX0ET4EZHWN0dcSKFhJyM c3N+u/tdwo8tQ7RbYOvfPipL9fOipKjkju9q4pZspoFbepi1o8kzFfnManolvFly mhtPz7jVCat48bBPrI64g2ec3DmG27ohpcfCuS9TP3evdQ7p2XMPwDXqxlXyQLm0 2PbFI9olRgoxaulJa7Yu0kgXwHrm0rfc8VSVQikUTa9kKJHdKn9Yi/UPr69J+6L5 Vfo4AQqiHvps2DrCGmkXjHfCvjPU8hvyUI/jw62DFJhEGe5KiEGGnMe7BMaNwlGX 0R8TbbsKO/eIuHs92JR0aV4VkvwQIcmM4ZjGoNZf95lDLUQZH+UvT6iYstT3paAx F3HuzPpEqWUFnRrtVU4HH/iBQP5PoAAJaVIxnO+cIlhEDeA5PdbxXclovMd6MPmO Ky24zL5xKrjd0PXQkEH0QDhndXwXfEgikT3cgAwY0/Lzmtzqd9NNsPmM1WmHV0cF YqhKvYj7lpIV+88C4LE9oQfWuNSZ9eRgM2z2qW0qtneOWR2Pvf4D7eKYzyP0htYl MzqtLT8HQwsOXN0MdS4Yft5+7552bkYnhg2ROu5I6HJdZ73RDJdLENjZUaLODVu+ WiibrEXljjzaWXaxBPj2ATrnVcLVoQti3kUKSg2YVpZz9TiZ9xo= =BciV -----END PGP SIGNATURE----- --ZGiS0Q5IWpPtfppv--